Revision 3376f415 target-sh4/translate.c
| b/target-sh4/translate.c | ||
|---|---|---|
| 464 | 464 |
{
|
| 465 | 465 |
TCGv addr = tcg_temp_new(); |
| 466 | 466 |
tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); |
| 467 |
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
|
|
| 467 |
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
|
|
| 468 | 468 |
tcg_temp_free(addr); |
| 469 | 469 |
} |
| 470 | 470 |
return; |
| ... | ... | |
| 472 | 472 |
{
|
| 473 | 473 |
TCGv addr = tcg_temp_new(); |
| 474 | 474 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 4); |
| 475 |
tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
|
|
| 475 |
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
|
|
| 476 | 476 |
tcg_temp_free(addr); |
| 477 | 477 |
} |
| 478 | 478 |
return; |
| ... | ... | |
| 482 | 482 |
case 0x9000: /* mov.w @(disp,PC),Rn */ |
| 483 | 483 |
{
|
| 484 | 484 |
TCGv addr = tcg_const_i32(ctx->pc + 4 + B7_0 * 2); |
| 485 |
tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
|
|
| 485 |
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
|
|
| 486 | 486 |
tcg_temp_free(addr); |
| 487 | 487 |
} |
| 488 | 488 |
return; |
| 489 | 489 |
case 0xd000: /* mov.l @(disp,PC),Rn */ |
| 490 | 490 |
{
|
| 491 | 491 |
TCGv addr = tcg_const_i32((ctx->pc + 4 + B7_0 * 4) & ~3); |
| 492 |
tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
|
|
| 492 |
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
|
|
| 493 | 493 |
tcg_temp_free(addr); |
| 494 | 494 |
} |
| 495 | 495 |
return; |
| ... | ... | |
| 516 | 516 |
tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); |
| 517 | 517 |
return; |
| 518 | 518 |
case 0x2000: /* mov.b Rm,@Rn */ |
| 519 |
tcg_gen_qemu_st8(REG(B7_4), REG(B11_8), ctx->memidx);
|
|
| 519 |
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB);
|
|
| 520 | 520 |
return; |
| 521 | 521 |
case 0x2001: /* mov.w Rm,@Rn */ |
| 522 |
tcg_gen_qemu_st16(REG(B7_4), REG(B11_8), ctx->memidx);
|
|
| 522 |
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW);
|
|
| 523 | 523 |
return; |
| 524 | 524 |
case 0x2002: /* mov.l Rm,@Rn */ |
| 525 |
tcg_gen_qemu_st32(REG(B7_4), REG(B11_8), ctx->memidx);
|
|
| 525 |
tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL);
|
|
| 526 | 526 |
return; |
| 527 | 527 |
case 0x6000: /* mov.b @Rm,Rn */ |
| 528 |
tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
|
|
| 528 |
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
|
|
| 529 | 529 |
return; |
| 530 | 530 |
case 0x6001: /* mov.w @Rm,Rn */ |
| 531 |
tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
|
|
| 531 |
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
|
|
| 532 | 532 |
return; |
| 533 | 533 |
case 0x6002: /* mov.l @Rm,Rn */ |
| 534 |
tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
|
|
| 534 |
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
|
|
| 535 | 535 |
return; |
| 536 | 536 |
case 0x2004: /* mov.b Rm,@-Rn */ |
| 537 | 537 |
{
|
| 538 | 538 |
TCGv addr = tcg_temp_new(); |
| 539 | 539 |
tcg_gen_subi_i32(addr, REG(B11_8), 1); |
| 540 |
tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx); /* might cause re-execution */ |
|
| 540 |
/* might cause re-execution */ |
|
| 541 |
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB); |
|
| 541 | 542 |
tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */ |
| 542 | 543 |
tcg_temp_free(addr); |
| 543 | 544 |
} |
| ... | ... | |
| 546 | 547 |
{
|
| 547 | 548 |
TCGv addr = tcg_temp_new(); |
| 548 | 549 |
tcg_gen_subi_i32(addr, REG(B11_8), 2); |
| 549 |
tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
|
|
| 550 |
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
|
|
| 550 | 551 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 551 | 552 |
tcg_temp_free(addr); |
| 552 | 553 |
} |
| ... | ... | |
| 555 | 556 |
{
|
| 556 | 557 |
TCGv addr = tcg_temp_new(); |
| 557 | 558 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 558 |
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
|
|
| 559 |
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
|
|
| 559 | 560 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 560 | 561 |
} |
| 561 | 562 |
return; |
| 562 | 563 |
case 0x6004: /* mov.b @Rm+,Rn */ |
| 563 |
tcg_gen_qemu_ld8s(REG(B11_8), REG(B7_4), ctx->memidx);
|
|
| 564 |
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB);
|
|
| 564 | 565 |
if ( B11_8 != B7_4 ) |
| 565 | 566 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 1); |
| 566 | 567 |
return; |
| 567 | 568 |
case 0x6005: /* mov.w @Rm+,Rn */ |
| 568 |
tcg_gen_qemu_ld16s(REG(B11_8), REG(B7_4), ctx->memidx);
|
|
| 569 |
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW);
|
|
| 569 | 570 |
if ( B11_8 != B7_4 ) |
| 570 | 571 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 2); |
| 571 | 572 |
return; |
| 572 | 573 |
case 0x6006: /* mov.l @Rm+,Rn */ |
| 573 |
tcg_gen_qemu_ld32s(REG(B11_8), REG(B7_4), ctx->memidx);
|
|
| 574 |
tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL);
|
|
| 574 | 575 |
if ( B11_8 != B7_4 ) |
| 575 | 576 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
| 576 | 577 |
return; |
| ... | ... | |
| 578 | 579 |
{
|
| 579 | 580 |
TCGv addr = tcg_temp_new(); |
| 580 | 581 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 581 |
tcg_gen_qemu_st8(REG(B7_4), addr, ctx->memidx);
|
|
| 582 |
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_UB);
|
|
| 582 | 583 |
tcg_temp_free(addr); |
| 583 | 584 |
} |
| 584 | 585 |
return; |
| ... | ... | |
| 586 | 587 |
{
|
| 587 | 588 |
TCGv addr = tcg_temp_new(); |
| 588 | 589 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 589 |
tcg_gen_qemu_st16(REG(B7_4), addr, ctx->memidx);
|
|
| 590 |
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUW);
|
|
| 590 | 591 |
tcg_temp_free(addr); |
| 591 | 592 |
} |
| 592 | 593 |
return; |
| ... | ... | |
| 594 | 595 |
{
|
| 595 | 596 |
TCGv addr = tcg_temp_new(); |
| 596 | 597 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 597 |
tcg_gen_qemu_st32(REG(B7_4), addr, ctx->memidx);
|
|
| 598 |
tcg_gen_qemu_st_i32(REG(B7_4), addr, ctx->memidx, MO_TEUL);
|
|
| 598 | 599 |
tcg_temp_free(addr); |
| 599 | 600 |
} |
| 600 | 601 |
return; |
| ... | ... | |
| 602 | 603 |
{
|
| 603 | 604 |
TCGv addr = tcg_temp_new(); |
| 604 | 605 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 605 |
tcg_gen_qemu_ld8s(REG(B11_8), addr, ctx->memidx);
|
|
| 606 |
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_SB);
|
|
| 606 | 607 |
tcg_temp_free(addr); |
| 607 | 608 |
} |
| 608 | 609 |
return; |
| ... | ... | |
| 610 | 611 |
{
|
| 611 | 612 |
TCGv addr = tcg_temp_new(); |
| 612 | 613 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 613 |
tcg_gen_qemu_ld16s(REG(B11_8), addr, ctx->memidx);
|
|
| 614 |
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW);
|
|
| 614 | 615 |
tcg_temp_free(addr); |
| 615 | 616 |
} |
| 616 | 617 |
return; |
| ... | ... | |
| 618 | 619 |
{
|
| 619 | 620 |
TCGv addr = tcg_temp_new(); |
| 620 | 621 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 621 |
tcg_gen_qemu_ld32s(REG(B11_8), addr, ctx->memidx);
|
|
| 622 |
tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL);
|
|
| 622 | 623 |
tcg_temp_free(addr); |
| 623 | 624 |
} |
| 624 | 625 |
return; |
| ... | ... | |
| 767 | 768 |
{
|
| 768 | 769 |
TCGv arg0, arg1; |
| 769 | 770 |
arg0 = tcg_temp_new(); |
| 770 |
tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
|
|
| 771 |
tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL);
|
|
| 771 | 772 |
arg1 = tcg_temp_new(); |
| 772 |
tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
|
|
| 773 |
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL);
|
|
| 773 | 774 |
gen_helper_macl(cpu_env, arg0, arg1); |
| 774 | 775 |
tcg_temp_free(arg1); |
| 775 | 776 |
tcg_temp_free(arg0); |
| ... | ... | |
| 781 | 782 |
{
|
| 782 | 783 |
TCGv arg0, arg1; |
| 783 | 784 |
arg0 = tcg_temp_new(); |
| 784 |
tcg_gen_qemu_ld32s(arg0, REG(B7_4), ctx->memidx);
|
|
| 785 |
tcg_gen_qemu_ld_i32(arg0, REG(B7_4), ctx->memidx, MO_TESL);
|
|
| 785 | 786 |
arg1 = tcg_temp_new(); |
| 786 |
tcg_gen_qemu_ld32s(arg1, REG(B11_8), ctx->memidx);
|
|
| 787 |
tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL);
|
|
| 787 | 788 |
gen_helper_macw(cpu_env, arg0, arg1); |
| 788 | 789 |
tcg_temp_free(arg1); |
| 789 | 790 |
tcg_temp_free(arg0); |
| ... | ... | |
| 979 | 980 |
TCGv addr_hi = tcg_temp_new(); |
| 980 | 981 |
int fr = XREG(B7_4); |
| 981 | 982 |
tcg_gen_addi_i32(addr_hi, REG(B11_8), 4); |
| 982 |
tcg_gen_qemu_st32(cpu_fregs[fr ], REG(B11_8), ctx->memidx); |
|
| 983 |
tcg_gen_qemu_st32(cpu_fregs[fr+1], addr_hi, ctx->memidx); |
|
| 983 |
tcg_gen_qemu_st_i32(cpu_fregs[fr], REG(B11_8), |
|
| 984 |
ctx->memidx, MO_TEUL); |
|
| 985 |
tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr_hi, |
|
| 986 |
ctx->memidx, MO_TEUL); |
|
| 984 | 987 |
tcg_temp_free(addr_hi); |
| 985 | 988 |
} else {
|
| 986 |
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], REG(B11_8), ctx->memidx); |
|
| 989 |
tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], REG(B11_8), |
|
| 990 |
ctx->memidx, MO_TEUL); |
|
| 987 | 991 |
} |
| 988 | 992 |
return; |
| 989 | 993 |
case 0xf008: /* fmov @Rm,{F,D,X}Rn - FPSCR: Nothing */
|
| ... | ... | |
| 992 | 996 |
TCGv addr_hi = tcg_temp_new(); |
| 993 | 997 |
int fr = XREG(B11_8); |
| 994 | 998 |
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); |
| 995 |
tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
|
|
| 996 |
tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
|
| 999 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_TEUL);
|
|
| 1000 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_TEUL);
|
|
| 997 | 1001 |
tcg_temp_free(addr_hi); |
| 998 | 1002 |
} else {
|
| 999 |
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
|
| 1003 |
tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4), |
|
| 1004 |
ctx->memidx, MO_TEUL); |
|
| 1000 | 1005 |
} |
| 1001 | 1006 |
return; |
| 1002 | 1007 |
case 0xf009: /* fmov @Rm+,{F,D,X}Rn - FPSCR: Nothing */
|
| ... | ... | |
| 1005 | 1010 |
TCGv addr_hi = tcg_temp_new(); |
| 1006 | 1011 |
int fr = XREG(B11_8); |
| 1007 | 1012 |
tcg_gen_addi_i32(addr_hi, REG(B7_4), 4); |
| 1008 |
tcg_gen_qemu_ld32u(cpu_fregs[fr ], REG(B7_4), ctx->memidx);
|
|
| 1009 |
tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr_hi, ctx->memidx);
|
|
| 1013 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr], REG(B7_4), ctx->memidx, MO_TEUL);
|
|
| 1014 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr_hi, ctx->memidx, MO_TEUL);
|
|
| 1010 | 1015 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 8); |
| 1011 | 1016 |
tcg_temp_free(addr_hi); |
| 1012 | 1017 |
} else {
|
| 1013 |
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], REG(B7_4), ctx->memidx); |
|
| 1018 |
tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], REG(B7_4), |
|
| 1019 |
ctx->memidx, MO_TEUL); |
|
| 1014 | 1020 |
tcg_gen_addi_i32(REG(B7_4), REG(B7_4), 4); |
| 1015 | 1021 |
} |
| 1016 | 1022 |
return; |
| ... | ... | |
| 1020 | 1026 |
TCGv addr = tcg_temp_new_i32(); |
| 1021 | 1027 |
int fr = XREG(B7_4); |
| 1022 | 1028 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1023 |
tcg_gen_qemu_st32(cpu_fregs[fr+1], addr, ctx->memidx);
|
|
| 1029 |
tcg_gen_qemu_st_i32(cpu_fregs[fr+1], addr, ctx->memidx, MO_TEUL);
|
|
| 1024 | 1030 |
tcg_gen_subi_i32(addr, addr, 4); |
| 1025 |
tcg_gen_qemu_st32(cpu_fregs[fr ], addr, ctx->memidx);
|
|
| 1031 |
tcg_gen_qemu_st_i32(cpu_fregs[fr], addr, ctx->memidx, MO_TEUL);
|
|
| 1026 | 1032 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 1027 | 1033 |
tcg_temp_free(addr); |
| 1028 | 1034 |
} else {
|
| 1029 | 1035 |
TCGv addr; |
| 1030 | 1036 |
addr = tcg_temp_new_i32(); |
| 1031 | 1037 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1032 |
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
|
| 1038 |
tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr, |
|
| 1039 |
ctx->memidx, MO_TEUL); |
|
| 1033 | 1040 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 1034 | 1041 |
tcg_temp_free(addr); |
| 1035 | 1042 |
} |
| ... | ... | |
| 1041 | 1048 |
tcg_gen_add_i32(addr, REG(B7_4), REG(0)); |
| 1042 | 1049 |
if (ctx->flags & FPSCR_SZ) {
|
| 1043 | 1050 |
int fr = XREG(B11_8); |
| 1044 |
tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
|
| 1051 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr, |
|
| 1052 |
ctx->memidx, MO_TEUL); |
|
| 1045 | 1053 |
tcg_gen_addi_i32(addr, addr, 4); |
| 1046 |
tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); |
|
| 1054 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr, |
|
| 1055 |
ctx->memidx, MO_TEUL); |
|
| 1047 | 1056 |
} else {
|
| 1048 |
tcg_gen_qemu_ld32u(cpu_fregs[FREG(B11_8)], addr, ctx->memidx); |
|
| 1057 |
tcg_gen_qemu_ld_i32(cpu_fregs[FREG(B11_8)], addr, |
|
| 1058 |
ctx->memidx, MO_TEUL); |
|
| 1049 | 1059 |
} |
| 1050 | 1060 |
tcg_temp_free(addr); |
| 1051 | 1061 |
} |
| ... | ... | |
| 1057 | 1067 |
tcg_gen_add_i32(addr, REG(B11_8), REG(0)); |
| 1058 | 1068 |
if (ctx->flags & FPSCR_SZ) {
|
| 1059 | 1069 |
int fr = XREG(B7_4); |
| 1060 |
tcg_gen_qemu_ld32u(cpu_fregs[fr ], addr, ctx->memidx); |
|
| 1070 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr], addr, |
|
| 1071 |
ctx->memidx, MO_TEUL); |
|
| 1061 | 1072 |
tcg_gen_addi_i32(addr, addr, 4); |
| 1062 |
tcg_gen_qemu_ld32u(cpu_fregs[fr+1], addr, ctx->memidx); |
|
| 1073 |
tcg_gen_qemu_ld_i32(cpu_fregs[fr+1], addr, |
|
| 1074 |
ctx->memidx, MO_TEUL); |
|
| 1063 | 1075 |
} else {
|
| 1064 |
tcg_gen_qemu_st32(cpu_fregs[FREG(B7_4)], addr, ctx->memidx); |
|
| 1076 |
tcg_gen_qemu_st_i32(cpu_fregs[FREG(B7_4)], addr, |
|
| 1077 |
ctx->memidx, MO_TEUL); |
|
| 1065 | 1078 |
} |
| 1066 | 1079 |
tcg_temp_free(addr); |
| 1067 | 1080 |
} |
| ... | ... | |
| 1164 | 1177 |
addr = tcg_temp_new(); |
| 1165 | 1178 |
tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
| 1166 | 1179 |
val = tcg_temp_new(); |
| 1167 |
tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
|
|
| 1180 |
tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1168 | 1181 |
tcg_gen_andi_i32(val, val, B7_0); |
| 1169 |
tcg_gen_qemu_st8(val, addr, ctx->memidx);
|
|
| 1182 |
tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1170 | 1183 |
tcg_temp_free(val); |
| 1171 | 1184 |
tcg_temp_free(addr); |
| 1172 | 1185 |
} |
| ... | ... | |
| 1200 | 1213 |
{
|
| 1201 | 1214 |
TCGv addr = tcg_temp_new(); |
| 1202 | 1215 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
| 1203 |
tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
|
| 1216 |
tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB);
|
|
| 1204 | 1217 |
tcg_temp_free(addr); |
| 1205 | 1218 |
} |
| 1206 | 1219 |
return; |
| ... | ... | |
| 1208 | 1221 |
{
|
| 1209 | 1222 |
TCGv addr = tcg_temp_new(); |
| 1210 | 1223 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
| 1211 |
tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
|
| 1224 |
tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
|
|
| 1212 | 1225 |
tcg_temp_free(addr); |
| 1213 | 1226 |
} |
| 1214 | 1227 |
return; |
| ... | ... | |
| 1216 | 1229 |
{
|
| 1217 | 1230 |
TCGv addr = tcg_temp_new(); |
| 1218 | 1231 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
| 1219 |
tcg_gen_qemu_ld32s(REG(0), addr, ctx->memidx);
|
|
| 1232 |
tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESL);
|
|
| 1220 | 1233 |
tcg_temp_free(addr); |
| 1221 | 1234 |
} |
| 1222 | 1235 |
return; |
| ... | ... | |
| 1224 | 1237 |
{
|
| 1225 | 1238 |
TCGv addr = tcg_temp_new(); |
| 1226 | 1239 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0); |
| 1227 |
tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
|
| 1240 |
tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB);
|
|
| 1228 | 1241 |
tcg_temp_free(addr); |
| 1229 | 1242 |
} |
| 1230 | 1243 |
return; |
| ... | ... | |
| 1232 | 1245 |
{
|
| 1233 | 1246 |
TCGv addr = tcg_temp_new(); |
| 1234 | 1247 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 2); |
| 1235 |
tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
|
| 1248 |
tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
|
|
| 1236 | 1249 |
tcg_temp_free(addr); |
| 1237 | 1250 |
} |
| 1238 | 1251 |
return; |
| ... | ... | |
| 1240 | 1253 |
{
|
| 1241 | 1254 |
TCGv addr = tcg_temp_new(); |
| 1242 | 1255 |
tcg_gen_addi_i32(addr, cpu_gbr, B7_0 * 4); |
| 1243 |
tcg_gen_qemu_st32(REG(0), addr, ctx->memidx);
|
|
| 1256 |
tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUL);
|
|
| 1244 | 1257 |
tcg_temp_free(addr); |
| 1245 | 1258 |
} |
| 1246 | 1259 |
return; |
| ... | ... | |
| 1248 | 1261 |
{
|
| 1249 | 1262 |
TCGv addr = tcg_temp_new(); |
| 1250 | 1263 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
| 1251 |
tcg_gen_qemu_st8(REG(0), addr, ctx->memidx);
|
|
| 1264 |
tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_UB);
|
|
| 1252 | 1265 |
tcg_temp_free(addr); |
| 1253 | 1266 |
} |
| 1254 | 1267 |
return; |
| ... | ... | |
| 1256 | 1269 |
{
|
| 1257 | 1270 |
TCGv addr = tcg_temp_new(); |
| 1258 | 1271 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
| 1259 |
tcg_gen_qemu_st16(REG(0), addr, ctx->memidx);
|
|
| 1272 |
tcg_gen_qemu_st_i32(REG(0), addr, ctx->memidx, MO_TEUW);
|
|
| 1260 | 1273 |
tcg_temp_free(addr); |
| 1261 | 1274 |
} |
| 1262 | 1275 |
return; |
| ... | ... | |
| 1264 | 1277 |
{
|
| 1265 | 1278 |
TCGv addr = tcg_temp_new(); |
| 1266 | 1279 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0); |
| 1267 |
tcg_gen_qemu_ld8s(REG(0), addr, ctx->memidx);
|
|
| 1280 |
tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_SB);
|
|
| 1268 | 1281 |
tcg_temp_free(addr); |
| 1269 | 1282 |
} |
| 1270 | 1283 |
return; |
| ... | ... | |
| 1272 | 1285 |
{
|
| 1273 | 1286 |
TCGv addr = tcg_temp_new(); |
| 1274 | 1287 |
tcg_gen_addi_i32(addr, REG(B7_4), B3_0 * 2); |
| 1275 |
tcg_gen_qemu_ld16s(REG(0), addr, ctx->memidx);
|
|
| 1288 |
tcg_gen_qemu_ld_i32(REG(0), addr, ctx->memidx, MO_TESW);
|
|
| 1276 | 1289 |
tcg_temp_free(addr); |
| 1277 | 1290 |
} |
| 1278 | 1291 |
return; |
| ... | ... | |
| 1288 | 1301 |
addr = tcg_temp_new(); |
| 1289 | 1302 |
tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
| 1290 | 1303 |
val = tcg_temp_new(); |
| 1291 |
tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
|
|
| 1304 |
tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1292 | 1305 |
tcg_gen_ori_i32(val, val, B7_0); |
| 1293 |
tcg_gen_qemu_st8(val, addr, ctx->memidx);
|
|
| 1306 |
tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1294 | 1307 |
tcg_temp_free(val); |
| 1295 | 1308 |
tcg_temp_free(addr); |
| 1296 | 1309 |
} |
| ... | ... | |
| 1318 | 1331 |
{
|
| 1319 | 1332 |
TCGv val = tcg_temp_new(); |
| 1320 | 1333 |
tcg_gen_add_i32(val, REG(0), cpu_gbr); |
| 1321 |
tcg_gen_qemu_ld8u(val, val, ctx->memidx);
|
|
| 1334 |
tcg_gen_qemu_ld_i32(val, val, ctx->memidx, MO_UB);
|
|
| 1322 | 1335 |
tcg_gen_andi_i32(val, val, B7_0); |
| 1323 | 1336 |
gen_cmp_imm(TCG_COND_EQ, val, 0); |
| 1324 | 1337 |
tcg_temp_free(val); |
| ... | ... | |
| 1333 | 1346 |
addr = tcg_temp_new(); |
| 1334 | 1347 |
tcg_gen_add_i32(addr, REG(0), cpu_gbr); |
| 1335 | 1348 |
val = tcg_temp_new(); |
| 1336 |
tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
|
|
| 1349 |
tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1337 | 1350 |
tcg_gen_xori_i32(val, val, B7_0); |
| 1338 |
tcg_gen_qemu_st8(val, addr, ctx->memidx);
|
|
| 1351 |
tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1339 | 1352 |
tcg_temp_free(val); |
| 1340 | 1353 |
tcg_temp_free(addr); |
| 1341 | 1354 |
} |
| ... | ... | |
| 1349 | 1362 |
return; |
| 1350 | 1363 |
case 0x4087: /* ldc.l @Rm+,Rn_BANK */ |
| 1351 | 1364 |
CHECK_PRIVILEGED |
| 1352 |
tcg_gen_qemu_ld32s(ALTREG(B6_4), REG(B11_8), ctx->memidx);
|
|
| 1365 |
tcg_gen_qemu_ld_i32(ALTREG(B6_4), REG(B11_8), ctx->memidx, MO_TESL);
|
|
| 1353 | 1366 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); |
| 1354 | 1367 |
return; |
| 1355 | 1368 |
case 0x0082: /* stc Rm_BANK,Rn */ |
| ... | ... | |
| 1361 | 1374 |
{
|
| 1362 | 1375 |
TCGv addr = tcg_temp_new(); |
| 1363 | 1376 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1364 |
tcg_gen_qemu_st32(ALTREG(B6_4), addr, ctx->memidx);
|
|
| 1377 |
tcg_gen_qemu_st_i32(ALTREG(B6_4), addr, ctx->memidx, MO_TEUL);
|
|
| 1365 | 1378 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 1366 | 1379 |
tcg_temp_free(addr); |
| 1367 | 1380 |
} |
| ... | ... | |
| 1414 | 1427 |
CHECK_PRIVILEGED |
| 1415 | 1428 |
{
|
| 1416 | 1429 |
TCGv val = tcg_temp_new(); |
| 1417 |
tcg_gen_qemu_ld32s(val, REG(B11_8), ctx->memidx);
|
|
| 1430 |
tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TESL);
|
|
| 1418 | 1431 |
tcg_gen_andi_i32(cpu_sr, val, 0x700083f3); |
| 1419 | 1432 |
tcg_temp_free(val); |
| 1420 | 1433 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); |
| ... | ... | |
| 1430 | 1443 |
{
|
| 1431 | 1444 |
TCGv addr = tcg_temp_new(); |
| 1432 | 1445 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1433 |
tcg_gen_qemu_st32(cpu_sr, addr, ctx->memidx);
|
|
| 1446 |
tcg_gen_qemu_st_i32(cpu_sr, addr, ctx->memidx, MO_TEUL);
|
|
| 1434 | 1447 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 1435 | 1448 |
tcg_temp_free(addr); |
| 1436 | 1449 |
} |
| ... | ... | |
| 1442 | 1455 |
return; \ |
| 1443 | 1456 |
case ldpnum: \ |
| 1444 | 1457 |
prechk \ |
| 1445 |
tcg_gen_qemu_ld32s (cpu_##reg, REG(B11_8), ctx->memidx); \
|
|
| 1458 |
tcg_gen_qemu_ld_i32(cpu_##reg, REG(B11_8), ctx->memidx, MO_TESL); \
|
|
| 1446 | 1459 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ |
| 1447 | 1460 |
return; |
| 1448 | 1461 |
#define ST(reg,stnum,stpnum,prechk) \ |
| ... | ... | |
| 1455 | 1468 |
{ \
|
| 1456 | 1469 |
TCGv addr = tcg_temp_new(); \ |
| 1457 | 1470 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); \ |
| 1458 |
tcg_gen_qemu_st32 (cpu_##reg, addr, ctx->memidx); \
|
|
| 1471 |
tcg_gen_qemu_st_i32(cpu_##reg, addr, ctx->memidx, MO_TEUL); \
|
|
| 1459 | 1472 |
tcg_gen_mov_i32(REG(B11_8), addr); \ |
| 1460 | 1473 |
tcg_temp_free(addr); \ |
| 1461 | 1474 |
} \ |
| ... | ... | |
| 1483 | 1496 |
CHECK_FPU_ENABLED |
| 1484 | 1497 |
{
|
| 1485 | 1498 |
TCGv addr = tcg_temp_new(); |
| 1486 |
tcg_gen_qemu_ld32s(addr, REG(B11_8), ctx->memidx);
|
|
| 1499 |
tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, MO_TESL);
|
|
| 1487 | 1500 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); |
| 1488 | 1501 |
gen_helper_ld_fpscr(cpu_env, addr); |
| 1489 | 1502 |
tcg_temp_free(addr); |
| ... | ... | |
| 1502 | 1515 |
tcg_gen_andi_i32(val, cpu_fpscr, 0x003fffff); |
| 1503 | 1516 |
addr = tcg_temp_new(); |
| 1504 | 1517 |
tcg_gen_subi_i32(addr, REG(B11_8), 4); |
| 1505 |
tcg_gen_qemu_st32(val, addr, ctx->memidx);
|
|
| 1518 |
tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_TEUL);
|
|
| 1506 | 1519 |
tcg_gen_mov_i32(REG(B11_8), addr); |
| 1507 | 1520 |
tcg_temp_free(addr); |
| 1508 | 1521 |
tcg_temp_free(val); |
| ... | ... | |
| 1511 | 1524 |
case 0x00c3: /* movca.l R0,@Rm */ |
| 1512 | 1525 |
{
|
| 1513 | 1526 |
TCGv val = tcg_temp_new(); |
| 1514 |
tcg_gen_qemu_ld32u(val, REG(B11_8), ctx->memidx);
|
|
| 1527 |
tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL);
|
|
| 1515 | 1528 |
gen_helper_movcal(cpu_env, REG(B11_8), val); |
| 1516 |
tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
|
|
| 1529 |
tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
|
|
| 1517 | 1530 |
} |
| 1518 | 1531 |
ctx->has_movcal = 1; |
| 1519 | 1532 |
return; |
| 1520 | 1533 |
case 0x40a9: |
| 1521 | 1534 |
/* MOVUA.L @Rm,R0 (Rm) -> R0 |
| 1522 | 1535 |
Load non-boundary-aligned data */ |
| 1523 |
tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
|
| 1536 |
tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
|
|
| 1524 | 1537 |
return; |
| 1525 | 1538 |
case 0x40e9: |
| 1526 | 1539 |
/* MOVUA.L @Rm+,R0 (Rm) -> R0, Rm + 4 -> Rm |
| 1527 | 1540 |
Load non-boundary-aligned data */ |
| 1528 |
tcg_gen_qemu_ld32u(REG(0), REG(B11_8), ctx->memidx);
|
|
| 1541 |
tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
|
|
| 1529 | 1542 |
tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); |
| 1530 | 1543 |
return; |
| 1531 | 1544 |
case 0x0029: /* movt Rn */ |
| ... | ... | |
| 1542 | 1555 |
tcg_gen_andi_i32(cpu_sr, cpu_sr, ~SR_T); |
| 1543 | 1556 |
tcg_gen_or_i32(cpu_sr, cpu_sr, cpu_ldst); |
| 1544 | 1557 |
tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_ldst, 0, label); |
| 1545 |
tcg_gen_qemu_st32(REG(0), REG(B11_8), ctx->memidx);
|
|
| 1558 |
tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL);
|
|
| 1546 | 1559 |
gen_set_label(label); |
| 1547 | 1560 |
tcg_gen_movi_i32(cpu_ldst, 0); |
| 1548 | 1561 |
return; |
| ... | ... | |
| 1557 | 1570 |
*/ |
| 1558 | 1571 |
if (ctx->features & SH_FEATURE_SH4A) {
|
| 1559 | 1572 |
tcg_gen_movi_i32(cpu_ldst, 0); |
| 1560 |
tcg_gen_qemu_ld32s(REG(0), REG(B11_8), ctx->memidx);
|
|
| 1573 |
tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL);
|
|
| 1561 | 1574 |
tcg_gen_movi_i32(cpu_ldst, 1); |
| 1562 | 1575 |
return; |
| 1563 | 1576 |
} else |
| ... | ... | |
| 1655 | 1668 |
addr = tcg_temp_local_new(); |
| 1656 | 1669 |
tcg_gen_mov_i32(addr, REG(B11_8)); |
| 1657 | 1670 |
val = tcg_temp_local_new(); |
| 1658 |
tcg_gen_qemu_ld8u(val, addr, ctx->memidx);
|
|
| 1671 |
tcg_gen_qemu_ld_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1659 | 1672 |
gen_cmp_imm(TCG_COND_EQ, val, 0); |
| 1660 | 1673 |
tcg_gen_ori_i32(val, val, 0x80); |
| 1661 |
tcg_gen_qemu_st8(val, addr, ctx->memidx);
|
|
| 1674 |
tcg_gen_qemu_st_i32(val, addr, ctx->memidx, MO_UB);
|
|
| 1662 | 1675 |
tcg_temp_free(val); |
| 1663 | 1676 |
tcg_temp_free(addr); |
| 1664 | 1677 |
} |
Also available in: Unified diff