Revision 33d68b5f target-mips/mips-defs.h
| b/target-mips/mips-defs.h | ||
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| 6 | 6 |
/* If we want to use host float regs... */ |
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//#define USE_HOST_FLOAT_REGS |
| 8 | 8 |
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#define MIPS_R4Kc 0x00018000 |
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#define MIPS_R4Kp 0x00018300 |
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/* Emulate MIPS R4Kc for now */ |
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#define MIPS_CPU MIPS_R4Kc |
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#if (MIPS_CPU == MIPS_R4Kc) |
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/* 32 bits target */ |
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#undef MIPS_HAS_MIPS64 |
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//#define MIPS_HAS_MIPS64 1 |
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/* real pages are variable size... */ |
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#define TARGET_PAGE_BITS 12 |
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/* Uses MIPS R4Kx enhancements to MIPS32 architecture */ |
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#define MIPS_USES_R4K_EXT |
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/* Uses MIPS R4Kc TLB model */ |
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#define MIPS_USES_R4K_TLB |
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#define MIPS_TLB_NB 16 |
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#define MIPS_TLB_MAX 128 |
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/* basic FPU register support */ |
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#define MIPS_USES_FPU 1 |
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/* Define a implementation number of 1. |
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* Define a major version 1, minor version 0. |
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*/ |
| ... | ... | |
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((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \ |
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(0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \ |
| 65 | 54 |
(0 << CP0C3_MT) | (0 << CP0C3_SM) | (0 << CP0C3_TL)) |
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#elif (MIPS_CPU == MIPS_R4Kp) |
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/* 32 bits target */ |
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#undef MIPS_HAS_MIPS64 |
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/* real pages are variable size... */ |
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#define TARGET_PAGE_BITS 12 |
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/* Uses MIPS R4Kx enhancements to MIPS32 architecture */ |
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#define MIPS_USES_R4K_EXT |
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/* Uses MIPS R4Km FPM MMU model */ |
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#define MIPS_USES_R4K_FPM |
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#else |
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#error "MIPS CPU not defined" |
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/* Reminder for other flags */ |
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//#undef MIPS_HAS_MIPS64 |
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//#define MIPS_USES_FPU |
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#endif |
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| 81 | 55 |
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| 82 | 56 |
#ifdef MIPS_HAS_MIPS64 |
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#define TARGET_LONG_BITS 64 |
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