Revision 33d68b5f target-mips/translate.c

b/target-mips/translate.c
5283 5283 
    env->CP0_Wired = 0;
5284 5284 
    /* SMP not implemented */
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    env->CP0_EBase = 0x80000000;
5286 
    env->CP0_Config0 = MIPS_CONFIG0;
5287 
    env->CP0_Config1 = MIPS_CONFIG1;
5288 
#ifdef MIPS_USES_FPU
5289 
    /* basic FPU register support */
5290 
    env->CP0_Config1 |= (1 << CP0C1_FP);
5291 
#endif
5292 5286 
    env->CP0_Config2 = MIPS_CONFIG2;
5293 5287 
    env->CP0_Config3 = MIPS_CONFIG3;
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    env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
......
5296 5290 
    env->hflags = MIPS_HFLAG_ERL;
5297 5291 
    /* Count register increments in debug mode, EJTAG version 1 */
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    env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
5299 
    env->CP0_PRid = MIPS_CPU;
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#endif
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    env->exception_index = EXCP_NONE;
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#if defined(CONFIG_USER_ONLY)
......
5308 5301 
    env->SYNCI_Step = 16;
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    env->CCRes = 2;
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}
5304 

  		





  
  5305
  
    
#include "translate_init.c"


  		












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