Statistics
| Branch: | Revision:

root / hw / ide.c @ 33f00271

History | View | Annotate | Download (111.4 kB)

1
/*
2
 * QEMU IDE disk and CD-ROM Emulator
3
 *
4
 * Copyright (c) 2003 Fabrice Bellard
5
 * Copyright (c) 2006 Openedhand Ltd.
6
 *
7
 * Permission is hereby granted, free of charge, to any person obtaining a copy
8
 * of this software and associated documentation files (the "Software"), to deal
9
 * in the Software without restriction, including without limitation the rights
10
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11
 * copies of the Software, and to permit persons to whom the Software is
12
 * furnished to do so, subject to the following conditions:
13
 *
14
 * The above copyright notice and this permission notice shall be included in
15
 * all copies or substantial portions of the Software.
16
 *
17
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22
 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23
 * THE SOFTWARE.
24
 */
25
#include "hw.h"
26
#include "pc.h"
27
#include "pci.h"
28
#include "scsi-disk.h"
29
#include "pcmcia.h"
30
#include "block.h"
31
#include "qemu-timer.h"
32
#include "sysemu.h"
33
#include "ppc_mac.h"
34

    
35
/* debug IDE devices */
36
//#define DEBUG_IDE
37
//#define DEBUG_IDE_ATAPI
38
//#define DEBUG_AIO
39
#define USE_DMA_CDROM
40

    
41
/* Bits of HD_STATUS */
42
#define ERR_STAT                0x01
43
#define INDEX_STAT                0x02
44
#define ECC_STAT                0x04        /* Corrected error */
45
#define DRQ_STAT                0x08
46
#define SEEK_STAT                0x10
47
#define SRV_STAT                0x10
48
#define WRERR_STAT                0x20
49
#define READY_STAT                0x40
50
#define BUSY_STAT                0x80
51

    
52
/* Bits for HD_ERROR */
53
#define MARK_ERR                0x01        /* Bad address mark */
54
#define TRK0_ERR                0x02        /* couldn't find track 0 */
55
#define ABRT_ERR                0x04        /* Command aborted */
56
#define MCR_ERR                        0x08        /* media change request */
57
#define ID_ERR                        0x10        /* ID field not found */
58
#define MC_ERR                        0x20        /* media changed */
59
#define ECC_ERR                        0x40        /* Uncorrectable ECC error */
60
#define BBD_ERR                        0x80        /* pre-EIDE meaning:  block marked bad */
61
#define ICRC_ERR                0x80        /* new meaning:  CRC error during transfer */
62

    
63
/* Bits of HD_NSECTOR */
64
#define CD                        0x01
65
#define IO                        0x02
66
#define REL                        0x04
67
#define TAG_MASK                0xf8
68

    
69
#define IDE_CMD_RESET           0x04
70
#define IDE_CMD_DISABLE_IRQ     0x02
71

    
72
/* ATA/ATAPI Commands pre T13 Spec */
73
#define WIN_NOP                                0x00
74
/*
75
 *        0x01->0x02 Reserved
76
 */
77
#define CFA_REQ_EXT_ERROR_CODE                0x03 /* CFA Request Extended Error Code */
78
/*
79
 *        0x04->0x07 Reserved
80
 */
81
#define WIN_SRST                        0x08 /* ATAPI soft reset command */
82
#define WIN_DEVICE_RESET                0x08
83
/*
84
 *        0x09->0x0F Reserved
85
 */
86
#define WIN_RECAL                        0x10
87
#define WIN_RESTORE                        WIN_RECAL
88
/*
89
 *        0x10->0x1F Reserved
90
 */
91
#define WIN_READ                        0x20 /* 28-Bit */
92
#define WIN_READ_ONCE                        0x21 /* 28-Bit without retries */
93
#define WIN_READ_LONG                        0x22 /* 28-Bit */
94
#define WIN_READ_LONG_ONCE                0x23 /* 28-Bit without retries */
95
#define WIN_READ_EXT                        0x24 /* 48-Bit */
96
#define WIN_READDMA_EXT                        0x25 /* 48-Bit */
97
#define WIN_READDMA_QUEUED_EXT                0x26 /* 48-Bit */
98
#define WIN_READ_NATIVE_MAX_EXT                0x27 /* 48-Bit */
99
/*
100
 *        0x28
101
 */
102
#define WIN_MULTREAD_EXT                0x29 /* 48-Bit */
103
/*
104
 *        0x2A->0x2F Reserved
105
 */
106
#define WIN_WRITE                        0x30 /* 28-Bit */
107
#define WIN_WRITE_ONCE                        0x31 /* 28-Bit without retries */
108
#define WIN_WRITE_LONG                        0x32 /* 28-Bit */
109
#define WIN_WRITE_LONG_ONCE                0x33 /* 28-Bit without retries */
110
#define WIN_WRITE_EXT                        0x34 /* 48-Bit */
111
#define WIN_WRITEDMA_EXT                0x35 /* 48-Bit */
112
#define WIN_WRITEDMA_QUEUED_EXT                0x36 /* 48-Bit */
113
#define WIN_SET_MAX_EXT                        0x37 /* 48-Bit */
114
#define CFA_WRITE_SECT_WO_ERASE                0x38 /* CFA Write Sectors without erase */
115
#define WIN_MULTWRITE_EXT                0x39 /* 48-Bit */
116
/*
117
 *        0x3A->0x3B Reserved
118
 */
119
#define WIN_WRITE_VERIFY                0x3C /* 28-Bit */
120
/*
121
 *        0x3D->0x3F Reserved
122
 */
123
#define WIN_VERIFY                        0x40 /* 28-Bit - Read Verify Sectors */
124
#define WIN_VERIFY_ONCE                        0x41 /* 28-Bit - without retries */
125
#define WIN_VERIFY_EXT                        0x42 /* 48-Bit */
126
/*
127
 *        0x43->0x4F Reserved
128
 */
129
#define WIN_FORMAT                        0x50
130
/*
131
 *        0x51->0x5F Reserved
132
 */
133
#define WIN_INIT                        0x60
134
/*
135
 *        0x61->0x5F Reserved
136
 */
137
#define WIN_SEEK                        0x70 /* 0x70-0x7F Reserved */
138
#define CFA_TRANSLATE_SECTOR                0x87 /* CFA Translate Sector */
139
#define WIN_DIAGNOSE                        0x90
140
#define WIN_SPECIFY                        0x91 /* set drive geometry translation */
141
#define WIN_DOWNLOAD_MICROCODE                0x92
142
#define WIN_STANDBYNOW2                        0x94
143
#define CFA_IDLEIMMEDIATE                0x95 /* force drive to become "ready" */
144
#define WIN_STANDBY2                        0x96
145
#define WIN_SETIDLE2                        0x97
146
#define WIN_CHECKPOWERMODE2                0x98
147
#define WIN_SLEEPNOW2                        0x99
148
/*
149
 *        0x9A VENDOR
150
 */
151
#define WIN_PACKETCMD                        0xA0 /* Send a packet command. */
152
#define WIN_PIDENTIFY                        0xA1 /* identify ATAPI device        */
153
#define WIN_QUEUED_SERVICE                0xA2
154
#define WIN_SMART                        0xB0 /* self-monitoring and reporting */
155
#define CFA_ACCESS_METADATA_STORAGE        0xB8
156
#define CFA_ERASE_SECTORS               0xC0 /* microdrives implement as NOP */
157
#define WIN_MULTREAD                        0xC4 /* read sectors using multiple mode*/
158
#define WIN_MULTWRITE                        0xC5 /* write sectors using multiple mode */
159
#define WIN_SETMULT                        0xC6 /* enable/disable multiple mode */
160
#define WIN_READDMA_QUEUED                0xC7 /* read sectors using Queued DMA transfers */
161
#define WIN_READDMA                        0xC8 /* read sectors using DMA transfers */
162
#define WIN_READDMA_ONCE                0xC9 /* 28-Bit - without retries */
163
#define WIN_WRITEDMA                        0xCA /* write sectors using DMA transfers */
164
#define WIN_WRITEDMA_ONCE                0xCB /* 28-Bit - without retries */
165
#define WIN_WRITEDMA_QUEUED                0xCC /* write sectors using Queued DMA transfers */
166
#define CFA_WRITE_MULTI_WO_ERASE        0xCD /* CFA Write multiple without erase */
167
#define WIN_GETMEDIASTATUS                0xDA
168
#define WIN_ACKMEDIACHANGE                0xDB /* ATA-1, ATA-2 vendor */
169
#define WIN_POSTBOOT                        0xDC
170
#define WIN_PREBOOT                        0xDD
171
#define WIN_DOORLOCK                        0xDE /* lock door on removable drives */
172
#define WIN_DOORUNLOCK                        0xDF /* unlock door on removable drives */
173
#define WIN_STANDBYNOW1                        0xE0
174
#define WIN_IDLEIMMEDIATE                0xE1 /* force drive to become "ready" */
175
#define WIN_STANDBY                     0xE2 /* Set device in Standby Mode */
176
#define WIN_SETIDLE1                        0xE3
177
#define WIN_READ_BUFFER                        0xE4 /* force read only 1 sector */
178
#define WIN_CHECKPOWERMODE1                0xE5
179
#define WIN_SLEEPNOW1                        0xE6
180
#define WIN_FLUSH_CACHE                        0xE7
181
#define WIN_WRITE_BUFFER                0xE8 /* force write only 1 sector */
182
#define WIN_WRITE_SAME                        0xE9 /* read ata-2 to use */
183
        /* SET_FEATURES 0x22 or 0xDD */
184
#define WIN_FLUSH_CACHE_EXT                0xEA /* 48-Bit */
185
#define WIN_IDENTIFY                        0xEC /* ask drive to identify itself        */
186
#define WIN_MEDIAEJECT                        0xED
187
#define WIN_IDENTIFY_DMA                0xEE /* same as WIN_IDENTIFY, but DMA */
188
#define WIN_SETFEATURES                        0xEF /* set special drive features */
189
#define EXABYTE_ENABLE_NEST                0xF0
190
#define IBM_SENSE_CONDITION                0xF0 /* measure disk temperature */
191
#define WIN_SECURITY_SET_PASS                0xF1
192
#define WIN_SECURITY_UNLOCK                0xF2
193
#define WIN_SECURITY_ERASE_PREPARE        0xF3
194
#define WIN_SECURITY_ERASE_UNIT                0xF4
195
#define WIN_SECURITY_FREEZE_LOCK        0xF5
196
#define CFA_WEAR_LEVEL                        0xF5 /* microdrives implement as NOP */
197
#define WIN_SECURITY_DISABLE                0xF6
198
#define WIN_READ_NATIVE_MAX                0xF8 /* return the native maximum address */
199
#define WIN_SET_MAX                        0xF9
200
#define DISABLE_SEAGATE                        0xFB
201

    
202
/* set to 1 set disable mult support */
203
#define MAX_MULT_SECTORS 16
204

    
205
/* ATAPI defines */
206

    
207
#define ATAPI_PACKET_SIZE 12
208

    
209
/* The generic packet command opcodes for CD/DVD Logical Units,
210
 * From Table 57 of the SFF8090 Ver. 3 (Mt. Fuji) draft standard. */
211
#define GPCMD_BLANK                            0xa1
212
#define GPCMD_CLOSE_TRACK                    0x5b
213
#define GPCMD_FLUSH_CACHE                    0x35
214
#define GPCMD_FORMAT_UNIT                    0x04
215
#define GPCMD_GET_CONFIGURATION                    0x46
216
#define GPCMD_GET_EVENT_STATUS_NOTIFICATION 0x4a
217
#define GPCMD_GET_PERFORMANCE                    0xac
218
#define GPCMD_INQUIRY                            0x12
219
#define GPCMD_LOAD_UNLOAD                    0xa6
220
#define GPCMD_MECHANISM_STATUS                    0xbd
221
#define GPCMD_MODE_SELECT_10                    0x55
222
#define GPCMD_MODE_SENSE_10                    0x5a
223
#define GPCMD_PAUSE_RESUME                    0x4b
224
#define GPCMD_PLAY_AUDIO_10                    0x45
225
#define GPCMD_PLAY_AUDIO_MSF                    0x47
226
#define GPCMD_PLAY_AUDIO_TI                    0x48
227
#define GPCMD_PLAY_CD                            0xbc
228
#define GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL  0x1e
229
#define GPCMD_READ_10                            0x28
230
#define GPCMD_READ_12                            0xa8
231
#define GPCMD_READ_CDVD_CAPACITY            0x25
232
#define GPCMD_READ_CD                            0xbe
233
#define GPCMD_READ_CD_MSF                    0xb9
234
#define GPCMD_READ_DISC_INFO                    0x51
235
#define GPCMD_READ_DVD_STRUCTURE            0xad
236
#define GPCMD_READ_FORMAT_CAPACITIES            0x23
237
#define GPCMD_READ_HEADER                    0x44
238
#define GPCMD_READ_TRACK_RZONE_INFO            0x52
239
#define GPCMD_READ_SUBCHANNEL                    0x42
240
#define GPCMD_READ_TOC_PMA_ATIP                    0x43
241
#define GPCMD_REPAIR_RZONE_TRACK            0x58
242
#define GPCMD_REPORT_KEY                    0xa4
243
#define GPCMD_REQUEST_SENSE                    0x03
244
#define GPCMD_RESERVE_RZONE_TRACK            0x53
245
#define GPCMD_SCAN                            0xba
246
#define GPCMD_SEEK                            0x2b
247
#define GPCMD_SEND_DVD_STRUCTURE            0xad
248
#define GPCMD_SEND_EVENT                    0xa2
249
#define GPCMD_SEND_KEY                            0xa3
250
#define GPCMD_SEND_OPC                            0x54
251
#define GPCMD_SET_READ_AHEAD                    0xa7
252
#define GPCMD_SET_STREAMING                    0xb6
253
#define GPCMD_START_STOP_UNIT                    0x1b
254
#define GPCMD_STOP_PLAY_SCAN                    0x4e
255
#define GPCMD_TEST_UNIT_READY                    0x00
256
#define GPCMD_VERIFY_10                            0x2f
257
#define GPCMD_WRITE_10                            0x2a
258
#define GPCMD_WRITE_AND_VERIFY_10            0x2e
259
/* This is listed as optional in ATAPI 2.6, but is (curiously)
260
 * missing from Mt. Fuji, Table 57.  It _is_ mentioned in Mt. Fuji
261
 * Table 377 as an MMC command for SCSi devices though...  Most ATAPI
262
 * drives support it. */
263
#define GPCMD_SET_SPEED                            0xbb
264
/* This seems to be a SCSI specific CD-ROM opcode
265
 * to play data at track/index */
266
#define GPCMD_PLAYAUDIO_TI                    0x48
267
/*
268
 * From MS Media Status Notification Support Specification. For
269
 * older drives only.
270
 */
271
#define GPCMD_GET_MEDIA_STATUS                    0xda
272
#define GPCMD_MODE_SENSE_6                    0x1a
273

    
274
/* Mode page codes for mode sense/set */
275
#define GPMODE_R_W_ERROR_PAGE                0x01
276
#define GPMODE_WRITE_PARMS_PAGE                0x05
277
#define GPMODE_AUDIO_CTL_PAGE                0x0e
278
#define GPMODE_POWER_PAGE                0x1a
279
#define GPMODE_FAULT_FAIL_PAGE                0x1c
280
#define GPMODE_TO_PROTECT_PAGE                0x1d
281
#define GPMODE_CAPABILITIES_PAGE        0x2a
282
#define GPMODE_ALL_PAGES                0x3f
283
/* Not in Mt. Fuji, but in ATAPI 2.6 -- depricated now in favor
284
 * of MODE_SENSE_POWER_PAGE */
285
#define GPMODE_CDROM_PAGE                0x0d
286

    
287
#define ATAPI_INT_REASON_CD             0x01 /* 0 = data transfer */
288
#define ATAPI_INT_REASON_IO             0x02 /* 1 = transfer to the host */
289
#define ATAPI_INT_REASON_REL            0x04
290
#define ATAPI_INT_REASON_TAG            0xf8
291

    
292
/* same constants as bochs */
293
#define ASC_ILLEGAL_OPCODE                   0x20
294
#define ASC_LOGICAL_BLOCK_OOR                0x21
295
#define ASC_INV_FIELD_IN_CMD_PACKET          0x24
296
#define ASC_MEDIUM_NOT_PRESENT               0x3a
297
#define ASC_SAVING_PARAMETERS_NOT_SUPPORTED  0x39
298

    
299
#define CFA_NO_ERROR            0x00
300
#define CFA_MISC_ERROR          0x09
301
#define CFA_INVALID_COMMAND     0x20
302
#define CFA_INVALID_ADDRESS     0x21
303
#define CFA_ADDRESS_OVERFLOW    0x2f
304

    
305
#define SENSE_NONE            0
306
#define SENSE_NOT_READY       2
307
#define SENSE_ILLEGAL_REQUEST 5
308
#define SENSE_UNIT_ATTENTION  6
309

    
310
struct IDEState;
311

    
312
typedef void EndTransferFunc(struct IDEState *);
313

    
314
/* NOTE: IDEState represents in fact one drive */
315
typedef struct IDEState {
316
    /* ide config */
317
    int is_cdrom;
318
    int is_cf;
319
    int cylinders, heads, sectors;
320
    int64_t nb_sectors;
321
    int mult_sectors;
322
    int identify_set;
323
    uint16_t identify_data[256];
324
    qemu_irq irq;
325
    PCIDevice *pci_dev;
326
    struct BMDMAState *bmdma;
327
    int drive_serial;
328
    /* ide regs */
329
    uint8_t feature;
330
    uint8_t error;
331
    uint32_t nsector;
332
    uint8_t sector;
333
    uint8_t lcyl;
334
    uint8_t hcyl;
335
    /* other part of tf for lba48 support */
336
    uint8_t hob_feature;
337
    uint8_t hob_nsector;
338
    uint8_t hob_sector;
339
    uint8_t hob_lcyl;
340
    uint8_t hob_hcyl;
341

    
342
    uint8_t select;
343
    uint8_t status;
344

    
345
    /* 0x3f6 command, only meaningful for drive 0 */
346
    uint8_t cmd;
347
    /* set for lba48 access */
348
    uint8_t lba48;
349
    /* depends on bit 4 in select, only meaningful for drive 0 */
350
    struct IDEState *cur_drive;
351
    BlockDriverState *bs;
352
    /* ATAPI specific */
353
    uint8_t sense_key;
354
    uint8_t asc;
355
    int packet_transfer_size;
356
    int elementary_transfer_size;
357
    int io_buffer_index;
358
    int lba;
359
    int cd_sector_size;
360
    int atapi_dma; /* true if dma is requested for the packet cmd */
361
    /* ATA DMA state */
362
    int io_buffer_size;
363
    /* PIO transfer handling */
364
    int req_nb_sectors; /* number of sectors per interrupt */
365
    EndTransferFunc *end_transfer_func;
366
    uint8_t *data_ptr;
367
    uint8_t *data_end;
368
    uint8_t *io_buffer;
369
    QEMUTimer *sector_write_timer; /* only used for win2k install hack */
370
    uint32_t irq_count; /* counts IRQs when using win2k install hack */
371
    /* CF-ATA extended error */
372
    uint8_t ext_error;
373
    /* CF-ATA metadata storage */
374
    uint32_t mdata_size;
375
    uint8_t *mdata_storage;
376
    int media_changed;
377
} IDEState;
378

    
379
#define BM_STATUS_DMAING 0x01
380
#define BM_STATUS_ERROR  0x02
381
#define BM_STATUS_INT    0x04
382

    
383
#define BM_CMD_START     0x01
384
#define BM_CMD_READ      0x08
385

    
386
#define IDE_TYPE_PIIX3   0
387
#define IDE_TYPE_CMD646  1
388
#define IDE_TYPE_PIIX4   2
389

    
390
/* CMD646 specific */
391
#define MRDMODE                0x71
392
#define   MRDMODE_INTR_CH0        0x04
393
#define   MRDMODE_INTR_CH1        0x08
394
#define   MRDMODE_BLK_CH0        0x10
395
#define   MRDMODE_BLK_CH1        0x20
396
#define UDIDETCR0        0x73
397
#define UDIDETCR1        0x7B
398

    
399
typedef struct BMDMAState {
400
    uint8_t cmd;
401
    uint8_t status;
402
    uint32_t addr;
403

    
404
    struct PCIIDEState *pci_dev;
405
    /* current transfer state */
406
    uint32_t cur_addr;
407
    uint32_t cur_prd_last;
408
    uint32_t cur_prd_addr;
409
    uint32_t cur_prd_len;
410
    IDEState *ide_if;
411
    BlockDriverCompletionFunc *dma_cb;
412
    BlockDriverAIOCB *aiocb;
413
} BMDMAState;
414

    
415
typedef struct PCIIDEState {
416
    PCIDevice dev;
417
    IDEState ide_if[4];
418
    BMDMAState bmdma[2];
419
    int type; /* see IDE_TYPE_xxx */
420
} PCIIDEState;
421

    
422
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb);
423
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret);
424

    
425
static void padstr(char *str, const char *src, int len)
426
{
427
    int i, v;
428
    for(i = 0; i < len; i++) {
429
        if (*src)
430
            v = *src++;
431
        else
432
            v = ' ';
433
        str[i^1] = v;
434
    }
435
}
436

    
437
static void padstr8(uint8_t *buf, int buf_size, const char *src)
438
{
439
    int i;
440
    for(i = 0; i < buf_size; i++) {
441
        if (*src)
442
            buf[i] = *src++;
443
        else
444
            buf[i] = ' ';
445
    }
446
}
447

    
448
static void put_le16(uint16_t *p, unsigned int v)
449
{
450
    *p = cpu_to_le16(v);
451
}
452

    
453
static void ide_identify(IDEState *s)
454
{
455
    uint16_t *p;
456
    unsigned int oldsize;
457
    char buf[20];
458

    
459
    if (s->identify_set) {
460
        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
461
        return;
462
    }
463

    
464
    memset(s->io_buffer, 0, 512);
465
    p = (uint16_t *)s->io_buffer;
466
    put_le16(p + 0, 0x0040);
467
    put_le16(p + 1, s->cylinders);
468
    put_le16(p + 3, s->heads);
469
    put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
470
    put_le16(p + 5, 512); /* XXX: retired, remove ? */
471
    put_le16(p + 6, s->sectors);
472
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
473
    padstr((char *)(p + 10), buf, 20); /* serial number */
474
    put_le16(p + 20, 3); /* XXX: retired, remove ? */
475
    put_le16(p + 21, 512); /* cache size in sectors */
476
    put_le16(p + 22, 4); /* ecc bytes */
477
    padstr((char *)(p + 23), QEMU_VERSION, 8); /* firmware version */
478
    padstr((char *)(p + 27), "QEMU HARDDISK", 40); /* model */
479
#if MAX_MULT_SECTORS > 1
480
    put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
481
#endif
482
    put_le16(p + 48, 1); /* dword I/O */
483
    put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
484
    put_le16(p + 51, 0x200); /* PIO transfer cycle */
485
    put_le16(p + 52, 0x200); /* DMA transfer cycle */
486
    put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
487
    put_le16(p + 54, s->cylinders);
488
    put_le16(p + 55, s->heads);
489
    put_le16(p + 56, s->sectors);
490
    oldsize = s->cylinders * s->heads * s->sectors;
491
    put_le16(p + 57, oldsize);
492
    put_le16(p + 58, oldsize >> 16);
493
    if (s->mult_sectors)
494
        put_le16(p + 59, 0x100 | s->mult_sectors);
495
    put_le16(p + 60, s->nb_sectors);
496
    put_le16(p + 61, s->nb_sectors >> 16);
497
    put_le16(p + 63, 0x07); /* mdma0-2 supported */
498
    put_le16(p + 65, 120);
499
    put_le16(p + 66, 120);
500
    put_le16(p + 67, 120);
501
    put_le16(p + 68, 120);
502
    put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
503
    put_le16(p + 81, 0x16); /* conforms to ata5 */
504
    put_le16(p + 82, (1 << 14));
505
    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
506
    put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
507
    put_le16(p + 84, (1 << 14));
508
    put_le16(p + 85, (1 << 14));
509
    /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
510
    put_le16(p + 86, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
511
    put_le16(p + 87, (1 << 14));
512
    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
513
    put_le16(p + 93, 1 | (1 << 14) | 0x2000);
514
    put_le16(p + 100, s->nb_sectors);
515
    put_le16(p + 101, s->nb_sectors >> 16);
516
    put_le16(p + 102, s->nb_sectors >> 32);
517
    put_le16(p + 103, s->nb_sectors >> 48);
518

    
519
    memcpy(s->identify_data, p, sizeof(s->identify_data));
520
    s->identify_set = 1;
521
}
522

    
523
static void ide_atapi_identify(IDEState *s)
524
{
525
    uint16_t *p;
526
    char buf[20];
527

    
528
    if (s->identify_set) {
529
        memcpy(s->io_buffer, s->identify_data, sizeof(s->identify_data));
530
        return;
531
    }
532

    
533
    memset(s->io_buffer, 0, 512);
534
    p = (uint16_t *)s->io_buffer;
535
    /* Removable CDROM, 50us response, 12 byte packets */
536
    put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
537
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
538
    padstr((char *)(p + 10), buf, 20); /* serial number */
539
    put_le16(p + 20, 3); /* buffer type */
540
    put_le16(p + 21, 512); /* cache size in sectors */
541
    put_le16(p + 22, 4); /* ecc bytes */
542
    padstr((char *)(p + 23), QEMU_VERSION, 8); /* firmware version */
543
    padstr((char *)(p + 27), "QEMU CD-ROM", 40); /* model */
544
    put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
545
#ifdef USE_DMA_CDROM
546
    put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
547
    put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
548
    put_le16(p + 63, 7);  /* mdma0-2 supported */
549
    put_le16(p + 64, 0x3f); /* PIO modes supported */
550
#else
551
    put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
552
    put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
553
    put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
554
    put_le16(p + 64, 1); /* PIO modes */
555
#endif
556
    put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
557
    put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
558
    put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
559
    put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
560

    
561
    put_le16(p + 71, 30); /* in ns */
562
    put_le16(p + 72, 30); /* in ns */
563

    
564
    put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
565
#ifdef USE_DMA_CDROM
566
    put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
567
#endif
568
    memcpy(s->identify_data, p, sizeof(s->identify_data));
569
    s->identify_set = 1;
570
}
571

    
572
static void ide_cfata_identify(IDEState *s)
573
{
574
    uint16_t *p;
575
    uint32_t cur_sec;
576
    char buf[20];
577

    
578
    p = (uint16_t *) s->identify_data;
579
    if (s->identify_set)
580
        goto fill_buffer;
581

    
582
    memset(p, 0, sizeof(s->identify_data));
583

    
584
    cur_sec = s->cylinders * s->heads * s->sectors;
585

    
586
    put_le16(p + 0, 0x848a);                        /* CF Storage Card signature */
587
    put_le16(p + 1, s->cylinders);                /* Default cylinders */
588
    put_le16(p + 3, s->heads);                        /* Default heads */
589
    put_le16(p + 6, s->sectors);                /* Default sectors per track */
590
    put_le16(p + 7, s->nb_sectors >> 16);        /* Sectors per card */
591
    put_le16(p + 8, s->nb_sectors);                /* Sectors per card */
592
    snprintf(buf, sizeof(buf), "QM%05d", s->drive_serial);
593
    padstr((char *)(p + 10), buf, 20);        /* Serial number in ASCII */
594
    put_le16(p + 22, 0x0004);                        /* ECC bytes */
595
    padstr((char *) (p + 23), QEMU_VERSION, 8);        /* Firmware Revision */
596
    padstr((char *) (p + 27), "QEMU MICRODRIVE", 40);/* Model number */
597
#if MAX_MULT_SECTORS > 1
598
    put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
599
#else
600
    put_le16(p + 47, 0x0000);
601
#endif
602
    put_le16(p + 49, 0x0f00);                        /* Capabilities */
603
    put_le16(p + 51, 0x0002);                        /* PIO cycle timing mode */
604
    put_le16(p + 52, 0x0001);                        /* DMA cycle timing mode */
605
    put_le16(p + 53, 0x0003);                        /* Translation params valid */
606
    put_le16(p + 54, s->cylinders);                /* Current cylinders */
607
    put_le16(p + 55, s->heads);                        /* Current heads */
608
    put_le16(p + 56, s->sectors);                /* Current sectors */
609
    put_le16(p + 57, cur_sec);                        /* Current capacity */
610
    put_le16(p + 58, cur_sec >> 16);                /* Current capacity */
611
    if (s->mult_sectors)                        /* Multiple sector setting */
612
        put_le16(p + 59, 0x100 | s->mult_sectors);
613
    put_le16(p + 60, s->nb_sectors);                /* Total LBA sectors */
614
    put_le16(p + 61, s->nb_sectors >> 16);        /* Total LBA sectors */
615
    put_le16(p + 63, 0x0203);                        /* Multiword DMA capability */
616
    put_le16(p + 64, 0x0001);                        /* Flow Control PIO support */
617
    put_le16(p + 65, 0x0096);                        /* Min. Multiword DMA cycle */
618
    put_le16(p + 66, 0x0096);                        /* Rec. Multiword DMA cycle */
619
    put_le16(p + 68, 0x00b4);                        /* Min. PIO cycle time */
620
    put_le16(p + 82, 0x400c);                        /* Command Set supported */
621
    put_le16(p + 83, 0x7068);                        /* Command Set supported */
622
    put_le16(p + 84, 0x4000);                        /* Features supported */
623
    put_le16(p + 85, 0x000c);                        /* Command Set enabled */
624
    put_le16(p + 86, 0x7044);                        /* Command Set enabled */
625
    put_le16(p + 87, 0x4000);                        /* Features enabled */
626
    put_le16(p + 91, 0x4060);                        /* Current APM level */
627
    put_le16(p + 129, 0x0002);                        /* Current features option */
628
    put_le16(p + 130, 0x0005);                        /* Reassigned sectors */
629
    put_le16(p + 131, 0x0001);                        /* Initial power mode */
630
    put_le16(p + 132, 0x0000);                        /* User signature */
631
    put_le16(p + 160, 0x8100);                        /* Power requirement */
632
    put_le16(p + 161, 0x8001);                        /* CF command set */
633

    
634
    s->identify_set = 1;
635

    
636
fill_buffer:
637
    memcpy(s->io_buffer, p, sizeof(s->identify_data));
638
}
639

    
640
static void ide_set_signature(IDEState *s)
641
{
642
    s->select &= 0xf0; /* clear head */
643
    /* put signature */
644
    s->nsector = 1;
645
    s->sector = 1;
646
    if (s->is_cdrom) {
647
        s->lcyl = 0x14;
648
        s->hcyl = 0xeb;
649
    } else if (s->bs) {
650
        s->lcyl = 0;
651
        s->hcyl = 0;
652
    } else {
653
        s->lcyl = 0xff;
654
        s->hcyl = 0xff;
655
    }
656
}
657

    
658
static inline void ide_abort_command(IDEState *s)
659
{
660
    s->status = READY_STAT | ERR_STAT;
661
    s->error = ABRT_ERR;
662
}
663

    
664
static inline void ide_set_irq(IDEState *s)
665
{
666
    BMDMAState *bm = s->bmdma;
667
    if (!(s->cmd & IDE_CMD_DISABLE_IRQ)) {
668
        if (bm) {
669
            bm->status |= BM_STATUS_INT;
670
        }
671
        qemu_irq_raise(s->irq);
672
    }
673
}
674

    
675
/* prepare data transfer and tell what to do after */
676
static void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
677
                               EndTransferFunc *end_transfer_func)
678
{
679
    s->end_transfer_func = end_transfer_func;
680
    s->data_ptr = buf;
681
    s->data_end = buf + size;
682
    if (!(s->status & ERR_STAT))
683
        s->status |= DRQ_STAT;
684
}
685

    
686
static void ide_transfer_stop(IDEState *s)
687
{
688
    s->end_transfer_func = ide_transfer_stop;
689
    s->data_ptr = s->io_buffer;
690
    s->data_end = s->io_buffer;
691
    s->status &= ~DRQ_STAT;
692
}
693

    
694
static int64_t ide_get_sector(IDEState *s)
695
{
696
    int64_t sector_num;
697
    if (s->select & 0x40) {
698
        /* lba */
699
        if (!s->lba48) {
700
            sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
701
                (s->lcyl << 8) | s->sector;
702
        } else {
703
            sector_num = ((int64_t)s->hob_hcyl << 40) |
704
                ((int64_t) s->hob_lcyl << 32) |
705
                ((int64_t) s->hob_sector << 24) |
706
                ((int64_t) s->hcyl << 16) |
707
                ((int64_t) s->lcyl << 8) | s->sector;
708
        }
709
    } else {
710
        sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
711
            (s->select & 0x0f) * s->sectors + (s->sector - 1);
712
    }
713
    return sector_num;
714
}
715

    
716
static void ide_set_sector(IDEState *s, int64_t sector_num)
717
{
718
    unsigned int cyl, r;
719
    if (s->select & 0x40) {
720
        if (!s->lba48) {
721
            s->select = (s->select & 0xf0) | (sector_num >> 24);
722
            s->hcyl = (sector_num >> 16);
723
            s->lcyl = (sector_num >> 8);
724
            s->sector = (sector_num);
725
        } else {
726
            s->sector = sector_num;
727
            s->lcyl = sector_num >> 8;
728
            s->hcyl = sector_num >> 16;
729
            s->hob_sector = sector_num >> 24;
730
            s->hob_lcyl = sector_num >> 32;
731
            s->hob_hcyl = sector_num >> 40;
732
        }
733
    } else {
734
        cyl = sector_num / (s->heads * s->sectors);
735
        r = sector_num % (s->heads * s->sectors);
736
        s->hcyl = cyl >> 8;
737
        s->lcyl = cyl;
738
        s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
739
        s->sector = (r % s->sectors) + 1;
740
    }
741
}
742

    
743
static void ide_sector_read(IDEState *s)
744
{
745
    int64_t sector_num;
746
    int ret, n;
747

    
748
    s->status = READY_STAT | SEEK_STAT;
749
    s->error = 0; /* not needed by IDE spec, but needed by Windows */
750
    sector_num = ide_get_sector(s);
751
    n = s->nsector;
752
    if (n == 0) {
753
        /* no more sector to read from disk */
754
        ide_transfer_stop(s);
755
    } else {
756
#if defined(DEBUG_IDE)
757
        printf("read sector=%Ld\n", sector_num);
758
#endif
759
        if (n > s->req_nb_sectors)
760
            n = s->req_nb_sectors;
761
        ret = bdrv_read(s->bs, sector_num, s->io_buffer, n);
762
        ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_read);
763
        ide_set_irq(s);
764
        ide_set_sector(s, sector_num + n);
765
        s->nsector -= n;
766
    }
767
}
768

    
769
/* return 0 if buffer completed */
770
static int dma_buf_rw(BMDMAState *bm, int is_write)
771
{
772
    IDEState *s = bm->ide_if;
773
    struct {
774
        uint32_t addr;
775
        uint32_t size;
776
    } prd;
777
    int l, len;
778

    
779
    for(;;) {
780
        l = s->io_buffer_size - s->io_buffer_index;
781
        if (l <= 0)
782
            break;
783
        if (bm->cur_prd_len == 0) {
784
            /* end of table (with a fail safe of one page) */
785
            if (bm->cur_prd_last ||
786
                (bm->cur_addr - bm->addr) >= 4096)
787
                return 0;
788
            cpu_physical_memory_read(bm->cur_addr, (uint8_t *)&prd, 8);
789
            bm->cur_addr += 8;
790
            prd.addr = le32_to_cpu(prd.addr);
791
            prd.size = le32_to_cpu(prd.size);
792
            len = prd.size & 0xfffe;
793
            if (len == 0)
794
                len = 0x10000;
795
            bm->cur_prd_len = len;
796
            bm->cur_prd_addr = prd.addr;
797
            bm->cur_prd_last = (prd.size & 0x80000000);
798
        }
799
        if (l > bm->cur_prd_len)
800
            l = bm->cur_prd_len;
801
        if (l > 0) {
802
            if (is_write) {
803
                cpu_physical_memory_write(bm->cur_prd_addr,
804
                                          s->io_buffer + s->io_buffer_index, l);
805
            } else {
806
                cpu_physical_memory_read(bm->cur_prd_addr,
807
                                          s->io_buffer + s->io_buffer_index, l);
808
            }
809
            bm->cur_prd_addr += l;
810
            bm->cur_prd_len -= l;
811
            s->io_buffer_index += l;
812
        }
813
    }
814
    return 1;
815
}
816

    
817
/* XXX: handle errors */
818
static void ide_read_dma_cb(void *opaque, int ret)
819
{
820
    BMDMAState *bm = opaque;
821
    IDEState *s = bm->ide_if;
822
    int n;
823
    int64_t sector_num;
824

    
825
    n = s->io_buffer_size >> 9;
826
    sector_num = ide_get_sector(s);
827
    if (n > 0) {
828
        sector_num += n;
829
        ide_set_sector(s, sector_num);
830
        s->nsector -= n;
831
        if (dma_buf_rw(bm, 1) == 0)
832
            goto eot;
833
    }
834

    
835
    /* end of transfer ? */
836
    if (s->nsector == 0) {
837
        s->status = READY_STAT | SEEK_STAT;
838
        ide_set_irq(s);
839
    eot:
840
        bm->status &= ~BM_STATUS_DMAING;
841
        bm->status |= BM_STATUS_INT;
842
        bm->dma_cb = NULL;
843
        bm->ide_if = NULL;
844
        bm->aiocb = NULL;
845
        return;
846
    }
847

    
848
    /* launch next transfer */
849
    n = s->nsector;
850
    if (n > MAX_MULT_SECTORS)
851
        n = MAX_MULT_SECTORS;
852
    s->io_buffer_index = 0;
853
    s->io_buffer_size = n * 512;
854
#ifdef DEBUG_AIO
855
    printf("aio_read: sector_num=%lld n=%d\n", sector_num, n);
856
#endif
857
    bm->aiocb = bdrv_aio_read(s->bs, sector_num, s->io_buffer, n,
858
                              ide_read_dma_cb, bm);
859
}
860

    
861
static void ide_sector_read_dma(IDEState *s)
862
{
863
    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
864
    s->io_buffer_index = 0;
865
    s->io_buffer_size = 0;
866
    ide_dma_start(s, ide_read_dma_cb);
867
}
868

    
869
static void ide_sector_write_timer_cb(void *opaque)
870
{
871
    IDEState *s = opaque;
872
    ide_set_irq(s);
873
}
874

    
875
static void ide_sector_write(IDEState *s)
876
{
877
    int64_t sector_num;
878
    int ret, n, n1;
879

    
880
    s->status = READY_STAT | SEEK_STAT;
881
    sector_num = ide_get_sector(s);
882
#if defined(DEBUG_IDE)
883
    printf("write sector=%Ld\n", sector_num);
884
#endif
885
    n = s->nsector;
886
    if (n > s->req_nb_sectors)
887
        n = s->req_nb_sectors;
888
    ret = bdrv_write(s->bs, sector_num, s->io_buffer, n);
889
    s->nsector -= n;
890
    if (s->nsector == 0) {
891
        /* no more sectors to write */
892
        ide_transfer_stop(s);
893
    } else {
894
        n1 = s->nsector;
895
        if (n1 > s->req_nb_sectors)
896
            n1 = s->req_nb_sectors;
897
        ide_transfer_start(s, s->io_buffer, 512 * n1, ide_sector_write);
898
    }
899
    ide_set_sector(s, sector_num + n);
900

    
901
#ifdef TARGET_I386
902
    if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
903
        /* It seems there is a bug in the Windows 2000 installer HDD
904
           IDE driver which fills the disk with empty logs when the
905
           IDE write IRQ comes too early. This hack tries to correct
906
           that at the expense of slower write performances. Use this
907
           option _only_ to install Windows 2000. You must disable it
908
           for normal use. */
909
        qemu_mod_timer(s->sector_write_timer, 
910
                       qemu_get_clock(vm_clock) + (ticks_per_sec / 1000));
911
    } else 
912
#endif
913
    {
914
        ide_set_irq(s);
915
    }
916
}
917

    
918
/* XXX: handle errors */
919
static void ide_write_dma_cb(void *opaque, int ret)
920
{
921
    BMDMAState *bm = opaque;
922
    IDEState *s = bm->ide_if;
923
    int n;
924
    int64_t sector_num;
925

    
926
    n = s->io_buffer_size >> 9;
927
    sector_num = ide_get_sector(s);
928
    if (n > 0) {
929
        sector_num += n;
930
        ide_set_sector(s, sector_num);
931
        s->nsector -= n;
932
    }
933

    
934
    /* end of transfer ? */
935
    if (s->nsector == 0) {
936
        s->status = READY_STAT | SEEK_STAT;
937
        ide_set_irq(s);
938
    eot:
939
        bm->status &= ~BM_STATUS_DMAING;
940
        bm->status |= BM_STATUS_INT;
941
        bm->dma_cb = NULL;
942
        bm->ide_if = NULL;
943
        bm->aiocb = NULL;
944
        return;
945
    }
946

    
947
    /* launch next transfer */
948
    n = s->nsector;
949
    if (n > MAX_MULT_SECTORS)
950
        n = MAX_MULT_SECTORS;
951
    s->io_buffer_index = 0;
952
    s->io_buffer_size = n * 512;
953

    
954
    if (dma_buf_rw(bm, 0) == 0)
955
        goto eot;
956
#ifdef DEBUG_AIO
957
    printf("aio_write: sector_num=%lld n=%d\n", sector_num, n);
958
#endif
959
    bm->aiocb = bdrv_aio_write(s->bs, sector_num, s->io_buffer, n,
960
                               ide_write_dma_cb, bm);
961
}
962

    
963
static void ide_sector_write_dma(IDEState *s)
964
{
965
    s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
966
    s->io_buffer_index = 0;
967
    s->io_buffer_size = 0;
968
    ide_dma_start(s, ide_write_dma_cb);
969
}
970

    
971
static void ide_atapi_cmd_ok(IDEState *s)
972
{
973
    s->error = 0;
974
    s->status = READY_STAT;
975
    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
976
    ide_set_irq(s);
977
}
978

    
979
static void ide_atapi_cmd_error(IDEState *s, int sense_key, int asc)
980
{
981
#ifdef DEBUG_IDE_ATAPI
982
    printf("atapi_cmd_error: sense=0x%x asc=0x%x\n", sense_key, asc);
983
#endif
984
    s->error = sense_key << 4;
985
    s->status = READY_STAT | ERR_STAT;
986
    s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
987
    s->sense_key = sense_key;
988
    s->asc = asc;
989
    ide_set_irq(s);
990
}
991

    
992
static inline void cpu_to_ube16(uint8_t *buf, int val)
993
{
994
    buf[0] = val >> 8;
995
    buf[1] = val;
996
}
997

    
998
static inline void cpu_to_ube32(uint8_t *buf, unsigned int val)
999
{
1000
    buf[0] = val >> 24;
1001
    buf[1] = val >> 16;
1002
    buf[2] = val >> 8;
1003
    buf[3] = val;
1004
}
1005

    
1006
static inline int ube16_to_cpu(const uint8_t *buf)
1007
{
1008
    return (buf[0] << 8) | buf[1];
1009
}
1010

    
1011
static inline int ube32_to_cpu(const uint8_t *buf)
1012
{
1013
    return (buf[0] << 24) | (buf[1] << 16) | (buf[2] << 8) | buf[3];
1014
}
1015

    
1016
static void lba_to_msf(uint8_t *buf, int lba)
1017
{
1018
    lba += 150;
1019
    buf[0] = (lba / 75) / 60;
1020
    buf[1] = (lba / 75) % 60;
1021
    buf[2] = lba % 75;
1022
}
1023

    
1024
static void cd_data_to_raw(uint8_t *buf, int lba)
1025
{
1026
    /* sync bytes */
1027
    buf[0] = 0x00;
1028
    memset(buf + 1, 0xff, 10);
1029
    buf[11] = 0x00;
1030
    buf += 12;
1031
    /* MSF */
1032
    lba_to_msf(buf, lba);
1033
    buf[3] = 0x01; /* mode 1 data */
1034
    buf += 4;
1035
    /* data */
1036
    buf += 2048;
1037
    /* XXX: ECC not computed */
1038
    memset(buf, 0, 288);
1039
}
1040

    
1041
static int cd_read_sector(BlockDriverState *bs, int lba, uint8_t *buf,
1042
                           int sector_size)
1043
{
1044
    int ret;
1045

    
1046
    switch(sector_size) {
1047
    case 2048:
1048
        ret = bdrv_read(bs, (int64_t)lba << 2, buf, 4);
1049
        break;
1050
    case 2352:
1051
        ret = bdrv_read(bs, (int64_t)lba << 2, buf + 16, 4);
1052
        if (ret < 0)
1053
            return ret;
1054
        cd_data_to_raw(buf, lba);
1055
        break;
1056
    default:
1057
        ret = -EIO;
1058
        break;
1059
    }
1060
    return ret;
1061
}
1062

    
1063
static void ide_atapi_io_error(IDEState *s, int ret)
1064
{
1065
    /* XXX: handle more errors */
1066
    if (ret == -ENOMEDIUM) {
1067
        ide_atapi_cmd_error(s, SENSE_NOT_READY,
1068
                            ASC_MEDIUM_NOT_PRESENT);
1069
    } else {
1070
        ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1071
                            ASC_LOGICAL_BLOCK_OOR);
1072
    }
1073
}
1074

    
1075
/* The whole ATAPI transfer logic is handled in this function */
1076
static void ide_atapi_cmd_reply_end(IDEState *s)
1077
{
1078
    int byte_count_limit, size, ret;
1079
#ifdef DEBUG_IDE_ATAPI
1080
    printf("reply: tx_size=%d elem_tx_size=%d index=%d\n",
1081
           s->packet_transfer_size,
1082
           s->elementary_transfer_size,
1083
           s->io_buffer_index);
1084
#endif
1085
    if (s->packet_transfer_size <= 0) {
1086
        /* end of transfer */
1087
        ide_transfer_stop(s);
1088
        s->status = READY_STAT;
1089
        s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1090
        ide_set_irq(s);
1091
#ifdef DEBUG_IDE_ATAPI
1092
        printf("status=0x%x\n", s->status);
1093
#endif
1094
    } else {
1095
        /* see if a new sector must be read */
1096
        if (s->lba != -1 && s->io_buffer_index >= s->cd_sector_size) {
1097
            ret = cd_read_sector(s->bs, s->lba, s->io_buffer, s->cd_sector_size);
1098
            if (ret < 0) {
1099
                ide_transfer_stop(s);
1100
                ide_atapi_io_error(s, ret);
1101
                return;
1102
            }
1103
            s->lba++;
1104
            s->io_buffer_index = 0;
1105
        }
1106
        if (s->elementary_transfer_size > 0) {
1107
            /* there are some data left to transmit in this elementary
1108
               transfer */
1109
            size = s->cd_sector_size - s->io_buffer_index;
1110
            if (size > s->elementary_transfer_size)
1111
                size = s->elementary_transfer_size;
1112
            ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
1113
                               size, ide_atapi_cmd_reply_end);
1114
            s->packet_transfer_size -= size;
1115
            s->elementary_transfer_size -= size;
1116
            s->io_buffer_index += size;
1117
        } else {
1118
            /* a new transfer is needed */
1119
            s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO;
1120
            byte_count_limit = s->lcyl | (s->hcyl << 8);
1121
#ifdef DEBUG_IDE_ATAPI
1122
            printf("byte_count_limit=%d\n", byte_count_limit);
1123
#endif
1124
            if (byte_count_limit == 0xffff)
1125
                byte_count_limit--;
1126
            size = s->packet_transfer_size;
1127
            if (size > byte_count_limit) {
1128
                /* byte count limit must be even if this case */
1129
                if (byte_count_limit & 1)
1130
                    byte_count_limit--;
1131
                size = byte_count_limit;
1132
            }
1133
            s->lcyl = size;
1134
            s->hcyl = size >> 8;
1135
            s->elementary_transfer_size = size;
1136
            /* we cannot transmit more than one sector at a time */
1137
            if (s->lba != -1) {
1138
                if (size > (s->cd_sector_size - s->io_buffer_index))
1139
                    size = (s->cd_sector_size - s->io_buffer_index);
1140
            }
1141
            ide_transfer_start(s, s->io_buffer + s->io_buffer_index,
1142
                               size, ide_atapi_cmd_reply_end);
1143
            s->packet_transfer_size -= size;
1144
            s->elementary_transfer_size -= size;
1145
            s->io_buffer_index += size;
1146
            ide_set_irq(s);
1147
#ifdef DEBUG_IDE_ATAPI
1148
            printf("status=0x%x\n", s->status);
1149
#endif
1150
        }
1151
    }
1152
}
1153

    
1154
/* send a reply of 'size' bytes in s->io_buffer to an ATAPI command */
1155
static void ide_atapi_cmd_reply(IDEState *s, int size, int max_size)
1156
{
1157
    if (size > max_size)
1158
        size = max_size;
1159
    s->lba = -1; /* no sector read */
1160
    s->packet_transfer_size = size;
1161
    s->io_buffer_size = size;    /* dma: send the reply data as one chunk */
1162
    s->elementary_transfer_size = 0;
1163
    s->io_buffer_index = 0;
1164

    
1165
    if (s->atapi_dma) {
1166
            s->status = READY_STAT | DRQ_STAT;
1167
        ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
1168
    } else {
1169
            s->status = READY_STAT;
1170
            ide_atapi_cmd_reply_end(s);
1171
    }
1172
}
1173

    
1174
/* start a CD-CDROM read command */
1175
static void ide_atapi_cmd_read_pio(IDEState *s, int lba, int nb_sectors,
1176
                                   int sector_size)
1177
{
1178
    s->lba = lba;
1179
    s->packet_transfer_size = nb_sectors * sector_size;
1180
    s->elementary_transfer_size = 0;
1181
    s->io_buffer_index = sector_size;
1182
    s->cd_sector_size = sector_size;
1183

    
1184
    s->status = READY_STAT;
1185
    ide_atapi_cmd_reply_end(s);
1186
}
1187

    
1188
/* ATAPI DMA support */
1189

    
1190
/* XXX: handle read errors */
1191
static void ide_atapi_cmd_read_dma_cb(void *opaque, int ret)
1192
{
1193
    BMDMAState *bm = opaque;
1194
    IDEState *s = bm->ide_if;
1195
    int data_offset, n;
1196

    
1197
    if (ret < 0) {
1198
        ide_atapi_io_error(s, ret);
1199
        goto eot;
1200
    }
1201

    
1202
    if (s->io_buffer_size > 0) {
1203
        /*
1204
         * For a cdrom read sector command (s->lba != -1),
1205
         * adjust the lba for the next s->io_buffer_size chunk
1206
         * and dma the current chunk.
1207
         * For a command != read (s->lba == -1), just transfer
1208
         * the reply data.
1209
         */
1210
        if (s->lba != -1) {
1211
            if (s->cd_sector_size == 2352) {
1212
                n = 1;
1213
                cd_data_to_raw(s->io_buffer, s->lba);
1214
            } else {
1215
                n = s->io_buffer_size >> 11;
1216
            }
1217
            s->lba += n;
1218
        }
1219
        s->packet_transfer_size -= s->io_buffer_size;
1220
        if (dma_buf_rw(bm, 1) == 0)
1221
            goto eot;
1222
    }
1223

    
1224
    if (s->packet_transfer_size <= 0) {
1225
        s->status = READY_STAT;
1226
        s->nsector = (s->nsector & ~7) | ATAPI_INT_REASON_IO | ATAPI_INT_REASON_CD;
1227
        ide_set_irq(s);
1228
    eot:
1229
        bm->status &= ~BM_STATUS_DMAING;
1230
        bm->status |= BM_STATUS_INT;
1231
        bm->dma_cb = NULL;
1232
        bm->ide_if = NULL;
1233
        bm->aiocb = NULL;
1234
        return;
1235
    }
1236

    
1237
    s->io_buffer_index = 0;
1238
    if (s->cd_sector_size == 2352) {
1239
        n = 1;
1240
        s->io_buffer_size = s->cd_sector_size;
1241
        data_offset = 16;
1242
    } else {
1243
        n = s->packet_transfer_size >> 11;
1244
        if (n > (MAX_MULT_SECTORS / 4))
1245
            n = (MAX_MULT_SECTORS / 4);
1246
        s->io_buffer_size = n * 2048;
1247
        data_offset = 0;
1248
    }
1249
#ifdef DEBUG_AIO
1250
    printf("aio_read_cd: lba=%u n=%d\n", s->lba, n);
1251
#endif
1252
    bm->aiocb = bdrv_aio_read(s->bs, (int64_t)s->lba << 2,
1253
                              s->io_buffer + data_offset, n * 4,
1254
                              ide_atapi_cmd_read_dma_cb, bm);
1255
    if (!bm->aiocb) {
1256
        /* Note: media not present is the most likely case */
1257
        ide_atapi_cmd_error(s, SENSE_NOT_READY,
1258
                            ASC_MEDIUM_NOT_PRESENT);
1259
        goto eot;
1260
    }
1261
}
1262

    
1263
/* start a CD-CDROM read command with DMA */
1264
/* XXX: test if DMA is available */
1265
static void ide_atapi_cmd_read_dma(IDEState *s, int lba, int nb_sectors,
1266
                                   int sector_size)
1267
{
1268
    s->lba = lba;
1269
    s->packet_transfer_size = nb_sectors * sector_size;
1270
    s->io_buffer_index = 0;
1271
    s->io_buffer_size = 0;
1272
    s->cd_sector_size = sector_size;
1273

    
1274
    /* XXX: check if BUSY_STAT should be set */
1275
    s->status = READY_STAT | DRQ_STAT | BUSY_STAT;
1276
    ide_dma_start(s, ide_atapi_cmd_read_dma_cb);
1277
}
1278

    
1279
static void ide_atapi_cmd_read(IDEState *s, int lba, int nb_sectors,
1280
                               int sector_size)
1281
{
1282
#ifdef DEBUG_IDE_ATAPI
1283
    printf("read %s: LBA=%d nb_sectors=%d\n", s->atapi_dma ? "dma" : "pio",
1284
        lba, nb_sectors);
1285
#endif
1286
    if (s->atapi_dma) {
1287
        ide_atapi_cmd_read_dma(s, lba, nb_sectors, sector_size);
1288
    } else {
1289
        ide_atapi_cmd_read_pio(s, lba, nb_sectors, sector_size);
1290
    }
1291
}
1292

    
1293
static void ide_atapi_cmd(IDEState *s)
1294
{
1295
    const uint8_t *packet;
1296
    uint8_t *buf;
1297
    int max_len;
1298

    
1299
    packet = s->io_buffer;
1300
    buf = s->io_buffer;
1301
#ifdef DEBUG_IDE_ATAPI
1302
    {
1303
        int i;
1304
        printf("ATAPI limit=0x%x packet:", s->lcyl | (s->hcyl << 8));
1305
        for(i = 0; i < ATAPI_PACKET_SIZE; i++) {
1306
            printf(" %02x", packet[i]);
1307
        }
1308
        printf("\n");
1309
    }
1310
#endif
1311
    switch(s->io_buffer[0]) {
1312
    case GPCMD_TEST_UNIT_READY:
1313
        if (bdrv_is_inserted(s->bs)) {
1314
            ide_atapi_cmd_ok(s);
1315
        } else {
1316
            ide_atapi_cmd_error(s, SENSE_NOT_READY,
1317
                                ASC_MEDIUM_NOT_PRESENT);
1318
        }
1319
        break;
1320
    case GPCMD_MODE_SENSE_6:
1321
    case GPCMD_MODE_SENSE_10:
1322
        {
1323
            int action, code;
1324
            if (packet[0] == GPCMD_MODE_SENSE_10)
1325
                max_len = ube16_to_cpu(packet + 7);
1326
            else
1327
                max_len = packet[4];
1328
            action = packet[2] >> 6;
1329
            code = packet[2] & 0x3f;
1330
            switch(action) {
1331
            case 0: /* current values */
1332
                switch(code) {
1333
                case 0x01: /* error recovery */
1334
                    cpu_to_ube16(&buf[0], 16 + 6);
1335
                    buf[2] = 0x70;
1336
                    buf[3] = 0;
1337
                    buf[4] = 0;
1338
                    buf[5] = 0;
1339
                    buf[6] = 0;
1340
                    buf[7] = 0;
1341

    
1342
                    buf[8] = 0x01;
1343
                    buf[9] = 0x06;
1344
                    buf[10] = 0x00;
1345
                    buf[11] = 0x05;
1346
                    buf[12] = 0x00;
1347
                    buf[13] = 0x00;
1348
                    buf[14] = 0x00;
1349
                    buf[15] = 0x00;
1350
                    ide_atapi_cmd_reply(s, 16, max_len);
1351
                    break;
1352
                case 0x2a:
1353
                    cpu_to_ube16(&buf[0], 28 + 6);
1354
                    buf[2] = 0x70;
1355
                    buf[3] = 0;
1356
                    buf[4] = 0;
1357
                    buf[5] = 0;
1358
                    buf[6] = 0;
1359
                    buf[7] = 0;
1360

    
1361
                    buf[8] = 0x2a;
1362
                    buf[9] = 0x12;
1363
                    buf[10] = 0x00;
1364
                    buf[11] = 0x00;
1365

    
1366
                    buf[12] = 0x70;
1367
                    buf[13] = 3 << 5;
1368
                    buf[14] = (1 << 0) | (1 << 3) | (1 << 5);
1369
                    if (bdrv_is_locked(s->bs))
1370
                        buf[6] |= 1 << 1;
1371
                    buf[15] = 0x00;
1372
                    cpu_to_ube16(&buf[16], 706);
1373
                    buf[18] = 0;
1374
                    buf[19] = 2;
1375
                    cpu_to_ube16(&buf[20], 512);
1376
                    cpu_to_ube16(&buf[22], 706);
1377
                    buf[24] = 0;
1378
                    buf[25] = 0;
1379
                    buf[26] = 0;
1380
                    buf[27] = 0;
1381
                    ide_atapi_cmd_reply(s, 28, max_len);
1382
                    break;
1383
                default:
1384
                    goto error_cmd;
1385
                }
1386
                break;
1387
            case 1: /* changeable values */
1388
                goto error_cmd;
1389
            case 2: /* default values */
1390
                goto error_cmd;
1391
            default:
1392
            case 3: /* saved values */
1393
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1394
                                    ASC_SAVING_PARAMETERS_NOT_SUPPORTED);
1395
                break;
1396
            }
1397
        }
1398
        break;
1399
    case GPCMD_REQUEST_SENSE:
1400
        max_len = packet[4];
1401
        memset(buf, 0, 18);
1402
        buf[0] = 0x70 | (1 << 7);
1403
        buf[2] = s->sense_key;
1404
        buf[7] = 10;
1405
        buf[12] = s->asc;
1406
        ide_atapi_cmd_reply(s, 18, max_len);
1407
        break;
1408
    case GPCMD_PREVENT_ALLOW_MEDIUM_REMOVAL:
1409
        if (bdrv_is_inserted(s->bs)) {
1410
            bdrv_set_locked(s->bs, packet[4] & 1);
1411
            ide_atapi_cmd_ok(s);
1412
        } else {
1413
            ide_atapi_cmd_error(s, SENSE_NOT_READY,
1414
                                ASC_MEDIUM_NOT_PRESENT);
1415
        }
1416
        break;
1417
    case GPCMD_READ_10:
1418
    case GPCMD_READ_12:
1419
        {
1420
            int nb_sectors, lba;
1421

    
1422
            if (packet[0] == GPCMD_READ_10)
1423
                nb_sectors = ube16_to_cpu(packet + 7);
1424
            else
1425
                nb_sectors = ube32_to_cpu(packet + 6);
1426
            lba = ube32_to_cpu(packet + 2);
1427
            if (nb_sectors == 0) {
1428
                ide_atapi_cmd_ok(s);
1429
                break;
1430
            }
1431
            ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1432
        }
1433
        break;
1434
    case GPCMD_READ_CD:
1435
        {
1436
            int nb_sectors, lba, transfer_request;
1437

    
1438
            nb_sectors = (packet[6] << 16) | (packet[7] << 8) | packet[8];
1439
            lba = ube32_to_cpu(packet + 2);
1440
            if (nb_sectors == 0) {
1441
                ide_atapi_cmd_ok(s);
1442
                break;
1443
            }
1444
            transfer_request = packet[9];
1445
            switch(transfer_request & 0xf8) {
1446
            case 0x00:
1447
                /* nothing */
1448
                ide_atapi_cmd_ok(s);
1449
                break;
1450
            case 0x10:
1451
                /* normal read */
1452
                ide_atapi_cmd_read(s, lba, nb_sectors, 2048);
1453
                break;
1454
            case 0xf8:
1455
                /* read all data */
1456
                ide_atapi_cmd_read(s, lba, nb_sectors, 2352);
1457
                break;
1458
            default:
1459
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1460
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1461
                break;
1462
            }
1463
        }
1464
        break;
1465
    case GPCMD_SEEK:
1466
        {
1467
            unsigned int lba;
1468
            uint64_t total_sectors;
1469

    
1470
            bdrv_get_geometry(s->bs, &total_sectors);
1471
            total_sectors >>= 2;
1472
            if (total_sectors == 0) {
1473
                ide_atapi_cmd_error(s, SENSE_NOT_READY,
1474
                                    ASC_MEDIUM_NOT_PRESENT);
1475
                break;
1476
            }
1477
            lba = ube32_to_cpu(packet + 2);
1478
            if (lba >= total_sectors) {
1479
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1480
                                    ASC_LOGICAL_BLOCK_OOR);
1481
                break;
1482
            }
1483
            ide_atapi_cmd_ok(s);
1484
        }
1485
        break;
1486
    case GPCMD_START_STOP_UNIT:
1487
        {
1488
            int start, eject;
1489
            start = packet[4] & 1;
1490
            eject = (packet[4] >> 1) & 1;
1491

    
1492
            if (eject && !start) {
1493
                /* eject the disk */
1494
                bdrv_eject(s->bs, 1);
1495
            } else if (eject && start) {
1496
                /* close the tray */
1497
                bdrv_eject(s->bs, 0);
1498
            }
1499
            ide_atapi_cmd_ok(s);
1500
        }
1501
        break;
1502
    case GPCMD_MECHANISM_STATUS:
1503
        {
1504
            max_len = ube16_to_cpu(packet + 8);
1505
            cpu_to_ube16(buf, 0);
1506
            /* no current LBA */
1507
            buf[2] = 0;
1508
            buf[3] = 0;
1509
            buf[4] = 0;
1510
            buf[5] = 1;
1511
            cpu_to_ube16(buf + 6, 0);
1512
            ide_atapi_cmd_reply(s, 8, max_len);
1513
        }
1514
        break;
1515
    case GPCMD_READ_TOC_PMA_ATIP:
1516
        {
1517
            int format, msf, start_track, len;
1518
            uint64_t total_sectors;
1519

    
1520
            bdrv_get_geometry(s->bs, &total_sectors);
1521
            total_sectors >>= 2;
1522
            if (total_sectors == 0) {
1523
                ide_atapi_cmd_error(s, SENSE_NOT_READY,
1524
                                    ASC_MEDIUM_NOT_PRESENT);
1525
                break;
1526
            }
1527
            max_len = ube16_to_cpu(packet + 7);
1528
            format = packet[9] >> 6;
1529
            msf = (packet[1] >> 1) & 1;
1530
            start_track = packet[6];
1531
            switch(format) {
1532
            case 0:
1533
                len = cdrom_read_toc(total_sectors, buf, msf, start_track);
1534
                if (len < 0)
1535
                    goto error_cmd;
1536
                ide_atapi_cmd_reply(s, len, max_len);
1537
                break;
1538
            case 1:
1539
                /* multi session : only a single session defined */
1540
                memset(buf, 0, 12);
1541
                buf[1] = 0x0a;
1542
                buf[2] = 0x01;
1543
                buf[3] = 0x01;
1544
                ide_atapi_cmd_reply(s, 12, max_len);
1545
                break;
1546
            case 2:
1547
                len = cdrom_read_toc_raw(total_sectors, buf, msf, start_track);
1548
                if (len < 0)
1549
                    goto error_cmd;
1550
                ide_atapi_cmd_reply(s, len, max_len);
1551
                break;
1552
            default:
1553
            error_cmd:
1554
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1555
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1556
                break;
1557
            }
1558
        }
1559
        break;
1560
    case GPCMD_READ_CDVD_CAPACITY:
1561
        {
1562
            uint64_t total_sectors;
1563

    
1564
            bdrv_get_geometry(s->bs, &total_sectors);
1565
            total_sectors >>= 2;
1566
            if (total_sectors == 0) {
1567
                ide_atapi_cmd_error(s, SENSE_NOT_READY,
1568
                                    ASC_MEDIUM_NOT_PRESENT);
1569
                break;
1570
            }
1571
            /* NOTE: it is really the number of sectors minus 1 */
1572
            cpu_to_ube32(buf, total_sectors - 1);
1573
            cpu_to_ube32(buf + 4, 2048);
1574
            ide_atapi_cmd_reply(s, 8, 8);
1575
        }
1576
        break;
1577
    case GPCMD_READ_DVD_STRUCTURE:
1578
        {
1579
            int media = packet[1];
1580
            int layer = packet[6];
1581
            int format = packet[2];
1582
            uint64_t total_sectors;
1583

    
1584
            if (media != 0 || layer != 0)
1585
            {
1586
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1587
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1588
            }
1589

    
1590
            switch (format) {
1591
                case 0:
1592
                    bdrv_get_geometry(s->bs, &total_sectors);
1593
                    total_sectors >>= 2;
1594
                    if (total_sectors == 0) {
1595
                        ide_atapi_cmd_error(s, SENSE_NOT_READY,
1596
                                            ASC_MEDIUM_NOT_PRESENT);
1597
                        break;
1598
                    }
1599

    
1600
                    memset(buf, 0, 2052);
1601

    
1602
                    buf[4] = 1;   // DVD-ROM, part version 1
1603
                    buf[5] = 0xf; // 120mm disc, maximum rate unspecified
1604
                    buf[6] = 0;   // one layer, embossed data
1605
                    buf[7] = 0;
1606

    
1607
                    cpu_to_ube32(buf + 8, 0);
1608
                    cpu_to_ube32(buf + 12, total_sectors - 1);
1609
                    cpu_to_ube32(buf + 16, total_sectors - 1);
1610

    
1611
                    cpu_to_be16wu((uint16_t *)buf, 2048 + 4);
1612

    
1613
                    ide_atapi_cmd_reply(s, 2048 + 3, 2048 + 4);
1614
                    break;
1615

    
1616
                default:
1617
                    ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1618
                                        ASC_INV_FIELD_IN_CMD_PACKET);
1619
                    break;
1620
            }
1621
        }
1622
        break;
1623
    case GPCMD_SET_SPEED:
1624
        ide_atapi_cmd_ok(s);
1625
        break;
1626
    case GPCMD_INQUIRY:
1627
        max_len = packet[4];
1628
        buf[0] = 0x05; /* CD-ROM */
1629
        buf[1] = 0x80; /* removable */
1630
        buf[2] = 0x00; /* ISO */
1631
        buf[3] = 0x21; /* ATAPI-2 (XXX: put ATAPI-4 ?) */
1632
        buf[4] = 31; /* additional length */
1633
        buf[5] = 0; /* reserved */
1634
        buf[6] = 0; /* reserved */
1635
        buf[7] = 0; /* reserved */
1636
        padstr8(buf + 8, 8, "QEMU");
1637
        padstr8(buf + 16, 16, "QEMU CD-ROM");
1638
        padstr8(buf + 32, 4, QEMU_VERSION);
1639
        ide_atapi_cmd_reply(s, 36, max_len);
1640
        break;
1641
    case GPCMD_GET_CONFIGURATION:
1642
        {
1643
            uint64_t total_sectors;
1644

    
1645
            /* only feature 0 is supported */
1646
            if (packet[2] != 0 || packet[3] != 0) {
1647
                ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1648
                                    ASC_INV_FIELD_IN_CMD_PACKET);
1649
                break;
1650
            }
1651
            memset(buf, 0, 32);
1652
            bdrv_get_geometry(s->bs, &total_sectors);
1653
            buf[3] = 16;
1654
            buf[7] = total_sectors <= 1433600 ? 0x08 : 0x10; /* current profile */
1655
            buf[10] = 0x10 | 0x1;
1656
            buf[11] = 0x08; /* size of profile list */
1657
            buf[13] = 0x10; /* DVD-ROM profile */
1658
            buf[14] = buf[7] == 0x10; /* (in)active */
1659
            buf[17] = 0x08; /* CD-ROM profile */
1660
            buf[18] = buf[7] == 0x08; /* (in)active */
1661
            ide_atapi_cmd_reply(s, 32, 32);
1662
            break;
1663
        }
1664
    default:
1665
        ide_atapi_cmd_error(s, SENSE_ILLEGAL_REQUEST,
1666
                            ASC_ILLEGAL_OPCODE);
1667
        break;
1668
    }
1669
}
1670

    
1671
static void ide_cfata_metadata_inquiry(IDEState *s)
1672
{
1673
    uint16_t *p;
1674
    uint32_t spd;
1675

    
1676
    p = (uint16_t *) s->io_buffer;
1677
    memset(p, 0, 0x200);
1678
    spd = ((s->mdata_size - 1) >> 9) + 1;
1679

    
1680
    put_le16(p + 0, 0x0001);                        /* Data format revision */
1681
    put_le16(p + 1, 0x0000);                        /* Media property: silicon */
1682
    put_le16(p + 2, s->media_changed);                /* Media status */
1683
    put_le16(p + 3, s->mdata_size & 0xffff);        /* Capacity in bytes (low) */
1684
    put_le16(p + 4, s->mdata_size >> 16);        /* Capacity in bytes (high) */
1685
    put_le16(p + 5, spd & 0xffff);                /* Sectors per device (low) */
1686
    put_le16(p + 6, spd >> 16);                        /* Sectors per device (high) */
1687
}
1688

    
1689
static void ide_cfata_metadata_read(IDEState *s)
1690
{
1691
    uint16_t *p;
1692

    
1693
    if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1694
        s->status = ERR_STAT;
1695
        s->error = ABRT_ERR;
1696
        return;
1697
    }
1698

    
1699
    p = (uint16_t *) s->io_buffer;
1700
    memset(p, 0, 0x200);
1701

    
1702
    put_le16(p + 0, s->media_changed);                /* Media status */
1703
    memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1704
                    MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1705
                                    s->nsector << 9), 0x200 - 2));
1706
}
1707

    
1708
static void ide_cfata_metadata_write(IDEState *s)
1709
{
1710
    if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
1711
        s->status = ERR_STAT;
1712
        s->error = ABRT_ERR;
1713
        return;
1714
    }
1715

    
1716
    s->media_changed = 0;
1717

    
1718
    memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
1719
                    s->io_buffer + 2,
1720
                    MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
1721
                                    s->nsector << 9), 0x200 - 2));
1722
}
1723

    
1724
/* called when the inserted state of the media has changed */
1725
static void cdrom_change_cb(void *opaque)
1726
{
1727
    IDEState *s = opaque;
1728
    uint64_t nb_sectors;
1729

    
1730
    /* XXX: send interrupt too */
1731
    bdrv_get_geometry(s->bs, &nb_sectors);
1732
    s->nb_sectors = nb_sectors;
1733
}
1734

    
1735
static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1736
{
1737
    s->lba48 = lba48;
1738

    
1739
    /* handle the 'magic' 0 nsector count conversion here. to avoid
1740
     * fiddling with the rest of the read logic, we just store the
1741
     * full sector count in ->nsector and ignore ->hob_nsector from now
1742
     */
1743
    if (!s->lba48) {
1744
        if (!s->nsector)
1745
            s->nsector = 256;
1746
    } else {
1747
        if (!s->nsector && !s->hob_nsector)
1748
            s->nsector = 65536;
1749
        else {
1750
            int lo = s->nsector;
1751
            int hi = s->hob_nsector;
1752

    
1753
            s->nsector = (hi << 8) | lo;
1754
        }
1755
    }
1756
}
1757

    
1758
static void ide_clear_hob(IDEState *ide_if)
1759
{
1760
    /* any write clears HOB high bit of device control register */
1761
    ide_if[0].select &= ~(1 << 7);
1762
    ide_if[1].select &= ~(1 << 7);
1763
}
1764

    
1765
static void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1766
{
1767
    IDEState *ide_if = opaque;
1768
    IDEState *s;
1769
    int unit, n;
1770
    int lba48 = 0;
1771

    
1772
#ifdef DEBUG_IDE
1773
    printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1774
#endif
1775

    
1776
    addr &= 7;
1777
    switch(addr) {
1778
    case 0:
1779
        break;
1780
    case 1:
1781
        ide_clear_hob(ide_if);
1782
        /* NOTE: data is written to the two drives */
1783
        ide_if[0].hob_feature = ide_if[0].feature;
1784
        ide_if[1].hob_feature = ide_if[1].feature;
1785
        ide_if[0].feature = val;
1786
        ide_if[1].feature = val;
1787
        break;
1788
    case 2:
1789
        ide_clear_hob(ide_if);
1790
        ide_if[0].hob_nsector = ide_if[0].nsector;
1791
        ide_if[1].hob_nsector = ide_if[1].nsector;
1792
        ide_if[0].nsector = val;
1793
        ide_if[1].nsector = val;
1794
        break;
1795
    case 3:
1796
        ide_clear_hob(ide_if);
1797
        ide_if[0].hob_sector = ide_if[0].sector;
1798
        ide_if[1].hob_sector = ide_if[1].sector;
1799
        ide_if[0].sector = val;
1800
        ide_if[1].sector = val;
1801
        break;
1802
    case 4:
1803
        ide_clear_hob(ide_if);
1804
        ide_if[0].hob_lcyl = ide_if[0].lcyl;
1805
        ide_if[1].hob_lcyl = ide_if[1].lcyl;
1806
        ide_if[0].lcyl = val;
1807
        ide_if[1].lcyl = val;
1808
        break;
1809
    case 5:
1810
        ide_clear_hob(ide_if);
1811
        ide_if[0].hob_hcyl = ide_if[0].hcyl;
1812
        ide_if[1].hob_hcyl = ide_if[1].hcyl;
1813
        ide_if[0].hcyl = val;
1814
        ide_if[1].hcyl = val;
1815
        break;
1816
    case 6:
1817
        /* FIXME: HOB readback uses bit 7 */
1818
        ide_if[0].select = (val & ~0x10) | 0xa0;
1819
        ide_if[1].select = (val | 0x10) | 0xa0;
1820
        /* select drive */
1821
        unit = (val >> 4) & 1;
1822
        s = ide_if + unit;
1823
        ide_if->cur_drive = s;
1824
        break;
1825
    default:
1826
    case 7:
1827
        /* command */
1828
#if defined(DEBUG_IDE)
1829
        printf("ide: CMD=%02x\n", val);
1830
#endif
1831
        s = ide_if->cur_drive;
1832
        /* ignore commands to non existant slave */
1833
        if (s != ide_if && !s->bs)
1834
            break;
1835

    
1836
        switch(val) {
1837
        case WIN_IDENTIFY:
1838
            if (s->bs && !s->is_cdrom) {
1839
                if (!s->is_cf)
1840
                    ide_identify(s);
1841
                else
1842
                    ide_cfata_identify(s);
1843
                s->status = READY_STAT | SEEK_STAT;
1844
                ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1845
            } else {
1846
                if (s->is_cdrom) {
1847
                    ide_set_signature(s);
1848
                }
1849
                ide_abort_command(s);
1850
            }
1851
            ide_set_irq(s);
1852
            break;
1853
        case WIN_SPECIFY:
1854
        case WIN_RECAL:
1855
            s->error = 0;
1856
            s->status = READY_STAT | SEEK_STAT;
1857
            ide_set_irq(s);
1858
            break;
1859
        case WIN_SETMULT:
1860
            if (s->is_cf && s->nsector == 0) {
1861
                /* Disable Read and Write Multiple */
1862
                s->mult_sectors = 0;
1863
                s->status = READY_STAT;
1864
            } else if ((s->nsector & 0xff) != 0 &&
1865
                ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1866
                 (s->nsector & (s->nsector - 1)) != 0)) {
1867
                ide_abort_command(s);
1868
            } else {
1869
                s->mult_sectors = s->nsector & 0xff;
1870
                s->status = READY_STAT;
1871
            }
1872
            ide_set_irq(s);
1873
            break;
1874
        case WIN_VERIFY_EXT:
1875
            lba48 = 1;
1876
        case WIN_VERIFY:
1877
        case WIN_VERIFY_ONCE:
1878
            /* do sector number check ? */
1879
            ide_cmd_lba48_transform(s, lba48);
1880
            s->status = READY_STAT;
1881
            ide_set_irq(s);
1882
            break;
1883
        case WIN_READ_EXT:
1884
            lba48 = 1;
1885
        case WIN_READ:
1886
        case WIN_READ_ONCE:
1887
            if (!s->bs)
1888
                goto abort_cmd;
1889
            ide_cmd_lba48_transform(s, lba48);
1890
            s->req_nb_sectors = 1;
1891
            ide_sector_read(s);
1892
            break;
1893
        case WIN_WRITE_EXT:
1894
            lba48 = 1;
1895
        case WIN_WRITE:
1896
        case WIN_WRITE_ONCE:
1897
        case CFA_WRITE_SECT_WO_ERASE:
1898
        case WIN_WRITE_VERIFY:
1899
            ide_cmd_lba48_transform(s, lba48);
1900
            s->error = 0;
1901
            s->status = SEEK_STAT | READY_STAT;
1902
            s->req_nb_sectors = 1;
1903
            ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1904
            s->media_changed = 1;
1905
            break;
1906
        case WIN_MULTREAD_EXT:
1907
            lba48 = 1;
1908
        case WIN_MULTREAD:
1909
            if (!s->mult_sectors)
1910
                goto abort_cmd;
1911
            ide_cmd_lba48_transform(s, lba48);
1912
            s->req_nb_sectors = s->mult_sectors;
1913
            ide_sector_read(s);
1914
            break;
1915
        case WIN_MULTWRITE_EXT:
1916
            lba48 = 1;
1917
        case WIN_MULTWRITE:
1918
        case CFA_WRITE_MULTI_WO_ERASE:
1919
            if (!s->mult_sectors)
1920
                goto abort_cmd;
1921
            ide_cmd_lba48_transform(s, lba48);
1922
            s->error = 0;
1923
            s->status = SEEK_STAT | READY_STAT;
1924
            s->req_nb_sectors = s->mult_sectors;
1925
            n = s->nsector;
1926
            if (n > s->req_nb_sectors)
1927
                n = s->req_nb_sectors;
1928
            ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1929
            s->media_changed = 1;
1930
            break;
1931
        case WIN_READDMA_EXT:
1932
            lba48 = 1;
1933
        case WIN_READDMA:
1934
        case WIN_READDMA_ONCE:
1935
            if (!s->bs)
1936
                goto abort_cmd;
1937
            ide_cmd_lba48_transform(s, lba48);
1938
            ide_sector_read_dma(s);
1939
            break;
1940
        case WIN_WRITEDMA_EXT:
1941
            lba48 = 1;
1942
        case WIN_WRITEDMA:
1943
        case WIN_WRITEDMA_ONCE:
1944
            if (!s->bs)
1945
                goto abort_cmd;
1946
            ide_cmd_lba48_transform(s, lba48);
1947
            ide_sector_write_dma(s);
1948
            s->media_changed = 1;
1949
            break;
1950
        case WIN_READ_NATIVE_MAX_EXT:
1951
            lba48 = 1;
1952
        case WIN_READ_NATIVE_MAX:
1953
            ide_cmd_lba48_transform(s, lba48);
1954
            ide_set_sector(s, s->nb_sectors - 1);
1955
            s->status = READY_STAT;
1956
            ide_set_irq(s);
1957
            break;
1958
        case WIN_CHECKPOWERMODE1:
1959
        case WIN_CHECKPOWERMODE2:
1960
            s->nsector = 0xff; /* device active or idle */
1961
            s->status = READY_STAT;
1962
            ide_set_irq(s);
1963
            break;
1964
        case WIN_SETFEATURES:
1965
            if (!s->bs)
1966
                goto abort_cmd;
1967
            /* XXX: valid for CDROM ? */
1968
            switch(s->feature) {
1969
            case 0xcc: /* reverting to power-on defaults enable */
1970
            case 0x66: /* reverting to power-on defaults disable */
1971
            case 0x02: /* write cache enable */
1972
            case 0x82: /* write cache disable */
1973
            case 0xaa: /* read look-ahead enable */
1974
            case 0x55: /* read look-ahead disable */
1975
            case 0x05: /* set advanced power management mode */
1976
            case 0x85: /* disable advanced power management mode */
1977
            case 0x69: /* NOP */
1978
            case 0x67: /* NOP */
1979
            case 0x96: /* NOP */
1980
            case 0x9a: /* NOP */
1981
            case 0x42: /* enable Automatic Acoustic Mode */
1982
            case 0xc2: /* disable Automatic Acoustic Mode */
1983
                s->status = READY_STAT | SEEK_STAT;
1984
                ide_set_irq(s);
1985
                break;
1986
            case 0x03: { /* set transfer mode */
1987
                uint8_t val = s->nsector & 0x07;
1988

    
1989
                switch (s->nsector >> 3) {
1990
                    case 0x00: /* pio default */
1991
                    case 0x01: /* pio mode */
1992
                        put_le16(s->identify_data + 63,0x07);
1993
                        put_le16(s->identify_data + 88,0x3f);
1994
                        break;
1995
                    case 0x04: /* mdma mode */
1996
                        put_le16(s->identify_data + 63,0x07 | (1 << (val + 8)));
1997
                        put_le16(s->identify_data + 88,0x3f);
1998
                        break;
1999
                    case 0x08: /* udma mode */
2000
                        put_le16(s->identify_data + 63,0x07);
2001
                        put_le16(s->identify_data + 88,0x3f | (1 << (val + 8)));
2002
                        break;
2003
                    default:
2004
                        goto abort_cmd;
2005
                }
2006
                s->status = READY_STAT | SEEK_STAT;
2007
                ide_set_irq(s);
2008
                break;
2009
            }
2010
            default:
2011
                goto abort_cmd;
2012
            }
2013
            break;
2014
        case WIN_FLUSH_CACHE:
2015
        case WIN_FLUSH_CACHE_EXT:
2016
            if (s->bs)
2017
                bdrv_flush(s->bs);
2018
            s->status = READY_STAT;
2019
            ide_set_irq(s);
2020
            break;
2021
        case WIN_STANDBY:
2022
        case WIN_STANDBY2:
2023
        case WIN_STANDBYNOW1:
2024
        case WIN_STANDBYNOW2:
2025
        case WIN_IDLEIMMEDIATE:
2026
        case CFA_IDLEIMMEDIATE:
2027
        case WIN_SETIDLE1:
2028
        case WIN_SETIDLE2:
2029
        case WIN_SLEEPNOW1:
2030
        case WIN_SLEEPNOW2:
2031
            s->status = READY_STAT;
2032
            ide_set_irq(s);
2033
            break;
2034
            /* ATAPI commands */
2035
        case WIN_PIDENTIFY:
2036
            if (s->is_cdrom) {
2037
                ide_atapi_identify(s);
2038
                s->status = READY_STAT | SEEK_STAT;
2039
                ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
2040
            } else {
2041
                ide_abort_command(s);
2042
            }
2043
            ide_set_irq(s);
2044
            break;
2045
        case WIN_DIAGNOSE:
2046
            ide_set_signature(s);
2047
            s->status = 0x00; /* NOTE: READY is _not_ set */
2048
            s->error = 0x01;
2049
            ide_set_irq(s);
2050
            break;
2051
        case WIN_SRST:
2052
            if (!s->is_cdrom)
2053
                goto abort_cmd;
2054
            ide_set_signature(s);
2055
            s->status = 0x00; /* NOTE: READY is _not_ set */
2056
            s->error = 0x01;
2057
            break;
2058
        case WIN_PACKETCMD:
2059
            if (!s->is_cdrom)
2060
                goto abort_cmd;
2061
            /* overlapping commands not supported */
2062
            if (s->feature & 0x02)
2063
                goto abort_cmd;
2064
            s->status = READY_STAT;
2065
            s->atapi_dma = s->feature & 1;
2066
            s->nsector = 1;
2067
            ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
2068
                               ide_atapi_cmd);
2069
            break;
2070
        /* CF-ATA commands */
2071
        case CFA_REQ_EXT_ERROR_CODE:
2072
            if (!s->is_cf)
2073
                goto abort_cmd;
2074
            s->error = 0x09;    /* miscellaneous error */
2075
            s->status = READY_STAT;
2076
            ide_set_irq(s);
2077
            break;
2078
        case CFA_ERASE_SECTORS:
2079
        case CFA_WEAR_LEVEL:
2080
            if (!s->is_cf)
2081
                goto abort_cmd;
2082
            if (val == CFA_WEAR_LEVEL)
2083
                s->nsector = 0;
2084
            if (val == CFA_ERASE_SECTORS)
2085
                s->media_changed = 1;
2086
            s->error = 0x00;
2087
            s->status = READY_STAT;
2088
            ide_set_irq(s);
2089
            break;
2090
        case CFA_TRANSLATE_SECTOR:
2091
            if (!s->is_cf)
2092
                goto abort_cmd;
2093
            s->error = 0x00;
2094
            s->status = READY_STAT;
2095
            memset(s->io_buffer, 0, 0x200);
2096
            s->io_buffer[0x00] = s->hcyl;                        /* Cyl MSB */
2097
            s->io_buffer[0x01] = s->lcyl;                        /* Cyl LSB */
2098
            s->io_buffer[0x02] = s->select;                        /* Head */
2099
            s->io_buffer[0x03] = s->sector;                        /* Sector */
2100
            s->io_buffer[0x04] = ide_get_sector(s) >> 16;        /* LBA MSB */
2101
            s->io_buffer[0x05] = ide_get_sector(s) >> 8;        /* LBA */
2102
            s->io_buffer[0x06] = ide_get_sector(s) >> 0;        /* LBA LSB */
2103
            s->io_buffer[0x13] = 0x00;                                /* Erase flag */
2104
            s->io_buffer[0x18] = 0x00;                                /* Hot count */
2105
            s->io_buffer[0x19] = 0x00;                                /* Hot count */
2106
            s->io_buffer[0x1a] = 0x01;                                /* Hot count */
2107
            ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2108
            ide_set_irq(s);
2109
            break;
2110
        case CFA_ACCESS_METADATA_STORAGE:
2111
            if (!s->is_cf)
2112
                goto abort_cmd;
2113
            switch (s->feature) {
2114
            case 0x02:        /* Inquiry Metadata Storage */
2115
                ide_cfata_metadata_inquiry(s);
2116
                break;
2117
            case 0x03:        /* Read Metadata Storage */
2118
                ide_cfata_metadata_read(s);
2119
                break;
2120
            case 0x04:        /* Write Metadata Storage */
2121
                ide_cfata_metadata_write(s);
2122
                break;
2123
            default:
2124
                goto abort_cmd;
2125
            }
2126
            ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
2127
            s->status = 0x00; /* NOTE: READY is _not_ set */
2128
            ide_set_irq(s);
2129
            break;
2130
        case IBM_SENSE_CONDITION:
2131
            if (!s->is_cf)
2132
                goto abort_cmd;
2133
            switch (s->feature) {
2134
            case 0x01:  /* sense temperature in device */
2135
                s->nsector = 0x50;      /* +20 C */
2136
                break;
2137
            default:
2138
                goto abort_cmd;
2139
            }
2140
            s->status = READY_STAT;
2141
            ide_set_irq(s);
2142
            break;
2143
        default:
2144
        abort_cmd:
2145
            ide_abort_command(s);
2146
            ide_set_irq(s);
2147
            break;
2148
        }
2149
    }
2150
}
2151

    
2152
static uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
2153
{
2154
    IDEState *ide_if = opaque;
2155
    IDEState *s = ide_if->cur_drive;
2156
    uint32_t addr;
2157
    int ret, hob;
2158

    
2159
    addr = addr1 & 7;
2160
    /* FIXME: HOB readback uses bit 7, but it's always set right now */
2161
    //hob = s->select & (1 << 7);
2162
    hob = 0;
2163
    switch(addr) {
2164
    case 0:
2165
        ret = 0xff;
2166
        break;
2167
    case 1:
2168
        if (!ide_if[0].bs && !ide_if[1].bs)
2169
            ret = 0;
2170
        else if (!hob)
2171
            ret = s->error;
2172
        else
2173
            ret = s->hob_feature;
2174
        break;
2175
    case 2:
2176
        if (!ide_if[0].bs && !ide_if[1].bs)
2177
            ret = 0;
2178
        else if (!hob)
2179
            ret = s->nsector & 0xff;
2180
        else
2181
            ret = s->hob_nsector;
2182
        break;
2183
    case 3:
2184
        if (!ide_if[0].bs && !ide_if[1].bs)
2185
            ret = 0;
2186
        else if (!hob)
2187
            ret = s->sector;
2188
        else
2189
            ret = s->hob_sector;
2190
        break;
2191
    case 4:
2192
        if (!ide_if[0].bs && !ide_if[1].bs)
2193
            ret = 0;
2194
        else if (!hob)
2195
            ret = s->lcyl;
2196
        else
2197
            ret = s->hob_lcyl;
2198
        break;
2199
    case 5:
2200
        if (!ide_if[0].bs && !ide_if[1].bs)
2201
            ret = 0;
2202
        else if (!hob)
2203
            ret = s->hcyl;
2204
        else
2205
            ret = s->hob_hcyl;
2206
        break;
2207
    case 6:
2208
        if (!ide_if[0].bs && !ide_if[1].bs)
2209
            ret = 0;
2210
        else
2211
            ret = s->select;
2212
        break;
2213
    default:
2214
    case 7:
2215
        if ((!ide_if[0].bs && !ide_if[1].bs) ||
2216
            (s != ide_if && !s->bs))
2217
            ret = 0;
2218
        else
2219
            ret = s->status;
2220
        qemu_irq_lower(s->irq);
2221
        break;
2222
    }
2223
#ifdef DEBUG_IDE
2224
    printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
2225
#endif
2226
    return ret;
2227
}
2228

    
2229
static uint32_t ide_status_read(void *opaque, uint32_t addr)
2230
{
2231
    IDEState *ide_if = opaque;
2232
    IDEState *s = ide_if->cur_drive;
2233
    int ret;
2234

    
2235
    if ((!ide_if[0].bs && !ide_if[1].bs) ||
2236
        (s != ide_if && !s->bs))
2237
        ret = 0;
2238
    else
2239
        ret = s->status;
2240
#ifdef DEBUG_IDE
2241
    printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
2242
#endif
2243
    return ret;
2244
}
2245

    
2246
static void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
2247
{
2248
    IDEState *ide_if = opaque;
2249
    IDEState *s;
2250
    int i;
2251

    
2252
#ifdef DEBUG_IDE
2253
    printf("ide: write control addr=0x%x val=%02x\n", addr, val);
2254
#endif
2255
    /* common for both drives */
2256
    if (!(ide_if[0].cmd & IDE_CMD_RESET) &&
2257
        (val & IDE_CMD_RESET)) {
2258
        /* reset low to high */
2259
        for(i = 0;i < 2; i++) {
2260
            s = &ide_if[i];
2261
            s->status = BUSY_STAT | SEEK_STAT;
2262
            s->error = 0x01;
2263
        }
2264
    } else if ((ide_if[0].cmd & IDE_CMD_RESET) &&
2265
               !(val & IDE_CMD_RESET)) {
2266
        /* high to low */
2267
        for(i = 0;i < 2; i++) {
2268
            s = &ide_if[i];
2269
            if (s->is_cdrom)
2270
                s->status = 0x00; /* NOTE: READY is _not_ set */
2271
            else
2272
                s->status = READY_STAT | SEEK_STAT;
2273
            ide_set_signature(s);
2274
        }
2275
    }
2276

    
2277
    ide_if[0].cmd = val;
2278
    ide_if[1].cmd = val;
2279
}
2280

    
2281
static void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
2282
{
2283
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2284
    uint8_t *p;
2285

    
2286
    p = s->data_ptr;
2287
    *(uint16_t *)p = le16_to_cpu(val);
2288
    p += 2;
2289
    s->data_ptr = p;
2290
    if (p >= s->data_end)
2291
        s->end_transfer_func(s);
2292
}
2293

    
2294
static uint32_t ide_data_readw(void *opaque, uint32_t addr)
2295
{
2296
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2297
    uint8_t *p;
2298
    int ret;
2299
    p = s->data_ptr;
2300
    ret = cpu_to_le16(*(uint16_t *)p);
2301
    p += 2;
2302
    s->data_ptr = p;
2303
    if (p >= s->data_end)
2304
        s->end_transfer_func(s);
2305
    return ret;
2306
}
2307

    
2308
static void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2309
{
2310
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2311
    uint8_t *p;
2312

    
2313
    p = s->data_ptr;
2314
    *(uint32_t *)p = le32_to_cpu(val);
2315
    p += 4;
2316
    s->data_ptr = p;
2317
    if (p >= s->data_end)
2318
        s->end_transfer_func(s);
2319
}
2320

    
2321
static uint32_t ide_data_readl(void *opaque, uint32_t addr)
2322
{
2323
    IDEState *s = ((IDEState *)opaque)->cur_drive;
2324
    uint8_t *p;
2325
    int ret;
2326

    
2327
    p = s->data_ptr;
2328
    ret = cpu_to_le32(*(uint32_t *)p);
2329
    p += 4;
2330
    s->data_ptr = p;
2331
    if (p >= s->data_end)
2332
        s->end_transfer_func(s);
2333
    return ret;
2334
}
2335

    
2336
static void ide_dummy_transfer_stop(IDEState *s)
2337
{
2338
    s->data_ptr = s->io_buffer;
2339
    s->data_end = s->io_buffer;
2340
    s->io_buffer[0] = 0xff;
2341
    s->io_buffer[1] = 0xff;
2342
    s->io_buffer[2] = 0xff;
2343
    s->io_buffer[3] = 0xff;
2344
}
2345

    
2346
static void ide_reset(IDEState *s)
2347
{
2348
    if (s->is_cf)
2349
        s->mult_sectors = 0;
2350
    else
2351
        s->mult_sectors = MAX_MULT_SECTORS;
2352
    s->cur_drive = s;
2353
    s->select = 0xa0;
2354
    s->status = READY_STAT;
2355
    ide_set_signature(s);
2356
    /* init the transfer handler so that 0xffff is returned on data
2357
       accesses */
2358
    s->end_transfer_func = ide_dummy_transfer_stop;
2359
    ide_dummy_transfer_stop(s);
2360
    s->media_changed = 0;
2361
}
2362

    
2363
struct partition {
2364
        uint8_t boot_ind;                /* 0x80 - active */
2365
        uint8_t head;                /* starting head */
2366
        uint8_t sector;                /* starting sector */
2367
        uint8_t cyl;                /* starting cylinder */
2368
        uint8_t sys_ind;                /* What partition type */
2369
        uint8_t end_head;                /* end head */
2370
        uint8_t end_sector;        /* end sector */
2371
        uint8_t end_cyl;                /* end cylinder */
2372
        uint32_t start_sect;        /* starting sector counting from 0 */
2373
        uint32_t nr_sects;                /* nr of sectors in partition */
2374
} __attribute__((packed));
2375

    
2376
/* try to guess the disk logical geometry from the MSDOS partition table. Return 0 if OK, -1 if could not guess */
2377
static int guess_disk_lchs(IDEState *s,
2378
                           int *pcylinders, int *pheads, int *psectors)
2379
{
2380
    uint8_t *buf;
2381
    int ret, i, heads, sectors, cylinders;
2382
    struct partition *p;
2383
    uint32_t nr_sects;
2384

    
2385
    buf = qemu_memalign(512, 512);
2386
    if (buf == NULL)
2387
        return -1;
2388
    ret = bdrv_read(s->bs, 0, buf, 1);
2389
    if (ret < 0) {
2390
        qemu_free(buf);
2391
        return -1;
2392
    }
2393
    /* test msdos magic */
2394
    if (buf[510] != 0x55 || buf[511] != 0xaa) {
2395
        qemu_free(buf);
2396
        return -1;
2397
    }
2398
    for(i = 0; i < 4; i++) {
2399
        p = ((struct partition *)(buf + 0x1be)) + i;
2400
        nr_sects = le32_to_cpu(p->nr_sects);
2401
        if (nr_sects && p->end_head) {
2402
            /* We make the assumption that the partition terminates on
2403
               a cylinder boundary */
2404
            heads = p->end_head + 1;
2405
            sectors = p->end_sector & 63;
2406
            if (sectors == 0)
2407
                continue;
2408
            cylinders = s->nb_sectors / (heads * sectors);
2409
            if (cylinders < 1 || cylinders > 16383)
2410
                continue;
2411
            *pheads = heads;
2412
            *psectors = sectors;
2413
            *pcylinders = cylinders;
2414
#if 0
2415
            printf("guessed geometry: LCHS=%d %d %d\n",
2416
                   cylinders, heads, sectors);
2417
#endif
2418
            qemu_free(buf);
2419
            return 0;
2420
        }
2421
    }
2422
    qemu_free(buf);
2423
    return -1;
2424
}
2425

    
2426
static void ide_init2(IDEState *ide_state,
2427
                      BlockDriverState *hd0, BlockDriverState *hd1,
2428
                      qemu_irq irq)
2429
{
2430
    IDEState *s;
2431
    static int drive_serial = 1;
2432
    int i, cylinders, heads, secs, translation, lba_detected = 0;
2433
    uint64_t nb_sectors;
2434

    
2435
    for(i = 0; i < 2; i++) {
2436
        s = ide_state + i;
2437
        s->io_buffer = qemu_memalign(512, MAX_MULT_SECTORS*512 + 4);
2438
        if (i == 0)
2439
            s->bs = hd0;
2440
        else
2441
            s->bs = hd1;
2442
        if (s->bs) {
2443
            bdrv_get_geometry(s->bs, &nb_sectors);
2444
            s->nb_sectors = nb_sectors;
2445
            /* if a geometry hint is available, use it */
2446
            bdrv_get_geometry_hint(s->bs, &cylinders, &heads, &secs);
2447
            translation = bdrv_get_translation_hint(s->bs);
2448
            if (cylinders != 0) {
2449
                s->cylinders = cylinders;
2450
                s->heads = heads;
2451
                s->sectors = secs;
2452
            } else {
2453
                if (guess_disk_lchs(s, &cylinders, &heads, &secs) == 0) {
2454
                    if (heads > 16) {
2455
                        /* if heads > 16, it means that a BIOS LBA
2456
                           translation was active, so the default
2457
                           hardware geometry is OK */
2458
                        lba_detected = 1;
2459
                        goto default_geometry;
2460
                    } else {
2461
                        s->cylinders = cylinders;
2462
                        s->heads = heads;
2463
                        s->sectors = secs;
2464
                        /* disable any translation to be in sync with
2465
                           the logical geometry */
2466
                        if (translation == BIOS_ATA_TRANSLATION_AUTO) {
2467
                            bdrv_set_translation_hint(s->bs,
2468
                                                      BIOS_ATA_TRANSLATION_NONE);
2469
                        }
2470
                    }
2471
                } else {
2472
                default_geometry:
2473
                    /* if no geometry, use a standard physical disk geometry */
2474
                    cylinders = nb_sectors / (16 * 63);
2475
                    if (cylinders > 16383)
2476
                        cylinders = 16383;
2477
                    else if (cylinders < 2)
2478
                        cylinders = 2;
2479
                    s->cylinders = cylinders;
2480
                    s->heads = 16;
2481
                    s->sectors = 63;
2482
                    if ((lba_detected == 1) && (translation == BIOS_ATA_TRANSLATION_AUTO)) {
2483
                      if ((s->cylinders * s->heads) <= 131072) {
2484
                        bdrv_set_translation_hint(s->bs,
2485
                                                  BIOS_ATA_TRANSLATION_LARGE);
2486
                      } else {
2487
                        bdrv_set_translation_hint(s->bs,
2488
                                                  BIOS_ATA_TRANSLATION_LBA);
2489
                      }
2490
                    }
2491
                }
2492
                bdrv_set_geometry_hint(s->bs, s->cylinders, s->heads, s->sectors);
2493
            }
2494
            if (bdrv_get_type_hint(s->bs) == BDRV_TYPE_CDROM) {
2495
                s->is_cdrom = 1;
2496
                bdrv_set_change_cb(s->bs, cdrom_change_cb, s);
2497
            }
2498
        }
2499
        s->drive_serial = drive_serial++;
2500
        s->irq = irq;
2501
        s->sector_write_timer = qemu_new_timer(vm_clock,
2502
                                               ide_sector_write_timer_cb, s);
2503
        ide_reset(s);
2504
    }
2505
}
2506

    
2507
static void ide_init_ioport(IDEState *ide_state, int iobase, int iobase2)
2508
{
2509
    register_ioport_write(iobase, 8, 1, ide_ioport_write, ide_state);
2510
    register_ioport_read(iobase, 8, 1, ide_ioport_read, ide_state);
2511
    if (iobase2) {
2512
        register_ioport_read(iobase2, 1, 1, ide_status_read, ide_state);
2513
        register_ioport_write(iobase2, 1, 1, ide_cmd_write, ide_state);
2514
    }
2515

    
2516
    /* data ports */
2517
    register_ioport_write(iobase, 2, 2, ide_data_writew, ide_state);
2518
    register_ioport_read(iobase, 2, 2, ide_data_readw, ide_state);
2519
    register_ioport_write(iobase, 4, 4, ide_data_writel, ide_state);
2520
    register_ioport_read(iobase, 4, 4, ide_data_readl, ide_state);
2521
}
2522

    
2523
/* save per IDE drive data */
2524
static void ide_save(QEMUFile* f, IDEState *s)
2525
{
2526
    qemu_put_be32(f, s->mult_sectors);
2527
    qemu_put_be32(f, s->identify_set);
2528
    if (s->identify_set) {
2529
        qemu_put_buffer(f, (const uint8_t *)s->identify_data, 512);
2530
    }
2531
    qemu_put_8s(f, &s->feature);
2532
    qemu_put_8s(f, &s->error);
2533
    qemu_put_be32s(f, &s->nsector);
2534
    qemu_put_8s(f, &s->sector);
2535
    qemu_put_8s(f, &s->lcyl);
2536
    qemu_put_8s(f, &s->hcyl);
2537
    qemu_put_8s(f, &s->hob_feature);
2538
    qemu_put_8s(f, &s->hob_nsector);
2539
    qemu_put_8s(f, &s->hob_sector);
2540
    qemu_put_8s(f, &s->hob_lcyl);
2541
    qemu_put_8s(f, &s->hob_hcyl);
2542
    qemu_put_8s(f, &s->select);
2543
    qemu_put_8s(f, &s->status);
2544
    qemu_put_8s(f, &s->lba48);
2545

    
2546
    qemu_put_8s(f, &s->sense_key);
2547
    qemu_put_8s(f, &s->asc);
2548
    /* XXX: if a transfer is pending, we do not save it yet */
2549
}
2550

    
2551
/* load per IDE drive data */
2552
static void ide_load(QEMUFile* f, IDEState *s)
2553
{
2554
    s->mult_sectors=qemu_get_be32(f);
2555
    s->identify_set=qemu_get_be32(f);
2556
    if (s->identify_set) {
2557
        qemu_get_buffer(f, (uint8_t *)s->identify_data, 512);
2558
    }
2559
    qemu_get_8s(f, &s->feature);
2560
    qemu_get_8s(f, &s->error);
2561
    qemu_get_be32s(f, &s->nsector);
2562
    qemu_get_8s(f, &s->sector);
2563
    qemu_get_8s(f, &s->lcyl);
2564
    qemu_get_8s(f, &s->hcyl);
2565
    qemu_get_8s(f, &s->hob_feature);
2566
    qemu_get_8s(f, &s->hob_nsector);
2567
    qemu_get_8s(f, &s->hob_sector);
2568
    qemu_get_8s(f, &s->hob_lcyl);
2569
    qemu_get_8s(f, &s->hob_hcyl);
2570
    qemu_get_8s(f, &s->select);
2571
    qemu_get_8s(f, &s->status);
2572
    qemu_get_8s(f, &s->lba48);
2573

    
2574
    qemu_get_8s(f, &s->sense_key);
2575
    qemu_get_8s(f, &s->asc);
2576
    /* XXX: if a transfer is pending, we do not save it yet */
2577
}
2578

    
2579
/***********************************************************/
2580
/* ISA IDE definitions */
2581

    
2582
void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
2583
                  BlockDriverState *hd0, BlockDriverState *hd1)
2584
{
2585
    IDEState *ide_state;
2586

    
2587
    ide_state = qemu_mallocz(sizeof(IDEState) * 2);
2588
    if (!ide_state)
2589
        return;
2590

    
2591
    ide_init2(ide_state, hd0, hd1, irq);
2592
    ide_init_ioport(ide_state, iobase, iobase2);
2593
}
2594

    
2595
/***********************************************************/
2596
/* PCI IDE definitions */
2597

    
2598
static void cmd646_update_irq(PCIIDEState *d);
2599

    
2600
static void ide_map(PCIDevice *pci_dev, int region_num,
2601
                    uint32_t addr, uint32_t size, int type)
2602
{
2603
    PCIIDEState *d = (PCIIDEState *)pci_dev;
2604
    IDEState *ide_state;
2605

    
2606
    if (region_num <= 3) {
2607
        ide_state = &d->ide_if[(region_num >> 1) * 2];
2608
        if (region_num & 1) {
2609
            register_ioport_read(addr + 2, 1, 1, ide_status_read, ide_state);
2610
            register_ioport_write(addr + 2, 1, 1, ide_cmd_write, ide_state);
2611
        } else {
2612
            register_ioport_write(addr, 8, 1, ide_ioport_write, ide_state);
2613
            register_ioport_read(addr, 8, 1, ide_ioport_read, ide_state);
2614

    
2615
            /* data ports */
2616
            register_ioport_write(addr, 2, 2, ide_data_writew, ide_state);
2617
            register_ioport_read(addr, 2, 2, ide_data_readw, ide_state);
2618
            register_ioport_write(addr, 4, 4, ide_data_writel, ide_state);
2619
            register_ioport_read(addr, 4, 4, ide_data_readl, ide_state);
2620
        }
2621
    }
2622
}
2623

    
2624
static void ide_dma_start(IDEState *s, BlockDriverCompletionFunc *dma_cb)
2625
{
2626
    BMDMAState *bm = s->bmdma;
2627
    if(!bm)
2628
        return;
2629
    bm->ide_if = s;
2630
    bm->dma_cb = dma_cb;
2631
    bm->cur_prd_last = 0;
2632
    bm->cur_prd_addr = 0;
2633
    bm->cur_prd_len = 0;
2634
    if (bm->status & BM_STATUS_DMAING) {
2635
        bm->dma_cb(bm, 0);
2636
    }
2637
}
2638

    
2639
static void bmdma_cmd_writeb(void *opaque, uint32_t addr, uint32_t val)
2640
{
2641
    BMDMAState *bm = opaque;
2642
#ifdef DEBUG_IDE
2643
    printf("%s: 0x%08x\n", __func__, val);
2644
#endif
2645
    if (!(val & BM_CMD_START)) {
2646
        /* XXX: do it better */
2647
        if (bm->status & BM_STATUS_DMAING) {
2648
            bm->status &= ~BM_STATUS_DMAING;
2649
            /* cancel DMA request */
2650
            bm->ide_if = NULL;
2651
            bm->dma_cb = NULL;
2652
            if (bm->aiocb) {
2653
#ifdef DEBUG_AIO
2654
                printf("aio_cancel\n");
2655
#endif
2656
                bdrv_aio_cancel(bm->aiocb);
2657
                bm->aiocb = NULL;
2658
            }
2659
        }
2660
        bm->cmd = val & 0x09;
2661
    } else {
2662
        if (!(bm->status & BM_STATUS_DMAING)) {
2663
            bm->status |= BM_STATUS_DMAING;
2664
            /* start dma transfer if possible */
2665
            if (bm->dma_cb)
2666
                bm->dma_cb(bm, 0);
2667
        }
2668
        bm->cmd = val & 0x09;
2669
    }
2670
}
2671

    
2672
static uint32_t bmdma_readb(void *opaque, uint32_t addr)
2673
{
2674
    BMDMAState *bm = opaque;
2675
    PCIIDEState *pci_dev;
2676
    uint32_t val;
2677

    
2678
    switch(addr & 3) {
2679
    case 0:
2680
        val = bm->cmd;
2681
        break;
2682
    case 1:
2683
        pci_dev = bm->pci_dev;
2684
        if (pci_dev->type == IDE_TYPE_CMD646) {
2685
            val = pci_dev->dev.config[MRDMODE];
2686
        } else {
2687
            val = 0xff;
2688
        }
2689
        break;
2690
    case 2:
2691
        val = bm->status;
2692
        break;
2693
    case 3:
2694
        pci_dev = bm->pci_dev;
2695
        if (pci_dev->type == IDE_TYPE_CMD646) {
2696
            if (bm == &pci_dev->bmdma[0])
2697
                val = pci_dev->dev.config[UDIDETCR0];
2698
            else
2699
                val = pci_dev->dev.config[UDIDETCR1];
2700
        } else {
2701
            val = 0xff;
2702
        }
2703
        break;
2704
    default:
2705
        val = 0xff;
2706
        break;
2707
    }
2708
#ifdef DEBUG_IDE
2709
    printf("bmdma: readb 0x%02x : 0x%02x\n", addr, val);
2710
#endif
2711
    return val;
2712
}
2713

    
2714
static void bmdma_writeb(void *opaque, uint32_t addr, uint32_t val)
2715
{
2716
    BMDMAState *bm = opaque;
2717
    PCIIDEState *pci_dev;
2718
#ifdef DEBUG_IDE
2719
    printf("bmdma: writeb 0x%02x : 0x%02x\n", addr, val);
2720
#endif
2721
    switch(addr & 3) {
2722
    case 1:
2723
        pci_dev = bm->pci_dev;
2724
        if (pci_dev->type == IDE_TYPE_CMD646) {
2725
            pci_dev->dev.config[MRDMODE] =
2726
                (pci_dev->dev.config[MRDMODE] & ~0x30) | (val & 0x30);
2727
            cmd646_update_irq(pci_dev);
2728
        }
2729
        break;
2730
    case 2:
2731
        bm->status = (val & 0x60) | (bm->status & 1) | (bm->status & ~val & 0x06);
2732
        break;
2733
    case 3:
2734
        pci_dev = bm->pci_dev;
2735
        if (pci_dev->type == IDE_TYPE_CMD646) {
2736
            if (bm == &pci_dev->bmdma[0])
2737
                pci_dev->dev.config[UDIDETCR0] = val;
2738
            else
2739
                pci_dev->dev.config[UDIDETCR1] = val;
2740
        }
2741
        break;
2742
    }
2743
}
2744

    
2745
static uint32_t bmdma_addr_readl(void *opaque, uint32_t addr)
2746
{
2747
    BMDMAState *bm = opaque;
2748
    uint32_t val;
2749
    val = bm->addr;
2750
#ifdef DEBUG_IDE
2751
    printf("%s: 0x%08x\n", __func__, val);
2752
#endif
2753
    return val;
2754
}
2755

    
2756
static void bmdma_addr_writel(void *opaque, uint32_t addr, uint32_t val)
2757
{
2758
    BMDMAState *bm = opaque;
2759
#ifdef DEBUG_IDE
2760
    printf("%s: 0x%08x\n", __func__, val);
2761
#endif
2762
    bm->addr = val & ~3;
2763
    bm->cur_addr = bm->addr;
2764
}
2765

    
2766
static void bmdma_map(PCIDevice *pci_dev, int region_num,
2767
                    uint32_t addr, uint32_t size, int type)
2768
{
2769
    PCIIDEState *d = (PCIIDEState *)pci_dev;
2770
    int i;
2771

    
2772
    for(i = 0;i < 2; i++) {
2773
        BMDMAState *bm = &d->bmdma[i];
2774
        d->ide_if[2 * i].bmdma = bm;
2775
        d->ide_if[2 * i + 1].bmdma = bm;
2776
        bm->pci_dev = (PCIIDEState *)pci_dev;
2777

    
2778
        register_ioport_write(addr, 1, 1, bmdma_cmd_writeb, bm);
2779

    
2780
        register_ioport_write(addr + 1, 3, 1, bmdma_writeb, bm);
2781
        register_ioport_read(addr, 4, 1, bmdma_readb, bm);
2782

    
2783
        register_ioport_write(addr + 4, 4, 4, bmdma_addr_writel, bm);
2784
        register_ioport_read(addr + 4, 4, 4, bmdma_addr_readl, bm);
2785
        addr += 8;
2786
    }
2787
}
2788

    
2789
/* XXX: call it also when the MRDMODE is changed from the PCI config
2790
   registers */
2791
static void cmd646_update_irq(PCIIDEState *d)
2792
{
2793
    int pci_level;
2794
    pci_level = ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH0) &&
2795
                 !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH0)) ||
2796
        ((d->dev.config[MRDMODE] & MRDMODE_INTR_CH1) &&
2797
         !(d->dev.config[MRDMODE] & MRDMODE_BLK_CH1));
2798
    qemu_set_irq(d->dev.irq[0], pci_level);
2799
}
2800

    
2801
/* the PCI irq level is the logical OR of the two channels */
2802
static void cmd646_set_irq(void *opaque, int channel, int level)
2803
{
2804
    PCIIDEState *d = opaque;
2805
    int irq_mask;
2806

    
2807
    irq_mask = MRDMODE_INTR_CH0 << channel;
2808
    if (level)
2809
        d->dev.config[MRDMODE] |= irq_mask;
2810
    else
2811
        d->dev.config[MRDMODE] &= ~irq_mask;
2812
    cmd646_update_irq(d);
2813
}
2814

    
2815
/* CMD646 PCI IDE controller */
2816
void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
2817
                         int secondary_ide_enabled)
2818
{
2819
    PCIIDEState *d;
2820
    uint8_t *pci_conf;
2821
    int i;
2822
    qemu_irq *irq;
2823

    
2824
    d = (PCIIDEState *)pci_register_device(bus, "CMD646 IDE",
2825
                                           sizeof(PCIIDEState),
2826
                                           -1,
2827
                                           NULL, NULL);
2828
    d->type = IDE_TYPE_CMD646;
2829
    pci_conf = d->dev.config;
2830
    pci_conf[0x00] = 0x95; // CMD646
2831
    pci_conf[0x01] = 0x10;
2832
    pci_conf[0x02] = 0x46;
2833
    pci_conf[0x03] = 0x06;
2834

    
2835
    pci_conf[0x08] = 0x07; // IDE controller revision
2836
    pci_conf[0x09] = 0x8f;
2837

    
2838
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2839
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2840
    pci_conf[0x0e] = 0x00; // header_type
2841

    
2842
    if (secondary_ide_enabled) {
2843
        /* XXX: if not enabled, really disable the seconday IDE controller */
2844
        pci_conf[0x51] = 0x80; /* enable IDE1 */
2845
    }
2846

    
2847
    pci_register_io_region((PCIDevice *)d, 0, 0x8,
2848
                           PCI_ADDRESS_SPACE_IO, ide_map);
2849
    pci_register_io_region((PCIDevice *)d, 1, 0x4,
2850
                           PCI_ADDRESS_SPACE_IO, ide_map);
2851
    pci_register_io_region((PCIDevice *)d, 2, 0x8,
2852
                           PCI_ADDRESS_SPACE_IO, ide_map);
2853
    pci_register_io_region((PCIDevice *)d, 3, 0x4,
2854
                           PCI_ADDRESS_SPACE_IO, ide_map);
2855
    pci_register_io_region((PCIDevice *)d, 4, 0x10,
2856
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
2857

    
2858
    pci_conf[0x3d] = 0x01; // interrupt on pin 1
2859

    
2860
    for(i = 0; i < 4; i++)
2861
        d->ide_if[i].pci_dev = (PCIDevice *)d;
2862

    
2863
    irq = qemu_allocate_irqs(cmd646_set_irq, d, 2);
2864
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], irq[0]);
2865
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], irq[1]);
2866
}
2867

    
2868
static void pci_ide_save(QEMUFile* f, void *opaque)
2869
{
2870
    PCIIDEState *d = opaque;
2871
    int i;
2872

    
2873
    pci_device_save(&d->dev, f);
2874

    
2875
    for(i = 0; i < 2; i++) {
2876
        BMDMAState *bm = &d->bmdma[i];
2877
        qemu_put_8s(f, &bm->cmd);
2878
        qemu_put_8s(f, &bm->status);
2879
        qemu_put_be32s(f, &bm->addr);
2880
        /* XXX: if a transfer is pending, we do not save it yet */
2881
    }
2882

    
2883
    /* per IDE interface data */
2884
    for(i = 0; i < 2; i++) {
2885
        IDEState *s = &d->ide_if[i * 2];
2886
        uint8_t drive1_selected;
2887
        qemu_put_8s(f, &s->cmd);
2888
        drive1_selected = (s->cur_drive != s);
2889
        qemu_put_8s(f, &drive1_selected);
2890
    }
2891

    
2892
    /* per IDE drive data */
2893
    for(i = 0; i < 4; i++) {
2894
        ide_save(f, &d->ide_if[i]);
2895
    }
2896
}
2897

    
2898
static int pci_ide_load(QEMUFile* f, void *opaque, int version_id)
2899
{
2900
    PCIIDEState *d = opaque;
2901
    int ret, i;
2902

    
2903
    if (version_id != 1)
2904
        return -EINVAL;
2905
    ret = pci_device_load(&d->dev, f);
2906
    if (ret < 0)
2907
        return ret;
2908

    
2909
    for(i = 0; i < 2; i++) {
2910
        BMDMAState *bm = &d->bmdma[i];
2911
        qemu_get_8s(f, &bm->cmd);
2912
        qemu_get_8s(f, &bm->status);
2913
        qemu_get_be32s(f, &bm->addr);
2914
        /* XXX: if a transfer is pending, we do not save it yet */
2915
    }
2916

    
2917
    /* per IDE interface data */
2918
    for(i = 0; i < 2; i++) {
2919
        IDEState *s = &d->ide_if[i * 2];
2920
        uint8_t drive1_selected;
2921
        qemu_get_8s(f, &s->cmd);
2922
        qemu_get_8s(f, &drive1_selected);
2923
        s->cur_drive = &d->ide_if[i * 2 + (drive1_selected != 0)];
2924
    }
2925

    
2926
    /* per IDE drive data */
2927
    for(i = 0; i < 4; i++) {
2928
        ide_load(f, &d->ide_if[i]);
2929
    }
2930
    return 0;
2931
}
2932

    
2933
static void piix3_reset(PCIIDEState *d)
2934
{
2935
    uint8_t *pci_conf = d->dev.config;
2936

    
2937
    pci_conf[0x04] = 0x00;
2938
    pci_conf[0x05] = 0x00;
2939
    pci_conf[0x06] = 0x80; /* FBC */
2940
    pci_conf[0x07] = 0x02; // PCI_status_devsel_medium
2941
    pci_conf[0x20] = 0x01; /* BMIBA: 20-23h */
2942
}
2943

    
2944
/* hd_table must contain 4 block drivers */
2945
/* NOTE: for the PIIX3, the IRQs and IOports are hardcoded */
2946
void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2947
                        qemu_irq *pic)
2948
{
2949
    PCIIDEState *d;
2950
    uint8_t *pci_conf;
2951

    
2952
    /* register a function 1 of PIIX3 */
2953
    d = (PCIIDEState *)pci_register_device(bus, "PIIX3 IDE",
2954
                                           sizeof(PCIIDEState),
2955
                                           devfn,
2956
                                           NULL, NULL);
2957
    d->type = IDE_TYPE_PIIX3;
2958

    
2959
    pci_conf = d->dev.config;
2960
    pci_conf[0x00] = 0x86; // Intel
2961
    pci_conf[0x01] = 0x80;
2962
    pci_conf[0x02] = 0x10;
2963
    pci_conf[0x03] = 0x70;
2964
    pci_conf[0x09] = 0x80; // legacy ATA mode
2965
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
2966
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
2967
    pci_conf[0x0e] = 0x00; // header_type
2968

    
2969
    piix3_reset(d);
2970

    
2971
    pci_register_io_region((PCIDevice *)d, 4, 0x10,
2972
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
2973

    
2974
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
2975
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
2976
    ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
2977
    ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
2978

    
2979
    register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
2980
}
2981

    
2982
/* hd_table must contain 4 block drivers */
2983
/* NOTE: for the PIIX4, the IRQs and IOports are hardcoded */
2984
void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
2985
                        qemu_irq *pic)
2986
{
2987
    PCIIDEState *d;
2988
    uint8_t *pci_conf;
2989

    
2990
    /* register a function 1 of PIIX4 */
2991
    d = (PCIIDEState *)pci_register_device(bus, "PIIX4 IDE",
2992
                                           sizeof(PCIIDEState),
2993
                                           devfn,
2994
                                           NULL, NULL);
2995
    d->type = IDE_TYPE_PIIX4;
2996

    
2997
    pci_conf = d->dev.config;
2998
    pci_conf[0x00] = 0x86; // Intel
2999
    pci_conf[0x01] = 0x80;
3000
    pci_conf[0x02] = 0x11;
3001
    pci_conf[0x03] = 0x71;
3002
    pci_conf[0x09] = 0x80; // legacy ATA mode
3003
    pci_conf[0x0a] = 0x01; // class_sub = PCI_IDE
3004
    pci_conf[0x0b] = 0x01; // class_base = PCI_mass_storage
3005
    pci_conf[0x0e] = 0x00; // header_type
3006

    
3007
    piix3_reset(d);
3008

    
3009
    pci_register_io_region((PCIDevice *)d, 4, 0x10,
3010
                           PCI_ADDRESS_SPACE_IO, bmdma_map);
3011

    
3012
    ide_init2(&d->ide_if[0], hd_table[0], hd_table[1], pic[14]);
3013
    ide_init2(&d->ide_if[2], hd_table[2], hd_table[3], pic[15]);
3014
    ide_init_ioport(&d->ide_if[0], 0x1f0, 0x3f6);
3015
    ide_init_ioport(&d->ide_if[2], 0x170, 0x376);
3016

    
3017
    register_savevm("ide", 0, 1, pci_ide_save, pci_ide_load, d);
3018
}
3019

    
3020
/***********************************************************/
3021
/* MacIO based PowerPC IDE */
3022

    
3023
/* PowerMac IDE memory IO */
3024
static void pmac_ide_writeb (void *opaque,
3025
                             target_phys_addr_t addr, uint32_t val)
3026
{
3027
    addr = (addr & 0xFFF) >> 4;
3028
    switch (addr) {
3029
    case 1 ... 7:
3030
        ide_ioport_write(opaque, addr, val);
3031
        break;
3032
    case 8:
3033
    case 22:
3034
        ide_cmd_write(opaque, 0, val);
3035
        break;
3036
    default:
3037
        break;
3038
    }
3039
}
3040

    
3041
static uint32_t pmac_ide_readb (void *opaque,target_phys_addr_t addr)
3042
{
3043
    uint8_t retval;
3044

    
3045
    addr = (addr & 0xFFF) >> 4;
3046
    switch (addr) {
3047
    case 1 ... 7:
3048
        retval = ide_ioport_read(opaque, addr);
3049
        break;
3050
    case 8:
3051
    case 22:
3052
        retval = ide_status_read(opaque, 0);
3053
        break;
3054
    default:
3055
        retval = 0xFF;
3056
        break;
3057
    }
3058
    return retval;
3059
}
3060

    
3061
static void pmac_ide_writew (void *opaque,
3062
                             target_phys_addr_t addr, uint32_t val)
3063
{
3064
    addr = (addr & 0xFFF) >> 4;
3065
#ifdef TARGET_WORDS_BIGENDIAN
3066
    val = bswap16(val);
3067
#endif
3068
    if (addr == 0) {
3069
        ide_data_writew(opaque, 0, val);
3070
    }
3071
}
3072

    
3073
static uint32_t pmac_ide_readw (void *opaque,target_phys_addr_t addr)
3074
{
3075
    uint16_t retval;
3076

    
3077
    addr = (addr & 0xFFF) >> 4;
3078
    if (addr == 0) {
3079
        retval = ide_data_readw(opaque, 0);
3080
    } else {
3081
        retval = 0xFFFF;
3082
    }
3083
#ifdef TARGET_WORDS_BIGENDIAN
3084
    retval = bswap16(retval);
3085
#endif
3086
    return retval;
3087
}
3088

    
3089
static void pmac_ide_writel (void *opaque,
3090
                             target_phys_addr_t addr, uint32_t val)
3091
{
3092
    addr = (addr & 0xFFF) >> 4;
3093
#ifdef TARGET_WORDS_BIGENDIAN
3094
    val = bswap32(val);
3095
#endif
3096
    if (addr == 0) {
3097
        ide_data_writel(opaque, 0, val);
3098
    }
3099
}
3100

    
3101
static uint32_t pmac_ide_readl (void *opaque,target_phys_addr_t addr)
3102
{
3103
    uint32_t retval;
3104

    
3105
    addr = (addr & 0xFFF) >> 4;
3106
    if (addr == 0) {
3107
        retval = ide_data_readl(opaque, 0);
3108
    } else {
3109
        retval = 0xFFFFFFFF;
3110
    }
3111
#ifdef TARGET_WORDS_BIGENDIAN
3112
    retval = bswap32(retval);
3113
#endif
3114
    return retval;
3115
}
3116

    
3117
static CPUWriteMemoryFunc *pmac_ide_write[] = {
3118
    pmac_ide_writeb,
3119
    pmac_ide_writew,
3120
    pmac_ide_writel,
3121
};
3122

    
3123
static CPUReadMemoryFunc *pmac_ide_read[] = {
3124
    pmac_ide_readb,
3125
    pmac_ide_readw,
3126
    pmac_ide_readl,
3127
};
3128

    
3129
/* hd_table must contain 4 block drivers */
3130
/* PowerMac uses memory mapped registers, not I/O. Return the memory
3131
   I/O index to access the ide. */
3132
int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq)
3133
{
3134
    IDEState *ide_if;
3135
    int pmac_ide_memory;
3136

    
3137
    ide_if = qemu_mallocz(sizeof(IDEState) * 2);
3138
    ide_init2(&ide_if[0], hd_table[0], hd_table[1], irq);
3139

    
3140
    pmac_ide_memory = cpu_register_io_memory(0, pmac_ide_read,
3141
                                             pmac_ide_write, &ide_if[0]);
3142
    return pmac_ide_memory;
3143
}
3144

    
3145
/***********************************************************/
3146
/* CF-ATA Microdrive */
3147

    
3148
#define METADATA_SIZE        0x20
3149

    
3150
/* DSCM-1XXXX Microdrive hard disk with CF+ II / PCMCIA interface.  */
3151
struct md_s {
3152
    IDEState ide[2];
3153
    struct pcmcia_card_s card;
3154
    uint32_t attr_base;
3155
    uint32_t io_base;
3156

    
3157
    /* Card state */
3158
    uint8_t opt;
3159
    uint8_t stat;
3160
    uint8_t pins;
3161

    
3162
    uint8_t ctrl;
3163
    uint16_t io;
3164
    int cycle;
3165
};
3166

    
3167
/* Register bitfields */
3168
enum md_opt {
3169
    OPT_MODE_MMAP        = 0,
3170
    OPT_MODE_IOMAP16        = 1,
3171
    OPT_MODE_IOMAP1        = 2,
3172
    OPT_MODE_IOMAP2        = 3,
3173
    OPT_MODE                = 0x3f,
3174
    OPT_LEVIREQ                = 0x40,
3175
    OPT_SRESET                = 0x80,
3176
};
3177
enum md_cstat {
3178
    STAT_INT                = 0x02,
3179
    STAT_PWRDWN                = 0x04,
3180
    STAT_XE                = 0x10,
3181
    STAT_IOIS8                = 0x20,
3182
    STAT_SIGCHG                = 0x40,
3183
    STAT_CHANGED        = 0x80,
3184
};
3185
enum md_pins {
3186
    PINS_MRDY                = 0x02,
3187
    PINS_CRDY                = 0x20,
3188
};
3189
enum md_ctrl {
3190
    CTRL_IEN                = 0x02,
3191
    CTRL_SRST                = 0x04,
3192
};
3193

    
3194
static inline void md_interrupt_update(struct md_s *s)
3195
{
3196
    if (!s->card.slot)
3197
        return;
3198

    
3199
    qemu_set_irq(s->card.slot->irq,
3200
                    !(s->stat & STAT_INT) &&        /* Inverted */
3201
                    !(s->ctrl & (CTRL_IEN | CTRL_SRST)) &&
3202
                    !(s->opt & OPT_SRESET));
3203
}
3204

    
3205
static void md_set_irq(void *opaque, int irq, int level)
3206
{
3207
    struct md_s *s = (struct md_s *) opaque;
3208
    if (level)
3209
        s->stat |= STAT_INT;
3210
    else
3211
        s->stat &= ~STAT_INT;
3212

    
3213
    md_interrupt_update(s);
3214
}
3215

    
3216
static void md_reset(struct md_s *s)
3217
{
3218
    s->opt = OPT_MODE_MMAP;
3219
    s->stat = 0;
3220
    s->pins = 0;
3221
    s->cycle = 0;
3222
    s->ctrl = 0;
3223
    ide_reset(s->ide);
3224
}
3225

    
3226
static uint8_t md_attr_read(void *opaque, uint32_t at)
3227
{
3228
    struct md_s *s = (struct md_s *) opaque;
3229
    if (at < s->attr_base) {
3230
        if (at < s->card.cis_len)
3231
            return s->card.cis[at];
3232
        else
3233
            return 0x00;
3234
    }
3235

    
3236
    at -= s->attr_base;
3237

    
3238
    switch (at) {
3239
    case 0x00:        /* Configuration Option Register */
3240
        return s->opt;
3241
    case 0x02:        /* Card Configuration Status Register */
3242
        if (s->ctrl & CTRL_IEN)
3243
            return s->stat & ~STAT_INT;
3244
        else
3245
            return s->stat;
3246
    case 0x04:        /* Pin Replacement Register */
3247
        return (s->pins & PINS_CRDY) | 0x0c;
3248
    case 0x06:        /* Socket and Copy Register */
3249
        return 0x00;
3250
#ifdef VERBOSE
3251
    default:
3252
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3253
#endif
3254
    }
3255

    
3256
    return 0;
3257
}
3258

    
3259
static void md_attr_write(void *opaque, uint32_t at, uint8_t value)
3260
{
3261
    struct md_s *s = (struct md_s *) opaque;
3262
    at -= s->attr_base;
3263

    
3264
    switch (at) {
3265
    case 0x00:        /* Configuration Option Register */
3266
        s->opt = value & 0xcf;
3267
        if (value & OPT_SRESET)
3268
            md_reset(s);
3269
        md_interrupt_update(s);
3270
        break;
3271
    case 0x02:        /* Card Configuration Status Register */
3272
        if ((s->stat ^ value) & STAT_PWRDWN)
3273
            s->pins |= PINS_CRDY;
3274
        s->stat &= 0x82;
3275
        s->stat |= value & 0x74;
3276
        md_interrupt_update(s);
3277
        /* Word 170 in Identify Device must be equal to STAT_XE */
3278
        break;
3279
    case 0x04:        /* Pin Replacement Register */
3280
        s->pins &= PINS_CRDY;
3281
        s->pins |= value & PINS_MRDY;
3282
        break;
3283
    case 0x06:        /* Socket and Copy Register */
3284
        break;
3285
    default:
3286
        printf("%s: Bad attribute space register %02x\n", __FUNCTION__, at);
3287
    }
3288
}
3289

    
3290
static uint16_t md_common_read(void *opaque, uint32_t at)
3291
{
3292
    struct md_s *s = (struct md_s *) opaque;
3293
    uint16_t ret;
3294
    at -= s->io_base;
3295

    
3296
    switch (s->opt & OPT_MODE) {
3297
    case OPT_MODE_MMAP:
3298
        if ((at & ~0x3ff) == 0x400)
3299
            at = 0;
3300
        break;
3301
    case OPT_MODE_IOMAP16:
3302
        at &= 0xf;
3303
        break;
3304
    case OPT_MODE_IOMAP1:
3305
        if ((at & ~0xf) == 0x3f0)
3306
            at -= 0x3e8;
3307
        else if ((at & ~0xf) == 0x1f0)
3308
            at -= 0x1f0;
3309
        break;
3310
    case OPT_MODE_IOMAP2:
3311
        if ((at & ~0xf) == 0x370)
3312
            at -= 0x368;
3313
        else if ((at & ~0xf) == 0x170)
3314
            at -= 0x170;
3315
    }
3316

    
3317
    switch (at) {
3318
    case 0x0:        /* Even RD Data */
3319
    case 0x8:
3320
        return ide_data_readw(s->ide, 0);
3321

    
3322
        /* TODO: 8-bit accesses */
3323
        if (s->cycle)
3324
            ret = s->io >> 8;
3325
        else {
3326
            s->io = ide_data_readw(s->ide, 0);
3327
            ret = s->io & 0xff;
3328
        }
3329
        s->cycle = !s->cycle;
3330
        return ret;
3331
    case 0x9:        /* Odd RD Data */
3332
        return s->io >> 8;
3333
    case 0xd:        /* Error */
3334
        return ide_ioport_read(s->ide, 0x1);
3335
    case 0xe:        /* Alternate Status */
3336
        if (s->ide->cur_drive->bs)
3337
            return s->ide->cur_drive->status;
3338
        else
3339
            return 0;
3340
    case 0xf:        /* Device Address */
3341
        return 0xc2 | ((~s->ide->select << 2) & 0x3c);
3342
    default:
3343
        return ide_ioport_read(s->ide, at);
3344
    }
3345

    
3346
    return 0;
3347
}
3348

    
3349
static void md_common_write(void *opaque, uint32_t at, uint16_t value)
3350
{
3351
    struct md_s *s = (struct md_s *) opaque;
3352
    at -= s->io_base;
3353

    
3354
    switch (s->opt & OPT_MODE) {
3355
    case OPT_MODE_MMAP:
3356
        if ((at & ~0x3ff) == 0x400)
3357
            at = 0;
3358
        break;
3359
    case OPT_MODE_IOMAP16:
3360
        at &= 0xf;
3361
        break;
3362
    case OPT_MODE_IOMAP1:
3363
        if ((at & ~0xf) == 0x3f0)
3364
            at -= 0x3e8;
3365
        else if ((at & ~0xf) == 0x1f0)
3366
            at -= 0x1f0;
3367
        break;
3368
    case OPT_MODE_IOMAP2:
3369
        if ((at & ~0xf) == 0x370)
3370
            at -= 0x368;
3371
        else if ((at & ~0xf) == 0x170)
3372
            at -= 0x170;
3373
    }
3374

    
3375
    switch (at) {
3376
    case 0x0:        /* Even WR Data */
3377
    case 0x8:
3378
        ide_data_writew(s->ide, 0, value);
3379
        break;
3380

    
3381
        /* TODO: 8-bit accesses */
3382
        if (s->cycle)
3383
            ide_data_writew(s->ide, 0, s->io | (value << 8));
3384
        else
3385
            s->io = value & 0xff;
3386
        s->cycle = !s->cycle;
3387
        break;
3388
    case 0x9:
3389
        s->io = value & 0xff;
3390
        s->cycle = !s->cycle;
3391
        break;
3392
    case 0xd:        /* Features */
3393
        ide_ioport_write(s->ide, 0x1, value);
3394
        break;
3395
    case 0xe:        /* Device Control */
3396
        s->ctrl = value;
3397
        if (value & CTRL_SRST)
3398
            md_reset(s);
3399
        md_interrupt_update(s);
3400
        break;
3401
    default:
3402
        if (s->stat & STAT_PWRDWN) {
3403
            s->pins |= PINS_CRDY;
3404
            s->stat &= ~STAT_PWRDWN;
3405
        }
3406
        ide_ioport_write(s->ide, at, value);
3407
    }
3408
}
3409

    
3410
static void md_save(QEMUFile *f, void *opaque)
3411
{
3412
    struct md_s *s = (struct md_s *) opaque;
3413
    int i;
3414
    uint8_t drive1_selected;
3415

    
3416
    qemu_put_8s(f, &s->opt);
3417
    qemu_put_8s(f, &s->stat);
3418
    qemu_put_8s(f, &s->pins);
3419

    
3420
    qemu_put_8s(f, &s->ctrl);
3421
    qemu_put_be16s(f, &s->io);
3422
    qemu_put_byte(f, s->cycle);
3423

    
3424
    drive1_selected = (s->ide->cur_drive != s->ide);
3425
    qemu_put_8s(f, &s->ide->cmd);
3426
    qemu_put_8s(f, &drive1_selected);
3427

    
3428
    for (i = 0; i < 2; i ++)
3429
        ide_save(f, &s->ide[i]);
3430
}
3431

    
3432
static int md_load(QEMUFile *f, void *opaque, int version_id)
3433
{
3434
    struct md_s *s = (struct md_s *) opaque;
3435
    int i;
3436
    uint8_t drive1_selected;
3437

    
3438
    qemu_get_8s(f, &s->opt);
3439
    qemu_get_8s(f, &s->stat);
3440
    qemu_get_8s(f, &s->pins);
3441

    
3442
    qemu_get_8s(f, &s->ctrl);
3443
    qemu_get_be16s(f, &s->io);
3444
    s->cycle = qemu_get_byte(f);
3445

    
3446
    qemu_get_8s(f, &s->ide->cmd);
3447
    qemu_get_8s(f, &drive1_selected);
3448
    s->ide->cur_drive = &s->ide[(drive1_selected != 0)];
3449

    
3450
    for (i = 0; i < 2; i ++)
3451
        ide_load(f, &s->ide[i]);
3452

    
3453
    return 0;
3454
}
3455

    
3456
static int md_iid = 0;
3457

    
3458
static const uint8_t dscm1xxxx_cis[0x14a] = {
3459
    [0x000] = CISTPL_DEVICE,        /* 5V Device Information */
3460
    [0x002] = 0x03,                /* Tuple length = 4 bytes */
3461
    [0x004] = 0xdb,                /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3462
    [0x006] = 0x01,                /* Size = 2K bytes */
3463
    [0x008] = CISTPL_ENDMARK,
3464

    
3465
    [0x00a] = CISTPL_DEVICE_OC,        /* Additional Device Information */
3466
    [0x00c] = 0x04,                /* Tuple length = 4 byest */
3467
    [0x00e] = 0x03,                /* Conditions: Ext = 0, Vcc 3.3V, MWAIT = 1 */
3468
    [0x010] = 0xdb,                /* ID: DTYPE_FUNCSPEC, non WP, DSPEED_150NS */
3469
    [0x012] = 0x01,                /* Size = 2K bytes */
3470
    [0x014] = CISTPL_ENDMARK,
3471

    
3472
    [0x016] = CISTPL_JEDEC_C,        /* JEDEC ID */
3473
    [0x018] = 0x02,                /* Tuple length = 2 bytes */
3474
    [0x01a] = 0xdf,                /* PC Card ATA with no Vpp required */
3475
    [0x01c] = 0x01,
3476

    
3477
    [0x01e] = CISTPL_MANFID,        /* Manufacture ID */
3478
    [0x020] = 0x04,                /* Tuple length = 4 bytes */
3479
    [0x022] = 0xa4,                /* TPLMID_MANF = 00a4 (IBM) */
3480
    [0x024] = 0x00,
3481
    [0x026] = 0x00,                /* PLMID_CARD = 0000 */
3482
    [0x028] = 0x00,
3483

    
3484
    [0x02a] = CISTPL_VERS_1,        /* Level 1 Version */
3485
    [0x02c] = 0x12,                /* Tuple length = 23 bytes */
3486
    [0x02e] = 0x04,                /* Major Version = JEIDA 4.2 / PCMCIA 2.1 */
3487
    [0x030] = 0x01,                /* Minor Version = 1 */
3488
    [0x032] = 'I',
3489
    [0x034] = 'B',
3490
    [0x036] = 'M',
3491
    [0x038] = 0x00,
3492
    [0x03a] = 'm',
3493
    [0x03c] = 'i',
3494
    [0x03e] = 'c',
3495
    [0x040] = 'r',
3496
    [0x042] = 'o',
3497
    [0x044] = 'd',
3498
    [0x046] = 'r',
3499
    [0x048] = 'i',
3500
    [0x04a] = 'v',
3501
    [0x04c] = 'e',
3502
    [0x04e] = 0x00,
3503
    [0x050] = CISTPL_ENDMARK,
3504

    
3505
    [0x052] = CISTPL_FUNCID,        /* Function ID */
3506
    [0x054] = 0x02,                /* Tuple length = 2 bytes */
3507
    [0x056] = 0x04,                /* TPLFID_FUNCTION = Fixed Disk */
3508
    [0x058] = 0x01,                /* TPLFID_SYSINIT: POST = 1, ROM = 0 */
3509

    
3510
    [0x05a] = CISTPL_FUNCE,        /* Function Extension */
3511
    [0x05c] = 0x02,                /* Tuple length = 2 bytes */
3512
    [0x05e] = 0x01,                /* TPLFE_TYPE = Disk Device Interface */
3513
    [0x060] = 0x01,                /* TPLFE_DATA = PC Card ATA Interface */
3514

    
3515
    [0x062] = CISTPL_FUNCE,        /* Function Extension */
3516
    [0x064] = 0x03,                /* Tuple length = 3 bytes */
3517
    [0x066] = 0x02,                /* TPLFE_TYPE = Basic PC Card ATA Interface */
3518
    [0x068] = 0x08,                /* TPLFE_DATA: Rotating, Unique, Single */
3519
    [0x06a] = 0x0f,                /* TPLFE_DATA: Sleep, Standby, Idle, Auto */
3520

    
3521
    [0x06c] = CISTPL_CONFIG,        /* Configuration */
3522
    [0x06e] = 0x05,                /* Tuple length = 5 bytes */
3523
    [0x070] = 0x01,                /* TPCC_RASZ = 2 bytes, TPCC_RMSZ = 1 byte */
3524
    [0x072] = 0x07,                /* TPCC_LAST = 7 */
3525
    [0x074] = 0x00,                /* TPCC_RADR = 0200 */
3526
    [0x076] = 0x02,
3527
    [0x078] = 0x0f,                /* TPCC_RMSK = 200, 202, 204, 206 */
3528

    
3529
    [0x07a] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3530
    [0x07c] = 0x0b,                /* Tuple length = 11 bytes */
3531
    [0x07e] = 0xc0,                /* TPCE_INDX = Memory Mode, Default, Iface */
3532
    [0x080] = 0xc0,                /* TPCE_IF = Memory, no BVDs, no WP, READY */
3533
    [0x082] = 0xa1,                /* TPCE_FS = Vcc only, no I/O, Memory, Misc */
3534
    [0x084] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3535
    [0x086] = 0x55,                /* NomV: 5.0 V */
3536
    [0x088] = 0x4d,                /* MinV: 4.5 V */
3537
    [0x08a] = 0x5d,                /* MaxV: 5.5 V */
3538
    [0x08c] = 0x4e,                /* Peakl: 450 mA */
3539
    [0x08e] = 0x08,                /* TPCE_MS = 1 window, 1 byte, Host address */
3540
    [0x090] = 0x00,                /* Window descriptor: Window length = 0 */
3541
    [0x092] = 0x20,                /* TPCE_MI: support power down mode, RW */
3542

    
3543
    [0x094] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3544
    [0x096] = 0x06,                /* Tuple length = 6 bytes */
3545
    [0x098] = 0x00,                /* TPCE_INDX = Memory Mode, no Default */
3546
    [0x09a] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3547
    [0x09c] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3548
    [0x09e] = 0xb5,                /* NomV: 3.3 V */
3549
    [0x0a0] = 0x1e,
3550
    [0x0a2] = 0x3e,                /* Peakl: 350 mA */
3551

    
3552
    [0x0a4] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3553
    [0x0a6] = 0x0d,                /* Tuple length = 13 bytes */
3554
    [0x0a8] = 0xc1,                /* TPCE_INDX = I/O and Memory Mode, Default */
3555
    [0x0aa] = 0x41,                /* TPCE_IF = I/O and Memory, no BVD, no WP */
3556
    [0x0ac] = 0x99,                /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3557
    [0x0ae] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3558
    [0x0b0] = 0x55,                /* NomV: 5.0 V */
3559
    [0x0b2] = 0x4d,                /* MinV: 4.5 V */
3560
    [0x0b4] = 0x5d,                /* MaxV: 5.5 V */
3561
    [0x0b6] = 0x4e,                /* Peakl: 450 mA */
3562
    [0x0b8] = 0x64,                /* TPCE_IO = 16-byte boundary, 16/8 accesses */
3563
    [0x0ba] = 0xf0,                /* TPCE_IR =  MASK, Level, Pulse, Share */
3564
    [0x0bc] = 0xff,                /* IRQ0..IRQ7 supported */
3565
    [0x0be] = 0xff,                /* IRQ8..IRQ15 supported */
3566
    [0x0c0] = 0x20,                /* TPCE_MI = support power down mode */
3567

    
3568
    [0x0c2] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3569
    [0x0c4] = 0x06,                /* Tuple length = 6 bytes */
3570
    [0x0c6] = 0x01,                /* TPCE_INDX = I/O and Memory Mode */
3571
    [0x0c8] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3572
    [0x0ca] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3573
    [0x0cc] = 0xb5,                /* NomV: 3.3 V */
3574
    [0x0ce] = 0x1e,
3575
    [0x0d0] = 0x3e,                /* Peakl: 350 mA */
3576

    
3577
    [0x0d2] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3578
    [0x0d4] = 0x12,                /* Tuple length = 18 bytes */
3579
    [0x0d6] = 0xc2,                /* TPCE_INDX = I/O Primary Mode */
3580
    [0x0d8] = 0x41,                /* TPCE_IF = I/O and Memory, no BVD, no WP */
3581
    [0x0da] = 0x99,                /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3582
    [0x0dc] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3583
    [0x0de] = 0x55,                /* NomV: 5.0 V */
3584
    [0x0e0] = 0x4d,                /* MinV: 4.5 V */
3585
    [0x0e2] = 0x5d,                /* MaxV: 5.5 V */
3586
    [0x0e4] = 0x4e,                /* Peakl: 450 mA */
3587
    [0x0e6] = 0xea,                /* TPCE_IO = 1K boundary, 16/8 access, Range */
3588
    [0x0e8] = 0x61,                /* Range: 2 fields, 2 bytes addr, 1 byte len */
3589
    [0x0ea] = 0xf0,                /* Field 1 address = 0x01f0 */
3590
    [0x0ec] = 0x01,
3591
    [0x0ee] = 0x07,                /* Address block length = 8 */
3592
    [0x0f0] = 0xf6,                /* Field 2 address = 0x03f6 */
3593
    [0x0f2] = 0x03,
3594
    [0x0f4] = 0x01,                /* Address block length = 2 */
3595
    [0x0f6] = 0xee,                /* TPCE_IR = IRQ E, Level, Pulse, Share */
3596
    [0x0f8] = 0x20,                /* TPCE_MI = support power down mode */
3597

    
3598
    [0x0fa] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3599
    [0x0fc] = 0x06,                /* Tuple length = 6 bytes */
3600
    [0x0fe] = 0x02,                /* TPCE_INDX = I/O Primary Mode, no Default */
3601
    [0x100] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3602
    [0x102] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3603
    [0x104] = 0xb5,                /* NomV: 3.3 V */
3604
    [0x106] = 0x1e,
3605
    [0x108] = 0x3e,                /* Peakl: 350 mA */
3606

    
3607
    [0x10a] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3608
    [0x10c] = 0x12,                /* Tuple length = 18 bytes */
3609
    [0x10e] = 0xc3,                /* TPCE_INDX = I/O Secondary Mode, Default */
3610
    [0x110] = 0x41,                /* TPCE_IF = I/O and Memory, no BVD, no WP */
3611
    [0x112] = 0x99,                /* TPCE_FS = Vcc only, I/O, Interrupt, Misc */
3612
    [0x114] = 0x27,                /* NomV = 1, MinV = 1, MaxV = 1, Peakl = 1 */
3613
    [0x116] = 0x55,                /* NomV: 5.0 V */
3614
    [0x118] = 0x4d,                /* MinV: 4.5 V */
3615
    [0x11a] = 0x5d,                /* MaxV: 5.5 V */
3616
    [0x11c] = 0x4e,                /* Peakl: 450 mA */
3617
    [0x11e] = 0xea,                /* TPCE_IO = 1K boundary, 16/8 access, Range */
3618
    [0x120] = 0x61,                /* Range: 2 fields, 2 byte addr, 1 byte len */
3619
    [0x122] = 0x70,                /* Field 1 address = 0x0170 */
3620
    [0x124] = 0x01,
3621
    [0x126] = 0x07,                /* Address block length = 8 */
3622
    [0x128] = 0x76,                /* Field 2 address = 0x0376 */
3623
    [0x12a] = 0x03,
3624
    [0x12c] = 0x01,                /* Address block length = 2 */
3625
    [0x12e] = 0xee,                /* TPCE_IR = IRQ E, Level, Pulse, Share */
3626
    [0x130] = 0x20,                /* TPCE_MI = support power down mode */
3627

    
3628
    [0x132] = CISTPL_CFTABLE_ENTRY,        /* 16-bit PC Card Configuration */
3629
    [0x134] = 0x06,                /* Tuple length = 6 bytes */
3630
    [0x136] = 0x03,                /* TPCE_INDX = I/O Secondary Mode */
3631
    [0x138] = 0x01,                /* TPCE_FS = Vcc only, no I/O, no Memory */
3632
    [0x13a] = 0x21,                /* NomV = 1, MinV = 0, MaxV = 0, Peakl = 1 */
3633
    [0x13c] = 0xb5,                /* NomV: 3.3 V */
3634
    [0x13e] = 0x1e,
3635
    [0x140] = 0x3e,                /* Peakl: 350 mA */
3636

    
3637
    [0x142] = CISTPL_NO_LINK,        /* No Link */
3638
    [0x144] = 0x00,                /* Tuple length = 0 bytes */
3639

    
3640
    [0x146] = CISTPL_END,        /* Tuple End */
3641
};
3642

    
3643
static int dscm1xxxx_attach(void *opaque)
3644
{
3645
    struct md_s *md = (struct md_s *) opaque;
3646
    md->card.attr_read = md_attr_read;
3647
    md->card.attr_write = md_attr_write;
3648
    md->card.common_read = md_common_read;
3649
    md->card.common_write = md_common_write;
3650
    md->card.io_read = md_common_read;
3651
    md->card.io_write = md_common_write;
3652

    
3653
    md->attr_base = md->card.cis[0x74] | (md->card.cis[0x76] << 8);
3654
    md->io_base = 0x0;
3655

    
3656
    md_reset(md);
3657
    md_interrupt_update(md);
3658

    
3659
    md->card.slot->card_string = "DSCM-1xxxx Hitachi Microdrive";
3660
    return 0;
3661
}
3662

    
3663
static int dscm1xxxx_detach(void *opaque)
3664
{
3665
    struct md_s *md = (struct md_s *) opaque;
3666
    md_reset(md);
3667
    return 0;
3668
}
3669

    
3670
struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv)
3671
{
3672
    struct md_s *md = (struct md_s *) qemu_mallocz(sizeof(struct md_s));
3673
    md->card.state = md;
3674
    md->card.attach = dscm1xxxx_attach;
3675
    md->card.detach = dscm1xxxx_detach;
3676
    md->card.cis = dscm1xxxx_cis;
3677
    md->card.cis_len = sizeof(dscm1xxxx_cis);
3678

    
3679
    ide_init2(md->ide, bdrv, 0, qemu_allocate_irqs(md_set_irq, md, 1)[0]);
3680
    md->ide->is_cf = 1;
3681
    md->ide->mdata_size = METADATA_SIZE;
3682
    md->ide->mdata_storage = (uint8_t *) qemu_mallocz(METADATA_SIZE);
3683

    
3684
    register_savevm("microdrive", md_iid ++, 0, md_save, md_load, md);
3685

    
3686
    return &md->card;
3687
}