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1
/*
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 *  i386 translation
3
 * 
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 *  Copyright (c) 2003 Fabrice Bellard
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 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
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#include <stdarg.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <string.h>
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#include <inttypes.h>
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#include <signal.h>
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#include <assert.h>
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#include <sys/mman.h>
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#include "cpu.h"
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#include "exec-all.h"
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#include "disas.h"
32

    
33
/* XXX: move that elsewhere */
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static uint16_t *gen_opc_ptr;
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static uint32_t *gen_opparam_ptr;
36

    
37
#define PREFIX_REPZ   0x01
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#define PREFIX_REPNZ  0x02
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#define PREFIX_LOCK   0x04
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#define PREFIX_DATA   0x08
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#define PREFIX_ADR    0x10
42

    
43
typedef struct DisasContext {
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    /* current insn context */
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    int override; /* -1 if no override */
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    int prefix;
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    int aflag, dflag;
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    uint8_t *pc; /* pc = eip + cs_base */
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    int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
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                   static state change (stop translation) */
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    /* current block context */
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    uint8_t *cs_base; /* base of CS segment */
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    int pe;     /* protected mode */
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    int code32; /* 32 bit code segment */
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    int ss32;   /* 32 bit stack segment */
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    int cc_op;  /* current CC operation */
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    int addseg; /* non zero if either DS/ES/SS have a non zero base */
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    int f_st;   /* currently unused */
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    int vm86;   /* vm86 mode */
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    int cpl;
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    int iopl;
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    int tf;     /* TF cpu flag */
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    int singlestep_enabled; /* "hardware" single step enabled */
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    int jmp_opt; /* use direct block chaining for direct jumps */
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    int mem_index; /* select memory access functions */
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    struct TranslationBlock *tb;
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    int popl_esp_hack; /* for correct popl with esp base handling */
68
} DisasContext;
69

    
70
static void gen_eob(DisasContext *s);
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static void gen_jmp(DisasContext *s, unsigned int eip);
72

    
73
/* i386 arith/logic operations */
74
enum {
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    OP_ADDL, 
76
    OP_ORL, 
77
    OP_ADCL, 
78
    OP_SBBL,
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    OP_ANDL, 
80
    OP_SUBL, 
81
    OP_XORL, 
82
    OP_CMPL,
83
};
84

    
85
/* i386 shift ops */
86
enum {
87
    OP_ROL, 
88
    OP_ROR, 
89
    OP_RCL, 
90
    OP_RCR, 
91
    OP_SHL, 
92
    OP_SHR, 
93
    OP_SHL1, /* undocumented */
94
    OP_SAR = 7,
95
};
96

    
97
enum {
98
#define DEF(s, n, copy_size) INDEX_op_ ## s,
99
#include "opc.h"
100
#undef DEF
101
    NB_OPS,
102
};
103

    
104
#include "gen-op.h"
105

    
106
/* operand size */
107
enum {
108
    OT_BYTE = 0,
109
    OT_WORD,
110
    OT_LONG, 
111
    OT_QUAD,
112
};
113

    
114
enum {
115
    /* I386 int registers */
116
    OR_EAX,   /* MUST be even numbered */
117
    OR_ECX,
118
    OR_EDX,
119
    OR_EBX,
120
    OR_ESP,
121
    OR_EBP,
122
    OR_ESI,
123
    OR_EDI,
124
    OR_TMP0,    /* temporary operand register */
125
    OR_TMP1,
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    OR_A0, /* temporary register used when doing address evaluation */
127
    OR_ZERO, /* fixed zero register */
128
    NB_OREGS,
129
};
130

    
131
typedef void (GenOpFunc)(void);
132
typedef void (GenOpFunc1)(long);
133
typedef void (GenOpFunc2)(long, long);
134
typedef void (GenOpFunc3)(long, long, long);
135
                    
136
static GenOpFunc *gen_op_mov_reg_T0[3][8] = {
137
    [OT_BYTE] = {
138
        gen_op_movb_EAX_T0,
139
        gen_op_movb_ECX_T0,
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        gen_op_movb_EDX_T0,
141
        gen_op_movb_EBX_T0,
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        gen_op_movh_EAX_T0,
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        gen_op_movh_ECX_T0,
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        gen_op_movh_EDX_T0,
145
        gen_op_movh_EBX_T0,
146
    },
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    [OT_WORD] = {
148
        gen_op_movw_EAX_T0,
149
        gen_op_movw_ECX_T0,
150
        gen_op_movw_EDX_T0,
151
        gen_op_movw_EBX_T0,
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        gen_op_movw_ESP_T0,
153
        gen_op_movw_EBP_T0,
154
        gen_op_movw_ESI_T0,
155
        gen_op_movw_EDI_T0,
156
    },
157
    [OT_LONG] = {
158
        gen_op_movl_EAX_T0,
159
        gen_op_movl_ECX_T0,
160
        gen_op_movl_EDX_T0,
161
        gen_op_movl_EBX_T0,
162
        gen_op_movl_ESP_T0,
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        gen_op_movl_EBP_T0,
164
        gen_op_movl_ESI_T0,
165
        gen_op_movl_EDI_T0,
166
    },
167
};
168

    
169
static GenOpFunc *gen_op_mov_reg_T1[3][8] = {
170
    [OT_BYTE] = {
171
        gen_op_movb_EAX_T1,
172
        gen_op_movb_ECX_T1,
173
        gen_op_movb_EDX_T1,
174
        gen_op_movb_EBX_T1,
175
        gen_op_movh_EAX_T1,
176
        gen_op_movh_ECX_T1,
177
        gen_op_movh_EDX_T1,
178
        gen_op_movh_EBX_T1,
179
    },
180
    [OT_WORD] = {
181
        gen_op_movw_EAX_T1,
182
        gen_op_movw_ECX_T1,
183
        gen_op_movw_EDX_T1,
184
        gen_op_movw_EBX_T1,
185
        gen_op_movw_ESP_T1,
186
        gen_op_movw_EBP_T1,
187
        gen_op_movw_ESI_T1,
188
        gen_op_movw_EDI_T1,
189
    },
190
    [OT_LONG] = {
191
        gen_op_movl_EAX_T1,
192
        gen_op_movl_ECX_T1,
193
        gen_op_movl_EDX_T1,
194
        gen_op_movl_EBX_T1,
195
        gen_op_movl_ESP_T1,
196
        gen_op_movl_EBP_T1,
197
        gen_op_movl_ESI_T1,
198
        gen_op_movl_EDI_T1,
199
    },
200
};
201

    
202
static GenOpFunc *gen_op_mov_reg_A0[2][8] = {
203
    [0] = {
204
        gen_op_movw_EAX_A0,
205
        gen_op_movw_ECX_A0,
206
        gen_op_movw_EDX_A0,
207
        gen_op_movw_EBX_A0,
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        gen_op_movw_ESP_A0,
209
        gen_op_movw_EBP_A0,
210
        gen_op_movw_ESI_A0,
211
        gen_op_movw_EDI_A0,
212
    },
213
    [1] = {
214
        gen_op_movl_EAX_A0,
215
        gen_op_movl_ECX_A0,
216
        gen_op_movl_EDX_A0,
217
        gen_op_movl_EBX_A0,
218
        gen_op_movl_ESP_A0,
219
        gen_op_movl_EBP_A0,
220
        gen_op_movl_ESI_A0,
221
        gen_op_movl_EDI_A0,
222
    },
223
};
224

    
225
static GenOpFunc *gen_op_mov_TN_reg[3][2][8] = 
226
{
227
    [OT_BYTE] = {
228
        {
229
            gen_op_movl_T0_EAX,
230
            gen_op_movl_T0_ECX,
231
            gen_op_movl_T0_EDX,
232
            gen_op_movl_T0_EBX,
233
            gen_op_movh_T0_EAX,
234
            gen_op_movh_T0_ECX,
235
            gen_op_movh_T0_EDX,
236
            gen_op_movh_T0_EBX,
237
        },
238
        {
239
            gen_op_movl_T1_EAX,
240
            gen_op_movl_T1_ECX,
241
            gen_op_movl_T1_EDX,
242
            gen_op_movl_T1_EBX,
243
            gen_op_movh_T1_EAX,
244
            gen_op_movh_T1_ECX,
245
            gen_op_movh_T1_EDX,
246
            gen_op_movh_T1_EBX,
247
        },
248
    },
249
    [OT_WORD] = {
250
        {
251
            gen_op_movl_T0_EAX,
252
            gen_op_movl_T0_ECX,
253
            gen_op_movl_T0_EDX,
254
            gen_op_movl_T0_EBX,
255
            gen_op_movl_T0_ESP,
256
            gen_op_movl_T0_EBP,
257
            gen_op_movl_T0_ESI,
258
            gen_op_movl_T0_EDI,
259
        },
260
        {
261
            gen_op_movl_T1_EAX,
262
            gen_op_movl_T1_ECX,
263
            gen_op_movl_T1_EDX,
264
            gen_op_movl_T1_EBX,
265
            gen_op_movl_T1_ESP,
266
            gen_op_movl_T1_EBP,
267
            gen_op_movl_T1_ESI,
268
            gen_op_movl_T1_EDI,
269
        },
270
    },
271
    [OT_LONG] = {
272
        {
273
            gen_op_movl_T0_EAX,
274
            gen_op_movl_T0_ECX,
275
            gen_op_movl_T0_EDX,
276
            gen_op_movl_T0_EBX,
277
            gen_op_movl_T0_ESP,
278
            gen_op_movl_T0_EBP,
279
            gen_op_movl_T0_ESI,
280
            gen_op_movl_T0_EDI,
281
        },
282
        {
283
            gen_op_movl_T1_EAX,
284
            gen_op_movl_T1_ECX,
285
            gen_op_movl_T1_EDX,
286
            gen_op_movl_T1_EBX,
287
            gen_op_movl_T1_ESP,
288
            gen_op_movl_T1_EBP,
289
            gen_op_movl_T1_ESI,
290
            gen_op_movl_T1_EDI,
291
        },
292
    },
293
};
294

    
295
static GenOpFunc *gen_op_movl_A0_reg[8] = {
296
    gen_op_movl_A0_EAX,
297
    gen_op_movl_A0_ECX,
298
    gen_op_movl_A0_EDX,
299
    gen_op_movl_A0_EBX,
300
    gen_op_movl_A0_ESP,
301
    gen_op_movl_A0_EBP,
302
    gen_op_movl_A0_ESI,
303
    gen_op_movl_A0_EDI,
304
};
305

    
306
static GenOpFunc *gen_op_addl_A0_reg_sN[4][8] = {
307
    [0] = {
308
        gen_op_addl_A0_EAX,
309
        gen_op_addl_A0_ECX,
310
        gen_op_addl_A0_EDX,
311
        gen_op_addl_A0_EBX,
312
        gen_op_addl_A0_ESP,
313
        gen_op_addl_A0_EBP,
314
        gen_op_addl_A0_ESI,
315
        gen_op_addl_A0_EDI,
316
    },
317
    [1] = {
318
        gen_op_addl_A0_EAX_s1,
319
        gen_op_addl_A0_ECX_s1,
320
        gen_op_addl_A0_EDX_s1,
321
        gen_op_addl_A0_EBX_s1,
322
        gen_op_addl_A0_ESP_s1,
323
        gen_op_addl_A0_EBP_s1,
324
        gen_op_addl_A0_ESI_s1,
325
        gen_op_addl_A0_EDI_s1,
326
    },
327
    [2] = {
328
        gen_op_addl_A0_EAX_s2,
329
        gen_op_addl_A0_ECX_s2,
330
        gen_op_addl_A0_EDX_s2,
331
        gen_op_addl_A0_EBX_s2,
332
        gen_op_addl_A0_ESP_s2,
333
        gen_op_addl_A0_EBP_s2,
334
        gen_op_addl_A0_ESI_s2,
335
        gen_op_addl_A0_EDI_s2,
336
    },
337
    [3] = {
338
        gen_op_addl_A0_EAX_s3,
339
        gen_op_addl_A0_ECX_s3,
340
        gen_op_addl_A0_EDX_s3,
341
        gen_op_addl_A0_EBX_s3,
342
        gen_op_addl_A0_ESP_s3,
343
        gen_op_addl_A0_EBP_s3,
344
        gen_op_addl_A0_ESI_s3,
345
        gen_op_addl_A0_EDI_s3,
346
    },
347
};
348

    
349
static GenOpFunc *gen_op_cmov_reg_T1_T0[2][8] = {
350
    [0] = {
351
        gen_op_cmovw_EAX_T1_T0,
352
        gen_op_cmovw_ECX_T1_T0,
353
        gen_op_cmovw_EDX_T1_T0,
354
        gen_op_cmovw_EBX_T1_T0,
355
        gen_op_cmovw_ESP_T1_T0,
356
        gen_op_cmovw_EBP_T1_T0,
357
        gen_op_cmovw_ESI_T1_T0,
358
        gen_op_cmovw_EDI_T1_T0,
359
    },
360
    [1] = {
361
        gen_op_cmovl_EAX_T1_T0,
362
        gen_op_cmovl_ECX_T1_T0,
363
        gen_op_cmovl_EDX_T1_T0,
364
        gen_op_cmovl_EBX_T1_T0,
365
        gen_op_cmovl_ESP_T1_T0,
366
        gen_op_cmovl_EBP_T1_T0,
367
        gen_op_cmovl_ESI_T1_T0,
368
        gen_op_cmovl_EDI_T1_T0,
369
    },
370
};
371

    
372
static GenOpFunc *gen_op_arith_T0_T1_cc[8] = {
373
    NULL,
374
    gen_op_orl_T0_T1,
375
    NULL,
376
    NULL,
377
    gen_op_andl_T0_T1,
378
    NULL,
379
    gen_op_xorl_T0_T1,
380
    NULL,
381
};
382

    
383
static GenOpFunc *gen_op_arithc_T0_T1_cc[3][2] = {
384
    [OT_BYTE] = {
385
        gen_op_adcb_T0_T1_cc,
386
        gen_op_sbbb_T0_T1_cc,
387
    },
388
    [OT_WORD] = {
389
        gen_op_adcw_T0_T1_cc,
390
        gen_op_sbbw_T0_T1_cc,
391
    },
392
    [OT_LONG] = {
393
        gen_op_adcl_T0_T1_cc,
394
        gen_op_sbbl_T0_T1_cc,
395
    },
396
};
397

    
398
static GenOpFunc *gen_op_arithc_mem_T0_T1_cc[3][2] = {
399
    [OT_BYTE] = {
400
        gen_op_adcb_mem_T0_T1_cc,
401
        gen_op_sbbb_mem_T0_T1_cc,
402
    },
403
    [OT_WORD] = {
404
        gen_op_adcw_mem_T0_T1_cc,
405
        gen_op_sbbw_mem_T0_T1_cc,
406
    },
407
    [OT_LONG] = {
408
        gen_op_adcl_mem_T0_T1_cc,
409
        gen_op_sbbl_mem_T0_T1_cc,
410
    },
411
};
412

    
413
static const int cc_op_arithb[8] = {
414
    CC_OP_ADDB,
415
    CC_OP_LOGICB,
416
    CC_OP_ADDB,
417
    CC_OP_SUBB,
418
    CC_OP_LOGICB,
419
    CC_OP_SUBB,
420
    CC_OP_LOGICB,
421
    CC_OP_SUBB,
422
};
423

    
424
static GenOpFunc *gen_op_cmpxchg_T0_T1_EAX_cc[3] = {
425
    gen_op_cmpxchgb_T0_T1_EAX_cc,
426
    gen_op_cmpxchgw_T0_T1_EAX_cc,
427
    gen_op_cmpxchgl_T0_T1_EAX_cc,
428
};
429

    
430
static GenOpFunc *gen_op_cmpxchg_mem_T0_T1_EAX_cc[3] = {
431
    gen_op_cmpxchgb_mem_T0_T1_EAX_cc,
432
    gen_op_cmpxchgw_mem_T0_T1_EAX_cc,
433
    gen_op_cmpxchgl_mem_T0_T1_EAX_cc,
434
};
435

    
436
static GenOpFunc *gen_op_shift_T0_T1_cc[3][8] = {
437
    [OT_BYTE] = {
438
        gen_op_rolb_T0_T1_cc,
439
        gen_op_rorb_T0_T1_cc,
440
        gen_op_rclb_T0_T1_cc,
441
        gen_op_rcrb_T0_T1_cc,
442
        gen_op_shlb_T0_T1_cc,
443
        gen_op_shrb_T0_T1_cc,
444
        gen_op_shlb_T0_T1_cc,
445
        gen_op_sarb_T0_T1_cc,
446
    },
447
    [OT_WORD] = {
448
        gen_op_rolw_T0_T1_cc,
449
        gen_op_rorw_T0_T1_cc,
450
        gen_op_rclw_T0_T1_cc,
451
        gen_op_rcrw_T0_T1_cc,
452
        gen_op_shlw_T0_T1_cc,
453
        gen_op_shrw_T0_T1_cc,
454
        gen_op_shlw_T0_T1_cc,
455
        gen_op_sarw_T0_T1_cc,
456
    },
457
    [OT_LONG] = {
458
        gen_op_roll_T0_T1_cc,
459
        gen_op_rorl_T0_T1_cc,
460
        gen_op_rcll_T0_T1_cc,
461
        gen_op_rcrl_T0_T1_cc,
462
        gen_op_shll_T0_T1_cc,
463
        gen_op_shrl_T0_T1_cc,
464
        gen_op_shll_T0_T1_cc,
465
        gen_op_sarl_T0_T1_cc,
466
    },
467
};
468

    
469
static GenOpFunc *gen_op_shift_mem_T0_T1_cc[3][8] = {
470
    [OT_BYTE] = {
471
        gen_op_rolb_mem_T0_T1_cc,
472
        gen_op_rorb_mem_T0_T1_cc,
473
        gen_op_rclb_mem_T0_T1_cc,
474
        gen_op_rcrb_mem_T0_T1_cc,
475
        gen_op_shlb_mem_T0_T1_cc,
476
        gen_op_shrb_mem_T0_T1_cc,
477
        gen_op_shlb_mem_T0_T1_cc,
478
        gen_op_sarb_mem_T0_T1_cc,
479
    },
480
    [OT_WORD] = {
481
        gen_op_rolw_mem_T0_T1_cc,
482
        gen_op_rorw_mem_T0_T1_cc,
483
        gen_op_rclw_mem_T0_T1_cc,
484
        gen_op_rcrw_mem_T0_T1_cc,
485
        gen_op_shlw_mem_T0_T1_cc,
486
        gen_op_shrw_mem_T0_T1_cc,
487
        gen_op_shlw_mem_T0_T1_cc,
488
        gen_op_sarw_mem_T0_T1_cc,
489
    },
490
    [OT_LONG] = {
491
        gen_op_roll_mem_T0_T1_cc,
492
        gen_op_rorl_mem_T0_T1_cc,
493
        gen_op_rcll_mem_T0_T1_cc,
494
        gen_op_rcrl_mem_T0_T1_cc,
495
        gen_op_shll_mem_T0_T1_cc,
496
        gen_op_shrl_mem_T0_T1_cc,
497
        gen_op_shll_mem_T0_T1_cc,
498
        gen_op_sarl_mem_T0_T1_cc,
499
    },
500
};
501

    
502
static GenOpFunc1 *gen_op_shiftd_T0_T1_im_cc[2][2] = {
503
    [0] = {
504
        gen_op_shldw_T0_T1_im_cc,
505
        gen_op_shrdw_T0_T1_im_cc,
506
    },
507
    [1] = {
508
        gen_op_shldl_T0_T1_im_cc,
509
        gen_op_shrdl_T0_T1_im_cc,
510
    },
511
};
512

    
513
static GenOpFunc *gen_op_shiftd_T0_T1_ECX_cc[2][2] = {
514
    [0] = {
515
        gen_op_shldw_T0_T1_ECX_cc,
516
        gen_op_shrdw_T0_T1_ECX_cc,
517
    },
518
    [1] = {
519
        gen_op_shldl_T0_T1_ECX_cc,
520
        gen_op_shrdl_T0_T1_ECX_cc,
521
    },
522
};
523

    
524
static GenOpFunc1 *gen_op_shiftd_mem_T0_T1_im_cc[2][2] = {
525
    [0] = {
526
        gen_op_shldw_mem_T0_T1_im_cc,
527
        gen_op_shrdw_mem_T0_T1_im_cc,
528
    },
529
    [1] = {
530
        gen_op_shldl_mem_T0_T1_im_cc,
531
        gen_op_shrdl_mem_T0_T1_im_cc,
532
    },
533
};
534

    
535
static GenOpFunc *gen_op_shiftd_mem_T0_T1_ECX_cc[2][2] = {
536
    [0] = {
537
        gen_op_shldw_mem_T0_T1_ECX_cc,
538
        gen_op_shrdw_mem_T0_T1_ECX_cc,
539
    },
540
    [1] = {
541
        gen_op_shldl_mem_T0_T1_ECX_cc,
542
        gen_op_shrdl_mem_T0_T1_ECX_cc,
543
    },
544
};
545

    
546
static GenOpFunc *gen_op_btx_T0_T1_cc[2][4] = {
547
    [0] = {
548
        gen_op_btw_T0_T1_cc,
549
        gen_op_btsw_T0_T1_cc,
550
        gen_op_btrw_T0_T1_cc,
551
        gen_op_btcw_T0_T1_cc,
552
    },
553
    [1] = {
554
        gen_op_btl_T0_T1_cc,
555
        gen_op_btsl_T0_T1_cc,
556
        gen_op_btrl_T0_T1_cc,
557
        gen_op_btcl_T0_T1_cc,
558
    },
559
};
560

    
561
static GenOpFunc *gen_op_bsx_T0_cc[2][2] = {
562
    [0] = {
563
        gen_op_bsfw_T0_cc,
564
        gen_op_bsrw_T0_cc,
565
    },
566
    [1] = {
567
        gen_op_bsfl_T0_cc,
568
        gen_op_bsrl_T0_cc,
569
    },
570
};
571

    
572
static GenOpFunc *gen_op_lds_T0_A0[3 * 3] = {
573
    gen_op_ldsb_raw_T0_A0,
574
    gen_op_ldsw_raw_T0_A0,
575
    NULL,
576
#ifndef CONFIG_USER_ONLY
577
    gen_op_ldsb_kernel_T0_A0,
578
    gen_op_ldsw_kernel_T0_A0,
579
    NULL,
580

    
581
    gen_op_ldsb_user_T0_A0,
582
    gen_op_ldsw_user_T0_A0,
583
    NULL,
584
#endif
585
};
586

    
587
static GenOpFunc *gen_op_ldu_T0_A0[3 * 3] = {
588
    gen_op_ldub_raw_T0_A0,
589
    gen_op_lduw_raw_T0_A0,
590
    NULL,
591

    
592
#ifndef CONFIG_USER_ONLY
593
    gen_op_ldub_kernel_T0_A0,
594
    gen_op_lduw_kernel_T0_A0,
595
    NULL,
596

    
597
    gen_op_ldub_user_T0_A0,
598
    gen_op_lduw_user_T0_A0,
599
    NULL,
600
#endif
601
};
602

    
603
/* sign does not matter, except for lidt/lgdt call (TODO: fix it) */
604
static GenOpFunc *gen_op_ld_T0_A0[3 * 3] = {
605
    gen_op_ldub_raw_T0_A0,
606
    gen_op_lduw_raw_T0_A0,
607
    gen_op_ldl_raw_T0_A0,
608

    
609
#ifndef CONFIG_USER_ONLY
610
    gen_op_ldub_kernel_T0_A0,
611
    gen_op_lduw_kernel_T0_A0,
612
    gen_op_ldl_kernel_T0_A0,
613

    
614
    gen_op_ldub_user_T0_A0,
615
    gen_op_lduw_user_T0_A0,
616
    gen_op_ldl_user_T0_A0,
617
#endif
618
};
619

    
620
static GenOpFunc *gen_op_ld_T1_A0[3 * 3] = {
621
    gen_op_ldub_raw_T1_A0,
622
    gen_op_lduw_raw_T1_A0,
623
    gen_op_ldl_raw_T1_A0,
624

    
625
#ifndef CONFIG_USER_ONLY
626
    gen_op_ldub_kernel_T1_A0,
627
    gen_op_lduw_kernel_T1_A0,
628
    gen_op_ldl_kernel_T1_A0,
629

    
630
    gen_op_ldub_user_T1_A0,
631
    gen_op_lduw_user_T1_A0,
632
    gen_op_ldl_user_T1_A0,
633
#endif
634
};
635

    
636
static GenOpFunc *gen_op_st_T0_A0[3 * 3] = {
637
    gen_op_stb_raw_T0_A0,
638
    gen_op_stw_raw_T0_A0,
639
    gen_op_stl_raw_T0_A0,
640

    
641
#ifndef CONFIG_USER_ONLY
642
    gen_op_stb_kernel_T0_A0,
643
    gen_op_stw_kernel_T0_A0,
644
    gen_op_stl_kernel_T0_A0,
645

    
646
    gen_op_stb_user_T0_A0,
647
    gen_op_stw_user_T0_A0,
648
    gen_op_stl_user_T0_A0,
649
#endif
650
};
651

    
652
static inline void gen_string_movl_A0_ESI(DisasContext *s)
653
{
654
    int override;
655

    
656
    override = s->override;
657
    if (s->aflag) {
658
        /* 32 bit address */
659
        if (s->addseg && override < 0)
660
            override = R_DS;
661
        if (override >= 0) {
662
            gen_op_movl_A0_seg(offsetof(CPUX86State,segs[override].base));
663
            gen_op_addl_A0_reg_sN[0][R_ESI]();
664
        } else {
665
            gen_op_movl_A0_reg[R_ESI]();
666
        }
667
    } else {
668
        /* 16 address, always override */
669
        if (override < 0)
670
            override = R_DS;
671
        gen_op_movl_A0_reg[R_ESI]();
672
        gen_op_andl_A0_ffff();
673
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
674
    }
675
}
676

    
677
static inline void gen_string_movl_A0_EDI(DisasContext *s)
678
{
679
    if (s->aflag) {
680
        if (s->addseg) {
681
            gen_op_movl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
682
            gen_op_addl_A0_reg_sN[0][R_EDI]();
683
        } else {
684
            gen_op_movl_A0_reg[R_EDI]();
685
        }
686
    } else {
687
        gen_op_movl_A0_reg[R_EDI]();
688
        gen_op_andl_A0_ffff();
689
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_ES].base));
690
    }
691
}
692

    
693
static GenOpFunc *gen_op_movl_T0_Dshift[3] = {
694
    gen_op_movl_T0_Dshiftb,
695
    gen_op_movl_T0_Dshiftw,
696
    gen_op_movl_T0_Dshiftl,
697
};
698

    
699
static GenOpFunc2 *gen_op_jz_ecx[2] = {
700
    gen_op_jz_ecxw,
701
    gen_op_jz_ecxl,
702
};
703
    
704
static GenOpFunc1 *gen_op_jz_ecx_im[2] = {
705
    gen_op_jz_ecxw_im,
706
    gen_op_jz_ecxl_im,
707
};
708

    
709
static GenOpFunc *gen_op_dec_ECX[2] = {
710
    gen_op_decw_ECX,
711
    gen_op_decl_ECX,
712
};
713

    
714
static GenOpFunc1 *gen_op_string_jnz_sub[2][3] = {
715
    {
716
        gen_op_string_jnz_subb,
717
        gen_op_string_jnz_subw,
718
        gen_op_string_jnz_subl,
719
    },
720
    {
721
        gen_op_string_jz_subb,
722
        gen_op_string_jz_subw,
723
        gen_op_string_jz_subl,
724
    },
725
};
726

    
727
static GenOpFunc1 *gen_op_string_jnz_sub_im[2][3] = {
728
    {
729
        gen_op_string_jnz_subb_im,
730
        gen_op_string_jnz_subw_im,
731
        gen_op_string_jnz_subl_im,
732
    },
733
    {
734
        gen_op_string_jz_subb_im,
735
        gen_op_string_jz_subw_im,
736
        gen_op_string_jz_subl_im,
737
    },
738
};
739

    
740
static GenOpFunc *gen_op_in_DX_T0[3] = {
741
    gen_op_inb_DX_T0,
742
    gen_op_inw_DX_T0,
743
    gen_op_inl_DX_T0,
744
};
745

    
746
static GenOpFunc *gen_op_out_DX_T0[3] = {
747
    gen_op_outb_DX_T0,
748
    gen_op_outw_DX_T0,
749
    gen_op_outl_DX_T0,
750
};
751

    
752
static GenOpFunc *gen_op_in[3] = {
753
    gen_op_inb_T0_T1,
754
    gen_op_inw_T0_T1,
755
    gen_op_inl_T0_T1,
756
};
757

    
758
static GenOpFunc *gen_op_out[3] = {
759
    gen_op_outb_T0_T1,
760
    gen_op_outw_T0_T1,
761
    gen_op_outl_T0_T1,
762
};
763

    
764
static GenOpFunc *gen_check_io_T0[3] = {
765
    gen_op_check_iob_T0,
766
    gen_op_check_iow_T0,
767
    gen_op_check_iol_T0,
768
};
769

    
770
static GenOpFunc *gen_check_io_DX[3] = {
771
    gen_op_check_iob_DX,
772
    gen_op_check_iow_DX,
773
    gen_op_check_iol_DX,
774
};
775

    
776
static void gen_check_io(DisasContext *s, int ot, int use_dx, int cur_eip)
777
{
778
    if (s->pe && (s->cpl > s->iopl || s->vm86)) {
779
        if (s->cc_op != CC_OP_DYNAMIC)
780
            gen_op_set_cc_op(s->cc_op);
781
        gen_op_jmp_im(cur_eip);
782
        if (use_dx)
783
            gen_check_io_DX[ot]();
784
        else
785
            gen_check_io_T0[ot]();
786
    }
787
}
788

    
789
static inline void gen_movs(DisasContext *s, int ot)
790
{
791
    gen_string_movl_A0_ESI(s);
792
    gen_op_ld_T0_A0[ot + s->mem_index]();
793
    gen_string_movl_A0_EDI(s);
794
    gen_op_st_T0_A0[ot + s->mem_index]();
795
    gen_op_movl_T0_Dshift[ot]();
796
    if (s->aflag) {
797
        gen_op_addl_ESI_T0();
798
        gen_op_addl_EDI_T0();
799
    } else {
800
        gen_op_addw_ESI_T0();
801
        gen_op_addw_EDI_T0();
802
    }
803
}
804

    
805
static inline void gen_update_cc_op(DisasContext *s)
806
{
807
    if (s->cc_op != CC_OP_DYNAMIC) {
808
        gen_op_set_cc_op(s->cc_op);
809
        s->cc_op = CC_OP_DYNAMIC;
810
    }
811
}
812

    
813
static inline void gen_jz_ecx_string(DisasContext *s, unsigned int next_eip)
814
{
815
    if (s->jmp_opt) {
816
        gen_op_jz_ecx[s->aflag]((long)s->tb, next_eip);
817
    } else {
818
        /* XXX: does not work with gdbstub "ice" single step - not a
819
           serious problem */
820
        gen_op_jz_ecx_im[s->aflag](next_eip);
821
    }
822
}
823

    
824
static inline void gen_stos(DisasContext *s, int ot)
825
{
826
    gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
827
    gen_string_movl_A0_EDI(s);
828
    gen_op_st_T0_A0[ot + s->mem_index]();
829
    gen_op_movl_T0_Dshift[ot]();
830
    if (s->aflag) {
831
        gen_op_addl_EDI_T0();
832
    } else {
833
        gen_op_addw_EDI_T0();
834
    }
835
}
836

    
837
static inline void gen_lods(DisasContext *s, int ot)
838
{
839
    gen_string_movl_A0_ESI(s);
840
    gen_op_ld_T0_A0[ot + s->mem_index]();
841
    gen_op_mov_reg_T0[ot][R_EAX]();
842
    gen_op_movl_T0_Dshift[ot]();
843
    if (s->aflag) {
844
        gen_op_addl_ESI_T0();
845
    } else {
846
        gen_op_addw_ESI_T0();
847
    }
848
}
849

    
850
static inline void gen_scas(DisasContext *s, int ot)
851
{
852
    gen_op_mov_TN_reg[OT_LONG][0][R_EAX]();
853
    gen_string_movl_A0_EDI(s);
854
    gen_op_ld_T1_A0[ot + s->mem_index]();
855
    gen_op_cmpl_T0_T1_cc();
856
    gen_op_movl_T0_Dshift[ot]();
857
    if (s->aflag) {
858
        gen_op_addl_EDI_T0();
859
    } else {
860
        gen_op_addw_EDI_T0();
861
    }
862
}
863

    
864
static inline void gen_cmps(DisasContext *s, int ot)
865
{
866
    gen_string_movl_A0_ESI(s);
867
    gen_op_ld_T0_A0[ot + s->mem_index]();
868
    gen_string_movl_A0_EDI(s);
869
    gen_op_ld_T1_A0[ot + s->mem_index]();
870
    gen_op_cmpl_T0_T1_cc();
871
    gen_op_movl_T0_Dshift[ot]();
872
    if (s->aflag) {
873
        gen_op_addl_ESI_T0();
874
        gen_op_addl_EDI_T0();
875
    } else {
876
        gen_op_addw_ESI_T0();
877
        gen_op_addw_EDI_T0();
878
    }
879
}
880

    
881
static inline void gen_ins(DisasContext *s, int ot)
882
{
883
    gen_op_in_DX_T0[ot]();
884
    gen_string_movl_A0_EDI(s);
885
    gen_op_st_T0_A0[ot + s->mem_index]();
886
    gen_op_movl_T0_Dshift[ot]();
887
    if (s->aflag) {
888
        gen_op_addl_EDI_T0();
889
    } else {
890
        gen_op_addw_EDI_T0();
891
    }
892
}
893

    
894
static inline void gen_outs(DisasContext *s, int ot)
895
{
896
    gen_string_movl_A0_ESI(s);
897
    gen_op_ld_T0_A0[ot + s->mem_index]();
898
    gen_op_out_DX_T0[ot]();
899
    gen_op_movl_T0_Dshift[ot]();
900
    if (s->aflag) {
901
        gen_op_addl_ESI_T0();
902
    } else {
903
        gen_op_addw_ESI_T0();
904
    }
905
}
906

    
907
/* same method as Valgrind : we generate jumps to current or next
908
   instruction */
909
#define GEN_REPZ(op)                                                          \
910
static inline void gen_repz_ ## op(DisasContext *s, int ot,                   \
911
                                 unsigned int cur_eip, unsigned int next_eip) \
912
{                                                                             \
913
    gen_update_cc_op(s);                                                      \
914
    gen_jz_ecx_string(s, next_eip);                                           \
915
    gen_ ## op(s, ot);                                                        \
916
    gen_op_dec_ECX[s->aflag]();                                               \
917
    /* a loop would cause two single step exceptions if ECX = 1               \
918
       before rep string_insn */                                              \
919
    if (!s->jmp_opt)                                                          \
920
        gen_op_jz_ecx_im[s->aflag](next_eip);                                 \
921
    gen_jmp(s, cur_eip);                                                      \
922
}
923

    
924
#define GEN_REPZ2(op)                                                         \
925
static inline void gen_repz_ ## op(DisasContext *s, int ot,                   \
926
                                   unsigned int cur_eip,                      \
927
                                   unsigned int next_eip,                     \
928
                                   int nz)                                    \
929
{                                                                             \
930
    gen_update_cc_op(s);                                                      \
931
    gen_jz_ecx_string(s, next_eip);                                           \
932
    gen_ ## op(s, ot);                                                        \
933
    gen_op_dec_ECX[s->aflag]();                                               \
934
    gen_op_set_cc_op(CC_OP_SUBB + ot);                                        \
935
    if (!s->jmp_opt)                                                          \
936
        gen_op_string_jnz_sub_im[nz][ot](next_eip);                           \
937
    else                                                                      \
938
        gen_op_string_jnz_sub[nz][ot]((long)s->tb);                           \
939
    if (!s->jmp_opt)                                                          \
940
        gen_op_jz_ecx_im[s->aflag](next_eip);                                 \
941
    gen_jmp(s, cur_eip);                                                      \
942
}
943

    
944
GEN_REPZ(movs)
945
GEN_REPZ(stos)
946
GEN_REPZ(lods)
947
GEN_REPZ(ins)
948
GEN_REPZ(outs)
949
GEN_REPZ2(scas)
950
GEN_REPZ2(cmps)
951

    
952
enum {
953
    JCC_O,
954
    JCC_B,
955
    JCC_Z,
956
    JCC_BE,
957
    JCC_S,
958
    JCC_P,
959
    JCC_L,
960
    JCC_LE,
961
};
962

    
963
static GenOpFunc3 *gen_jcc_sub[3][8] = {
964
    [OT_BYTE] = {
965
        NULL,
966
        gen_op_jb_subb,
967
        gen_op_jz_subb,
968
        gen_op_jbe_subb,
969
        gen_op_js_subb,
970
        NULL,
971
        gen_op_jl_subb,
972
        gen_op_jle_subb,
973
    },
974
    [OT_WORD] = {
975
        NULL,
976
        gen_op_jb_subw,
977
        gen_op_jz_subw,
978
        gen_op_jbe_subw,
979
        gen_op_js_subw,
980
        NULL,
981
        gen_op_jl_subw,
982
        gen_op_jle_subw,
983
    },
984
    [OT_LONG] = {
985
        NULL,
986
        gen_op_jb_subl,
987
        gen_op_jz_subl,
988
        gen_op_jbe_subl,
989
        gen_op_js_subl,
990
        NULL,
991
        gen_op_jl_subl,
992
        gen_op_jle_subl,
993
    },
994
};
995
static GenOpFunc2 *gen_op_loop[2][4] = {
996
    [0] = {
997
        gen_op_loopnzw,
998
        gen_op_loopzw,
999
        gen_op_loopw,
1000
        gen_op_jecxzw,
1001
    },
1002
    [1] = {
1003
        gen_op_loopnzl,
1004
        gen_op_loopzl,
1005
        gen_op_loopl,
1006
        gen_op_jecxzl,
1007
    },
1008
};
1009

    
1010
static GenOpFunc *gen_setcc_slow[8] = {
1011
    gen_op_seto_T0_cc,
1012
    gen_op_setb_T0_cc,
1013
    gen_op_setz_T0_cc,
1014
    gen_op_setbe_T0_cc,
1015
    gen_op_sets_T0_cc,
1016
    gen_op_setp_T0_cc,
1017
    gen_op_setl_T0_cc,
1018
    gen_op_setle_T0_cc,
1019
};
1020

    
1021
static GenOpFunc *gen_setcc_sub[3][8] = {
1022
    [OT_BYTE] = {
1023
        NULL,
1024
        gen_op_setb_T0_subb,
1025
        gen_op_setz_T0_subb,
1026
        gen_op_setbe_T0_subb,
1027
        gen_op_sets_T0_subb,
1028
        NULL,
1029
        gen_op_setl_T0_subb,
1030
        gen_op_setle_T0_subb,
1031
    },
1032
    [OT_WORD] = {
1033
        NULL,
1034
        gen_op_setb_T0_subw,
1035
        gen_op_setz_T0_subw,
1036
        gen_op_setbe_T0_subw,
1037
        gen_op_sets_T0_subw,
1038
        NULL,
1039
        gen_op_setl_T0_subw,
1040
        gen_op_setle_T0_subw,
1041
    },
1042
    [OT_LONG] = {
1043
        NULL,
1044
        gen_op_setb_T0_subl,
1045
        gen_op_setz_T0_subl,
1046
        gen_op_setbe_T0_subl,
1047
        gen_op_sets_T0_subl,
1048
        NULL,
1049
        gen_op_setl_T0_subl,
1050
        gen_op_setle_T0_subl,
1051
    },
1052
};
1053

    
1054
static GenOpFunc *gen_op_fp_arith_ST0_FT0[8] = {
1055
    gen_op_fadd_ST0_FT0,
1056
    gen_op_fmul_ST0_FT0,
1057
    gen_op_fcom_ST0_FT0,
1058
    gen_op_fcom_ST0_FT0,
1059
    gen_op_fsub_ST0_FT0,
1060
    gen_op_fsubr_ST0_FT0,
1061
    gen_op_fdiv_ST0_FT0,
1062
    gen_op_fdivr_ST0_FT0,
1063
};
1064

    
1065
/* NOTE the exception in "r" op ordering */
1066
static GenOpFunc1 *gen_op_fp_arith_STN_ST0[8] = {
1067
    gen_op_fadd_STN_ST0,
1068
    gen_op_fmul_STN_ST0,
1069
    NULL,
1070
    NULL,
1071
    gen_op_fsubr_STN_ST0,
1072
    gen_op_fsub_STN_ST0,
1073
    gen_op_fdivr_STN_ST0,
1074
    gen_op_fdiv_STN_ST0,
1075
};
1076

    
1077
/* if d == OR_TMP0, it means memory operand (address in A0) */
1078
static void gen_op(DisasContext *s1, int op, int ot, int d)
1079
{
1080
    GenOpFunc *gen_update_cc;
1081
    
1082
    if (d != OR_TMP0) {
1083
        gen_op_mov_TN_reg[ot][0][d]();
1084
    } else {
1085
        gen_op_ld_T0_A0[ot + s1->mem_index]();
1086
    }
1087
    switch(op) {
1088
    case OP_ADCL:
1089
    case OP_SBBL:
1090
        if (s1->cc_op != CC_OP_DYNAMIC)
1091
            gen_op_set_cc_op(s1->cc_op);
1092
        if (d != OR_TMP0) {
1093
            gen_op_arithc_T0_T1_cc[ot][op - OP_ADCL]();
1094
            gen_op_mov_reg_T0[ot][d]();
1095
        } else {
1096
            gen_op_arithc_mem_T0_T1_cc[ot][op - OP_ADCL]();
1097
        }
1098
        s1->cc_op = CC_OP_DYNAMIC;
1099
        goto the_end;
1100
    case OP_ADDL:
1101
        gen_op_addl_T0_T1();
1102
        s1->cc_op = CC_OP_ADDB + ot;
1103
        gen_update_cc = gen_op_update2_cc;
1104
        break;
1105
    case OP_SUBL:
1106
        gen_op_subl_T0_T1();
1107
        s1->cc_op = CC_OP_SUBB + ot;
1108
        gen_update_cc = gen_op_update2_cc;
1109
        break;
1110
    default:
1111
    case OP_ANDL:
1112
    case OP_ORL:
1113
    case OP_XORL:
1114
        gen_op_arith_T0_T1_cc[op]();
1115
        s1->cc_op = CC_OP_LOGICB + ot;
1116
        gen_update_cc = gen_op_update1_cc;
1117
        break;
1118
    case OP_CMPL:
1119
        gen_op_cmpl_T0_T1_cc();
1120
        s1->cc_op = CC_OP_SUBB + ot;
1121
        gen_update_cc = NULL;
1122
        break;
1123
    }
1124
    if (op != OP_CMPL) {
1125
        if (d != OR_TMP0)
1126
            gen_op_mov_reg_T0[ot][d]();
1127
        else
1128
            gen_op_st_T0_A0[ot + s1->mem_index]();
1129
    }
1130
    /* the flags update must happen after the memory write (precise
1131
       exception support) */
1132
    if (gen_update_cc)
1133
        gen_update_cc();
1134
 the_end: ;
1135
}
1136

    
1137
/* if d == OR_TMP0, it means memory operand (address in A0) */
1138
static void gen_inc(DisasContext *s1, int ot, int d, int c)
1139
{
1140
    if (d != OR_TMP0)
1141
        gen_op_mov_TN_reg[ot][0][d]();
1142
    else
1143
        gen_op_ld_T0_A0[ot + s1->mem_index]();
1144
    if (s1->cc_op != CC_OP_DYNAMIC)
1145
        gen_op_set_cc_op(s1->cc_op);
1146
    if (c > 0) {
1147
        gen_op_incl_T0();
1148
        s1->cc_op = CC_OP_INCB + ot;
1149
    } else {
1150
        gen_op_decl_T0();
1151
        s1->cc_op = CC_OP_DECB + ot;
1152
    }
1153
    if (d != OR_TMP0)
1154
        gen_op_mov_reg_T0[ot][d]();
1155
    else
1156
        gen_op_st_T0_A0[ot + s1->mem_index]();
1157
    gen_op_update_inc_cc();
1158
}
1159

    
1160
static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1161
{
1162
    if (d != OR_TMP0)
1163
        gen_op_mov_TN_reg[ot][0][d]();
1164
    else
1165
        gen_op_ld_T0_A0[ot + s1->mem_index]();
1166
    if (s != OR_TMP1)
1167
        gen_op_mov_TN_reg[ot][1][s]();
1168
    /* for zero counts, flags are not updated, so must do it dynamically */
1169
    if (s1->cc_op != CC_OP_DYNAMIC)
1170
        gen_op_set_cc_op(s1->cc_op);
1171
    
1172
    if (d != OR_TMP0)
1173
        gen_op_shift_T0_T1_cc[ot][op]();
1174
    else
1175
        gen_op_shift_mem_T0_T1_cc[ot][op]();
1176
    if (d != OR_TMP0)
1177
        gen_op_mov_reg_T0[ot][d]();
1178
    s1->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1179
}
1180

    
1181
static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1182
{
1183
    /* currently not optimized */
1184
    gen_op_movl_T1_im(c);
1185
    gen_shift(s1, op, ot, d, OR_TMP1);
1186
}
1187

    
1188
static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
1189
{
1190
    int havesib;
1191
    int base, disp;
1192
    int index;
1193
    int scale;
1194
    int opreg;
1195
    int mod, rm, code, override, must_add_seg;
1196

    
1197
    override = s->override;
1198
    must_add_seg = s->addseg;
1199
    if (override >= 0)
1200
        must_add_seg = 1;
1201
    mod = (modrm >> 6) & 3;
1202
    rm = modrm & 7;
1203

    
1204
    if (s->aflag) {
1205

    
1206
        havesib = 0;
1207
        base = rm;
1208
        index = 0;
1209
        scale = 0;
1210
        
1211
        if (base == 4) {
1212
            havesib = 1;
1213
            code = ldub_code(s->pc++);
1214
            scale = (code >> 6) & 3;
1215
            index = (code >> 3) & 7;
1216
            base = code & 7;
1217
        }
1218

    
1219
        switch (mod) {
1220
        case 0:
1221
            if (base == 5) {
1222
                base = -1;
1223
                disp = ldl_code(s->pc);
1224
                s->pc += 4;
1225
            } else {
1226
                disp = 0;
1227
            }
1228
            break;
1229
        case 1:
1230
            disp = (int8_t)ldub_code(s->pc++);
1231
            break;
1232
        default:
1233
        case 2:
1234
            disp = ldl_code(s->pc);
1235
            s->pc += 4;
1236
            break;
1237
        }
1238
        
1239
        if (base >= 0) {
1240
            /* for correct popl handling with esp */
1241
            if (base == 4 && s->popl_esp_hack)
1242
                disp += s->popl_esp_hack;
1243
            gen_op_movl_A0_reg[base]();
1244
            if (disp != 0)
1245
                gen_op_addl_A0_im(disp);
1246
        } else {
1247
            gen_op_movl_A0_im(disp);
1248
        }
1249
        /* XXX: index == 4 is always invalid */
1250
        if (havesib && (index != 4 || scale != 0)) {
1251
            gen_op_addl_A0_reg_sN[scale][index]();
1252
        }
1253
        if (must_add_seg) {
1254
            if (override < 0) {
1255
                if (base == R_EBP || base == R_ESP)
1256
                    override = R_SS;
1257
                else
1258
                    override = R_DS;
1259
            }
1260
            gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1261
        }
1262
    } else {
1263
        switch (mod) {
1264
        case 0:
1265
            if (rm == 6) {
1266
                disp = lduw_code(s->pc);
1267
                s->pc += 2;
1268
                gen_op_movl_A0_im(disp);
1269
                rm = 0; /* avoid SS override */
1270
                goto no_rm;
1271
            } else {
1272
                disp = 0;
1273
            }
1274
            break;
1275
        case 1:
1276
            disp = (int8_t)ldub_code(s->pc++);
1277
            break;
1278
        default:
1279
        case 2:
1280
            disp = lduw_code(s->pc);
1281
            s->pc += 2;
1282
            break;
1283
        }
1284
        switch(rm) {
1285
        case 0:
1286
            gen_op_movl_A0_reg[R_EBX]();
1287
            gen_op_addl_A0_reg_sN[0][R_ESI]();
1288
            break;
1289
        case 1:
1290
            gen_op_movl_A0_reg[R_EBX]();
1291
            gen_op_addl_A0_reg_sN[0][R_EDI]();
1292
            break;
1293
        case 2:
1294
            gen_op_movl_A0_reg[R_EBP]();
1295
            gen_op_addl_A0_reg_sN[0][R_ESI]();
1296
            break;
1297
        case 3:
1298
            gen_op_movl_A0_reg[R_EBP]();
1299
            gen_op_addl_A0_reg_sN[0][R_EDI]();
1300
            break;
1301
        case 4:
1302
            gen_op_movl_A0_reg[R_ESI]();
1303
            break;
1304
        case 5:
1305
            gen_op_movl_A0_reg[R_EDI]();
1306
            break;
1307
        case 6:
1308
            gen_op_movl_A0_reg[R_EBP]();
1309
            break;
1310
        default:
1311
        case 7:
1312
            gen_op_movl_A0_reg[R_EBX]();
1313
            break;
1314
        }
1315
        if (disp != 0)
1316
            gen_op_addl_A0_im(disp);
1317
        gen_op_andl_A0_ffff();
1318
    no_rm:
1319
        if (must_add_seg) {
1320
            if (override < 0) {
1321
                if (rm == 2 || rm == 3 || rm == 6)
1322
                    override = R_SS;
1323
                else
1324
                    override = R_DS;
1325
            }
1326
            gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
1327
        }
1328
    }
1329

    
1330
    opreg = OR_A0;
1331
    disp = 0;
1332
    *reg_ptr = opreg;
1333
    *offset_ptr = disp;
1334
}
1335

    
1336
/* generate modrm memory load or store of 'reg'. TMP0 is used if reg !=
1337
   OR_TMP0 */
1338
static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
1339
{
1340
    int mod, rm, opreg, disp;
1341

    
1342
    mod = (modrm >> 6) & 3;
1343
    rm = modrm & 7;
1344
    if (mod == 3) {
1345
        if (is_store) {
1346
            if (reg != OR_TMP0)
1347
                gen_op_mov_TN_reg[ot][0][reg]();
1348
            gen_op_mov_reg_T0[ot][rm]();
1349
        } else {
1350
            gen_op_mov_TN_reg[ot][0][rm]();
1351
            if (reg != OR_TMP0)
1352
                gen_op_mov_reg_T0[ot][reg]();
1353
        }
1354
    } else {
1355
        gen_lea_modrm(s, modrm, &opreg, &disp);
1356
        if (is_store) {
1357
            if (reg != OR_TMP0)
1358
                gen_op_mov_TN_reg[ot][0][reg]();
1359
            gen_op_st_T0_A0[ot + s->mem_index]();
1360
        } else {
1361
            gen_op_ld_T0_A0[ot + s->mem_index]();
1362
            if (reg != OR_TMP0)
1363
                gen_op_mov_reg_T0[ot][reg]();
1364
        }
1365
    }
1366
}
1367

    
1368
static inline uint32_t insn_get(DisasContext *s, int ot)
1369
{
1370
    uint32_t ret;
1371

    
1372
    switch(ot) {
1373
    case OT_BYTE:
1374
        ret = ldub_code(s->pc);
1375
        s->pc++;
1376
        break;
1377
    case OT_WORD:
1378
        ret = lduw_code(s->pc);
1379
        s->pc += 2;
1380
        break;
1381
    default:
1382
    case OT_LONG:
1383
        ret = ldl_code(s->pc);
1384
        s->pc += 4;
1385
        break;
1386
    }
1387
    return ret;
1388
}
1389

    
1390
static inline void gen_jcc(DisasContext *s, int b, int val, int next_eip)
1391
{
1392
    TranslationBlock *tb;
1393
    int inv, jcc_op;
1394
    GenOpFunc3 *func;
1395

    
1396
    inv = b & 1;
1397
    jcc_op = (b >> 1) & 7;
1398
    
1399
    if (s->jmp_opt) {
1400
        switch(s->cc_op) {
1401
            /* we optimize the cmp/jcc case */
1402
        case CC_OP_SUBB:
1403
        case CC_OP_SUBW:
1404
        case CC_OP_SUBL:
1405
            func = gen_jcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1406
            break;
1407
            
1408
            /* some jumps are easy to compute */
1409
        case CC_OP_ADDB:
1410
        case CC_OP_ADDW:
1411
        case CC_OP_ADDL:
1412
        case CC_OP_ADCB:
1413
        case CC_OP_ADCW:
1414
        case CC_OP_ADCL:
1415
        case CC_OP_SBBB:
1416
        case CC_OP_SBBW:
1417
        case CC_OP_SBBL:
1418
        case CC_OP_LOGICB:
1419
        case CC_OP_LOGICW:
1420
        case CC_OP_LOGICL:
1421
        case CC_OP_INCB:
1422
        case CC_OP_INCW:
1423
        case CC_OP_INCL:
1424
        case CC_OP_DECB:
1425
        case CC_OP_DECW:
1426
        case CC_OP_DECL:
1427
        case CC_OP_SHLB:
1428
        case CC_OP_SHLW:
1429
        case CC_OP_SHLL:
1430
        case CC_OP_SARB:
1431
        case CC_OP_SARW:
1432
        case CC_OP_SARL:
1433
            switch(jcc_op) {
1434
            case JCC_Z:
1435
                func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1436
                break;
1437
            case JCC_S:
1438
                func = gen_jcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1439
                break;
1440
            default:
1441
                func = NULL;
1442
                break;
1443
            }
1444
            break;
1445
        default:
1446
            func = NULL;
1447
            break;
1448
        }
1449

    
1450
        if (s->cc_op != CC_OP_DYNAMIC)
1451
            gen_op_set_cc_op(s->cc_op);
1452

    
1453
        if (!func) {
1454
            gen_setcc_slow[jcc_op]();
1455
            func = gen_op_jcc;
1456
        }
1457
    
1458
        tb = s->tb;
1459
        if (!inv) {
1460
            func((long)tb, val, next_eip);
1461
        } else {
1462
            func((long)tb, next_eip, val);
1463
        }
1464
        s->is_jmp = 3;
1465
    } else {
1466
        if (s->cc_op != CC_OP_DYNAMIC) {
1467
            gen_op_set_cc_op(s->cc_op);
1468
            s->cc_op = CC_OP_DYNAMIC;
1469
        }
1470
        gen_setcc_slow[jcc_op]();
1471
        if (!inv) {
1472
            gen_op_jcc_im(val, next_eip);
1473
        } else {
1474
            gen_op_jcc_im(next_eip, val);
1475
        }
1476
        gen_eob(s);
1477
    }
1478
}
1479

    
1480
static void gen_setcc(DisasContext *s, int b)
1481
{
1482
    int inv, jcc_op;
1483
    GenOpFunc *func;
1484

    
1485
    inv = b & 1;
1486
    jcc_op = (b >> 1) & 7;
1487
    switch(s->cc_op) {
1488
        /* we optimize the cmp/jcc case */
1489
    case CC_OP_SUBB:
1490
    case CC_OP_SUBW:
1491
    case CC_OP_SUBL:
1492
        func = gen_setcc_sub[s->cc_op - CC_OP_SUBB][jcc_op];
1493
        if (!func)
1494
            goto slow_jcc;
1495
        break;
1496
        
1497
        /* some jumps are easy to compute */
1498
    case CC_OP_ADDB:
1499
    case CC_OP_ADDW:
1500
    case CC_OP_ADDL:
1501
    case CC_OP_LOGICB:
1502
    case CC_OP_LOGICW:
1503
    case CC_OP_LOGICL:
1504
    case CC_OP_INCB:
1505
    case CC_OP_INCW:
1506
    case CC_OP_INCL:
1507
    case CC_OP_DECB:
1508
    case CC_OP_DECW:
1509
    case CC_OP_DECL:
1510
    case CC_OP_SHLB:
1511
    case CC_OP_SHLW:
1512
    case CC_OP_SHLL:
1513
        switch(jcc_op) {
1514
        case JCC_Z:
1515
            func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1516
            break;
1517
        case JCC_S:
1518
            func = gen_setcc_sub[(s->cc_op - CC_OP_ADDB) % 3][jcc_op];
1519
            break;
1520
        default:
1521
            goto slow_jcc;
1522
        }
1523
        break;
1524
    default:
1525
    slow_jcc:
1526
        if (s->cc_op != CC_OP_DYNAMIC)
1527
            gen_op_set_cc_op(s->cc_op);
1528
        func = gen_setcc_slow[jcc_op];
1529
        break;
1530
    }
1531
    func();
1532
    if (inv) {
1533
        gen_op_xor_T0_1();
1534
    }
1535
}
1536

    
1537
/* move T0 to seg_reg and compute if the CPU state may change. Never
1538
   call this function with seg_reg == R_CS */
1539
static void gen_movl_seg_T0(DisasContext *s, int seg_reg, unsigned int cur_eip)
1540
{
1541
    if (s->pe && !s->vm86) {
1542
        /* XXX: optimize by finding processor state dynamically */
1543
        if (s->cc_op != CC_OP_DYNAMIC)
1544
            gen_op_set_cc_op(s->cc_op);
1545
        gen_op_jmp_im(cur_eip);
1546
        gen_op_movl_seg_T0(seg_reg);
1547
    } else {
1548
        gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[seg_reg]));
1549
    }
1550
    /* abort translation because the register may have a non zero base
1551
       or because ss32 may change. For R_SS, translation must always
1552
       stop as a special handling must be done to disable hardware
1553
       interrupts for the next instruction */
1554
    if (seg_reg == R_SS || (!s->addseg && seg_reg < R_FS))
1555
        s->is_jmp = 3;
1556
}
1557

    
1558
/* generate a push. It depends on ss32, addseg and dflag */
1559
static void gen_push_T0(DisasContext *s)
1560
{
1561
    if (s->ss32) {
1562
        if (!s->addseg) {
1563
            if (s->dflag)
1564
                gen_op_pushl_T0();
1565
            else
1566
                gen_op_pushw_T0();
1567
        } else {
1568
            if (s->dflag)
1569
                gen_op_pushl_ss32_T0();
1570
            else
1571
                gen_op_pushw_ss32_T0();
1572
        }
1573
    } else {
1574
        if (s->dflag)
1575
            gen_op_pushl_ss16_T0();
1576
        else
1577
            gen_op_pushw_ss16_T0();
1578
    }
1579
}
1580

    
1581
/* two step pop is necessary for precise exceptions */
1582
static void gen_pop_T0(DisasContext *s)
1583
{
1584
    if (s->ss32) {
1585
        if (!s->addseg) {
1586
            if (s->dflag)
1587
                gen_op_popl_T0();
1588
            else
1589
                gen_op_popw_T0();
1590
        } else {
1591
            if (s->dflag)
1592
                gen_op_popl_ss32_T0();
1593
            else
1594
                gen_op_popw_ss32_T0();
1595
        }
1596
    } else {
1597
        if (s->dflag)
1598
            gen_op_popl_ss16_T0();
1599
        else
1600
            gen_op_popw_ss16_T0();
1601
    }
1602
}
1603

    
1604
static inline void gen_stack_update(DisasContext *s, int addend)
1605
{
1606
    if (s->ss32) {
1607
        if (addend == 2)
1608
            gen_op_addl_ESP_2();
1609
        else if (addend == 4)
1610
            gen_op_addl_ESP_4();
1611
        else 
1612
            gen_op_addl_ESP_im(addend);
1613
    } else {
1614
        if (addend == 2)
1615
            gen_op_addw_ESP_2();
1616
        else if (addend == 4)
1617
            gen_op_addw_ESP_4();
1618
        else
1619
            gen_op_addw_ESP_im(addend);
1620
    }
1621
}
1622

    
1623
static void gen_pop_update(DisasContext *s)
1624
{
1625
    gen_stack_update(s, 2 << s->dflag);
1626
}
1627

    
1628
static void gen_stack_A0(DisasContext *s)
1629
{
1630
    gen_op_movl_A0_ESP();
1631
    if (!s->ss32)
1632
        gen_op_andl_A0_ffff();
1633
    gen_op_movl_T1_A0();
1634
    if (s->addseg)
1635
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1636
}
1637

    
1638
/* NOTE: wrap around in 16 bit not fully handled */
1639
static void gen_pusha(DisasContext *s)
1640
{
1641
    int i;
1642
    gen_op_movl_A0_ESP();
1643
    gen_op_addl_A0_im(-16 <<  s->dflag);
1644
    if (!s->ss32)
1645
        gen_op_andl_A0_ffff();
1646
    gen_op_movl_T1_A0();
1647
    if (s->addseg)
1648
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1649
    for(i = 0;i < 8; i++) {
1650
        gen_op_mov_TN_reg[OT_LONG][0][7 - i]();
1651
        gen_op_st_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1652
        gen_op_addl_A0_im(2 <<  s->dflag);
1653
    }
1654
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1655
}
1656

    
1657
/* NOTE: wrap around in 16 bit not fully handled */
1658
static void gen_popa(DisasContext *s)
1659
{
1660
    int i;
1661
    gen_op_movl_A0_ESP();
1662
    if (!s->ss32)
1663
        gen_op_andl_A0_ffff();
1664
    gen_op_movl_T1_A0();
1665
    gen_op_addl_T1_im(16 <<  s->dflag);
1666
    if (s->addseg)
1667
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1668
    for(i = 0;i < 8; i++) {
1669
        /* ESP is not reloaded */
1670
        if (i != 3) {
1671
            gen_op_ld_T0_A0[OT_WORD + s->dflag + s->mem_index]();
1672
            gen_op_mov_reg_T0[OT_WORD + s->dflag][7 - i]();
1673
        }
1674
        gen_op_addl_A0_im(2 <<  s->dflag);
1675
    }
1676
    gen_op_mov_reg_T1[OT_WORD + s->dflag][R_ESP]();
1677
}
1678

    
1679
/* NOTE: wrap around in 16 bit not fully handled */
1680
/* XXX: check this */
1681
static void gen_enter(DisasContext *s, int esp_addend, int level)
1682
{
1683
    int ot, level1, addend, opsize;
1684

    
1685
    ot = s->dflag + OT_WORD;
1686
    level &= 0x1f;
1687
    level1 = level;
1688
    opsize = 2 << s->dflag;
1689

    
1690
    gen_op_movl_A0_ESP();
1691
    gen_op_addl_A0_im(-opsize);
1692
    if (!s->ss32)
1693
        gen_op_andl_A0_ffff();
1694
    gen_op_movl_T1_A0();
1695
    if (s->addseg)
1696
        gen_op_addl_A0_seg(offsetof(CPUX86State,segs[R_SS].base));
1697
    /* push bp */
1698
    gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
1699
    gen_op_st_T0_A0[ot + s->mem_index]();
1700
    if (level) {
1701
        while (level--) {
1702
            gen_op_addl_A0_im(-opsize);
1703
            gen_op_addl_T0_im(-opsize);
1704
            gen_op_st_T0_A0[ot + s->mem_index]();
1705
        }
1706
        gen_op_addl_A0_im(-opsize);
1707
        /* XXX: add st_T1_A0 ? */
1708
        gen_op_movl_T0_T1();
1709
        gen_op_st_T0_A0[ot + s->mem_index]();
1710
    }
1711
    gen_op_mov_reg_T1[ot][R_EBP]();
1712
    addend = -esp_addend;
1713
    if (level1)
1714
        addend -= opsize * (level1 + 1);
1715
    gen_op_addl_T1_im(addend);
1716
    gen_op_mov_reg_T1[ot][R_ESP]();
1717
}
1718

    
1719
static void gen_exception(DisasContext *s, int trapno, unsigned int cur_eip)
1720
{
1721
    if (s->cc_op != CC_OP_DYNAMIC)
1722
        gen_op_set_cc_op(s->cc_op);
1723
    gen_op_jmp_im(cur_eip);
1724
    gen_op_raise_exception(trapno);
1725
    s->is_jmp = 3;
1726
}
1727

    
1728
/* an interrupt is different from an exception because of the
1729
   priviledge checks */
1730
static void gen_interrupt(DisasContext *s, int intno, 
1731
                          unsigned int cur_eip, unsigned int next_eip)
1732
{
1733
    if (s->cc_op != CC_OP_DYNAMIC)
1734
        gen_op_set_cc_op(s->cc_op);
1735
    gen_op_jmp_im(cur_eip);
1736
    gen_op_raise_interrupt(intno, next_eip);
1737
    s->is_jmp = 3;
1738
}
1739

    
1740
static void gen_debug(DisasContext *s, unsigned int cur_eip)
1741
{
1742
    if (s->cc_op != CC_OP_DYNAMIC)
1743
        gen_op_set_cc_op(s->cc_op);
1744
    gen_op_jmp_im(cur_eip);
1745
    gen_op_debug();
1746
    s->is_jmp = 3;
1747
}
1748

    
1749
/* generate a generic end of block. Trace exception is also generated
1750
   if needed */
1751
static void gen_eob(DisasContext *s)
1752
{
1753
    if (s->cc_op != CC_OP_DYNAMIC)
1754
        gen_op_set_cc_op(s->cc_op);
1755
    if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
1756
        gen_op_reset_inhibit_irq();
1757
    }
1758
    if (s->singlestep_enabled) {
1759
        gen_op_debug();
1760
    } else if (s->tf) {
1761
        gen_op_raise_exception(EXCP01_SSTP);
1762
    } else {
1763
        gen_op_movl_T0_0();
1764
        gen_op_exit_tb();
1765
    }
1766
    s->is_jmp = 3;
1767
}
1768

    
1769
/* generate a jump to eip. No segment change must happen before as a
1770
   direct call to the next block may occur */
1771
static void gen_jmp(DisasContext *s, unsigned int eip)
1772
{
1773
    TranslationBlock *tb = s->tb;
1774

    
1775
    if (s->jmp_opt) {
1776
        if (s->cc_op != CC_OP_DYNAMIC)
1777
            gen_op_set_cc_op(s->cc_op);
1778
        gen_op_jmp((long)tb, eip);
1779
        s->is_jmp = 3;
1780
    } else {
1781
        gen_op_jmp_im(eip);
1782
        gen_eob(s);
1783
    }
1784
}
1785

    
1786
/* convert one instruction. s->is_jmp is set if the translation must
1787
   be stopped. Return the next pc value */
1788
static uint8_t *disas_insn(DisasContext *s, uint8_t *pc_start)
1789
{
1790
    int b, prefixes, aflag, dflag;
1791
    int shift, ot;
1792
    int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
1793
    unsigned int next_eip;
1794

    
1795
    s->pc = pc_start;
1796
    prefixes = 0;
1797
    aflag = s->code32;
1798
    dflag = s->code32;
1799
    s->override = -1;
1800
 next_byte:
1801
    b = ldub_code(s->pc);
1802
    s->pc++;
1803
    /* check prefixes */
1804
    switch (b) {
1805
    case 0xf3:
1806
        prefixes |= PREFIX_REPZ;
1807
        goto next_byte;
1808
    case 0xf2:
1809
        prefixes |= PREFIX_REPNZ;
1810
        goto next_byte;
1811
    case 0xf0:
1812
        prefixes |= PREFIX_LOCK;
1813
        goto next_byte;
1814
    case 0x2e:
1815
        s->override = R_CS;
1816
        goto next_byte;
1817
    case 0x36:
1818
        s->override = R_SS;
1819
        goto next_byte;
1820
    case 0x3e:
1821
        s->override = R_DS;
1822
        goto next_byte;
1823
    case 0x26:
1824
        s->override = R_ES;
1825
        goto next_byte;
1826
    case 0x64:
1827
        s->override = R_FS;
1828
        goto next_byte;
1829
    case 0x65:
1830
        s->override = R_GS;
1831
        goto next_byte;
1832
    case 0x66:
1833
        prefixes |= PREFIX_DATA;
1834
        goto next_byte;
1835
    case 0x67:
1836
        prefixes |= PREFIX_ADR;
1837
        goto next_byte;
1838
    }
1839

    
1840
    if (prefixes & PREFIX_DATA)
1841
        dflag ^= 1;
1842
    if (prefixes & PREFIX_ADR)
1843
        aflag ^= 1;
1844

    
1845
    s->prefix = prefixes;
1846
    s->aflag = aflag;
1847
    s->dflag = dflag;
1848

    
1849
    /* lock generation */
1850
    if (prefixes & PREFIX_LOCK)
1851
        gen_op_lock();
1852

    
1853
    /* now check op code */
1854
 reswitch:
1855
    switch(b) {
1856
    case 0x0f:
1857
        /**************************/
1858
        /* extended op code */
1859
        b = ldub_code(s->pc++) | 0x100;
1860
        goto reswitch;
1861
        
1862
        /**************************/
1863
        /* arith & logic */
1864
    case 0x00 ... 0x05:
1865
    case 0x08 ... 0x0d:
1866
    case 0x10 ... 0x15:
1867
    case 0x18 ... 0x1d:
1868
    case 0x20 ... 0x25:
1869
    case 0x28 ... 0x2d:
1870
    case 0x30 ... 0x35:
1871
    case 0x38 ... 0x3d:
1872
        {
1873
            int op, f, val;
1874
            op = (b >> 3) & 7;
1875
            f = (b >> 1) & 3;
1876

    
1877
            if ((b & 1) == 0)
1878
                ot = OT_BYTE;
1879
            else
1880
                ot = dflag ? OT_LONG : OT_WORD;
1881
            
1882
            switch(f) {
1883
            case 0: /* OP Ev, Gv */
1884
                modrm = ldub_code(s->pc++);
1885
                reg = ((modrm >> 3) & 7);
1886
                mod = (modrm >> 6) & 3;
1887
                rm = modrm & 7;
1888
                if (mod != 3) {
1889
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1890
                    opreg = OR_TMP0;
1891
                } else if (op == OP_XORL && rm == reg) {
1892
                xor_zero:
1893
                    /* xor reg, reg optimisation */
1894
                    gen_op_movl_T0_0();
1895
                    s->cc_op = CC_OP_LOGICB + ot;
1896
                    gen_op_mov_reg_T0[ot][reg]();
1897
                    gen_op_update1_cc();
1898
                    break;
1899
                } else {
1900
                    opreg = rm;
1901
                }
1902
                gen_op_mov_TN_reg[ot][1][reg]();
1903
                gen_op(s, op, ot, opreg);
1904
                break;
1905
            case 1: /* OP Gv, Ev */
1906
                modrm = ldub_code(s->pc++);
1907
                mod = (modrm >> 6) & 3;
1908
                reg = ((modrm >> 3) & 7);
1909
                rm = modrm & 7;
1910
                if (mod != 3) {
1911
                    gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1912
                    gen_op_ld_T1_A0[ot + s->mem_index]();
1913
                } else if (op == OP_XORL && rm == reg) {
1914
                    goto xor_zero;
1915
                } else {
1916
                    gen_op_mov_TN_reg[ot][1][rm]();
1917
                }
1918
                gen_op(s, op, ot, reg);
1919
                break;
1920
            case 2: /* OP A, Iv */
1921
                val = insn_get(s, ot);
1922
                gen_op_movl_T1_im(val);
1923
                gen_op(s, op, ot, OR_EAX);
1924
                break;
1925
            }
1926
        }
1927
        break;
1928

    
1929
    case 0x80: /* GRP1 */
1930
    case 0x81:
1931
    case 0x83:
1932
        {
1933
            int val;
1934

    
1935
            if ((b & 1) == 0)
1936
                ot = OT_BYTE;
1937
            else
1938
                ot = dflag ? OT_LONG : OT_WORD;
1939
            
1940
            modrm = ldub_code(s->pc++);
1941
            mod = (modrm >> 6) & 3;
1942
            rm = modrm & 7;
1943
            op = (modrm >> 3) & 7;
1944
            
1945
            if (mod != 3) {
1946
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1947
                opreg = OR_TMP0;
1948
            } else {
1949
                opreg = rm + OR_EAX;
1950
            }
1951

    
1952
            switch(b) {
1953
            default:
1954
            case 0x80:
1955
            case 0x81:
1956
                val = insn_get(s, ot);
1957
                break;
1958
            case 0x83:
1959
                val = (int8_t)insn_get(s, OT_BYTE);
1960
                break;
1961
            }
1962
            gen_op_movl_T1_im(val);
1963
            gen_op(s, op, ot, opreg);
1964
        }
1965
        break;
1966

    
1967
        /**************************/
1968
        /* inc, dec, and other misc arith */
1969
    case 0x40 ... 0x47: /* inc Gv */
1970
        ot = dflag ? OT_LONG : OT_WORD;
1971
        gen_inc(s, ot, OR_EAX + (b & 7), 1);
1972
        break;
1973
    case 0x48 ... 0x4f: /* dec Gv */
1974
        ot = dflag ? OT_LONG : OT_WORD;
1975
        gen_inc(s, ot, OR_EAX + (b & 7), -1);
1976
        break;
1977
    case 0xf6: /* GRP3 */
1978
    case 0xf7:
1979
        if ((b & 1) == 0)
1980
            ot = OT_BYTE;
1981
        else
1982
            ot = dflag ? OT_LONG : OT_WORD;
1983

    
1984
        modrm = ldub_code(s->pc++);
1985
        mod = (modrm >> 6) & 3;
1986
        rm = modrm & 7;
1987
        op = (modrm >> 3) & 7;
1988
        if (mod != 3) {
1989
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
1990
            gen_op_ld_T0_A0[ot + s->mem_index]();
1991
        } else {
1992
            gen_op_mov_TN_reg[ot][0][rm]();
1993
        }
1994

    
1995
        switch(op) {
1996
        case 0: /* test */
1997
            val = insn_get(s, ot);
1998
            gen_op_movl_T1_im(val);
1999
            gen_op_testl_T0_T1_cc();
2000
            s->cc_op = CC_OP_LOGICB + ot;
2001
            break;
2002
        case 2: /* not */
2003
            gen_op_notl_T0();
2004
            if (mod != 3) {
2005
                gen_op_st_T0_A0[ot + s->mem_index]();
2006
            } else {
2007
                gen_op_mov_reg_T0[ot][rm]();
2008
            }
2009
            break;
2010
        case 3: /* neg */
2011
            gen_op_negl_T0();
2012
            if (mod != 3) {
2013
                gen_op_st_T0_A0[ot + s->mem_index]();
2014
            } else {
2015
                gen_op_mov_reg_T0[ot][rm]();
2016
            }
2017
            gen_op_update_neg_cc();
2018
            s->cc_op = CC_OP_SUBB + ot;
2019
            break;
2020
        case 4: /* mul */
2021
            switch(ot) {
2022
            case OT_BYTE:
2023
                gen_op_mulb_AL_T0();
2024
                s->cc_op = CC_OP_MULB;
2025
                break;
2026
            case OT_WORD:
2027
                gen_op_mulw_AX_T0();
2028
                s->cc_op = CC_OP_MULW;
2029
                break;
2030
            default:
2031
            case OT_LONG:
2032
                gen_op_mull_EAX_T0();
2033
                s->cc_op = CC_OP_MULL;
2034
                break;
2035
            }
2036
            break;
2037
        case 5: /* imul */
2038
            switch(ot) {
2039
            case OT_BYTE:
2040
                gen_op_imulb_AL_T0();
2041
                s->cc_op = CC_OP_MULB;
2042
                break;
2043
            case OT_WORD:
2044
                gen_op_imulw_AX_T0();
2045
                s->cc_op = CC_OP_MULW;
2046
                break;
2047
            default:
2048
            case OT_LONG:
2049
                gen_op_imull_EAX_T0();
2050
                s->cc_op = CC_OP_MULL;
2051
                break;
2052
            }
2053
            break;
2054
        case 6: /* div */
2055
            switch(ot) {
2056
            case OT_BYTE:
2057
                gen_op_divb_AL_T0(pc_start - s->cs_base);
2058
                break;
2059
            case OT_WORD:
2060
                gen_op_divw_AX_T0(pc_start - s->cs_base);
2061
                break;
2062
            default:
2063
            case OT_LONG:
2064
                gen_op_divl_EAX_T0(pc_start - s->cs_base);
2065
                break;
2066
            }
2067
            break;
2068
        case 7: /* idiv */
2069
            switch(ot) {
2070
            case OT_BYTE:
2071
                gen_op_idivb_AL_T0(pc_start - s->cs_base);
2072
                break;
2073
            case OT_WORD:
2074
                gen_op_idivw_AX_T0(pc_start - s->cs_base);
2075
                break;
2076
            default:
2077
            case OT_LONG:
2078
                gen_op_idivl_EAX_T0(pc_start - s->cs_base);
2079
                break;
2080
            }
2081
            break;
2082
        default:
2083
            goto illegal_op;
2084
        }
2085
        break;
2086

    
2087
    case 0xfe: /* GRP4 */
2088
    case 0xff: /* GRP5 */
2089
        if ((b & 1) == 0)
2090
            ot = OT_BYTE;
2091
        else
2092
            ot = dflag ? OT_LONG : OT_WORD;
2093

    
2094
        modrm = ldub_code(s->pc++);
2095
        mod = (modrm >> 6) & 3;
2096
        rm = modrm & 7;
2097
        op = (modrm >> 3) & 7;
2098
        if (op >= 2 && b == 0xfe) {
2099
            goto illegal_op;
2100
        }
2101
        if (mod != 3) {
2102
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2103
            if (op >= 2 && op != 3 && op != 5)
2104
                gen_op_ld_T0_A0[ot + s->mem_index]();
2105
        } else {
2106
            gen_op_mov_TN_reg[ot][0][rm]();
2107
        }
2108

    
2109
        switch(op) {
2110
        case 0: /* inc Ev */
2111
            if (mod != 3)
2112
                opreg = OR_TMP0;
2113
            else
2114
                opreg = rm;
2115
            gen_inc(s, ot, opreg, 1);
2116
            break;
2117
        case 1: /* dec Ev */
2118
            if (mod != 3)
2119
                opreg = OR_TMP0;
2120
            else
2121
                opreg = rm;
2122
            gen_inc(s, ot, opreg, -1);
2123
            break;
2124
        case 2: /* call Ev */
2125
            /* XXX: optimize if memory (no and is necessary) */
2126
            if (s->dflag == 0)
2127
                gen_op_andl_T0_ffff();
2128
            gen_op_jmp_T0();
2129
            next_eip = s->pc - s->cs_base;
2130
            gen_op_movl_T0_im(next_eip);
2131
            gen_push_T0(s);
2132
            gen_eob(s);
2133
            break;
2134
        case 3: /* lcall Ev */
2135
            gen_op_ld_T1_A0[ot + s->mem_index]();
2136
            gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2137
            gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2138
        do_lcall:
2139
            if (s->pe && !s->vm86) {
2140
                if (s->cc_op != CC_OP_DYNAMIC)
2141
                    gen_op_set_cc_op(s->cc_op);
2142
                gen_op_jmp_im(pc_start - s->cs_base);
2143
                gen_op_lcall_protected_T0_T1(dflag, s->pc - s->cs_base);
2144
            } else {
2145
                gen_op_lcall_real_T0_T1(dflag, s->pc - s->cs_base);
2146
            }
2147
            gen_eob(s);
2148
            break;
2149
        case 4: /* jmp Ev */
2150
            if (s->dflag == 0)
2151
                gen_op_andl_T0_ffff();
2152
            gen_op_jmp_T0();
2153
            gen_eob(s);
2154
            break;
2155
        case 5: /* ljmp Ev */
2156
            gen_op_ld_T1_A0[ot + s->mem_index]();
2157
            gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2158
            gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2159
        do_ljmp:
2160
            if (s->pe && !s->vm86) {
2161
                if (s->cc_op != CC_OP_DYNAMIC)
2162
                    gen_op_set_cc_op(s->cc_op);
2163
                gen_op_jmp_im(pc_start - s->cs_base);
2164
                gen_op_ljmp_protected_T0_T1();
2165
            } else {
2166
                gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
2167
                gen_op_movl_T0_T1();
2168
                gen_op_jmp_T0();
2169
            }
2170
            gen_eob(s);
2171
            break;
2172
        case 6: /* push Ev */
2173
            gen_push_T0(s);
2174
            break;
2175
        default:
2176
            goto illegal_op;
2177
        }
2178
        break;
2179

    
2180
    case 0x84: /* test Ev, Gv */
2181
    case 0x85: 
2182
        if ((b & 1) == 0)
2183
            ot = OT_BYTE;
2184
        else
2185
            ot = dflag ? OT_LONG : OT_WORD;
2186

    
2187
        modrm = ldub_code(s->pc++);
2188
        mod = (modrm >> 6) & 3;
2189
        rm = modrm & 7;
2190
        reg = (modrm >> 3) & 7;
2191
        
2192
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2193
        gen_op_mov_TN_reg[ot][1][reg + OR_EAX]();
2194
        gen_op_testl_T0_T1_cc();
2195
        s->cc_op = CC_OP_LOGICB + ot;
2196
        break;
2197
        
2198
    case 0xa8: /* test eAX, Iv */
2199
    case 0xa9:
2200
        if ((b & 1) == 0)
2201
            ot = OT_BYTE;
2202
        else
2203
            ot = dflag ? OT_LONG : OT_WORD;
2204
        val = insn_get(s, ot);
2205

    
2206
        gen_op_mov_TN_reg[ot][0][OR_EAX]();
2207
        gen_op_movl_T1_im(val);
2208
        gen_op_testl_T0_T1_cc();
2209
        s->cc_op = CC_OP_LOGICB + ot;
2210
        break;
2211
        
2212
    case 0x98: /* CWDE/CBW */
2213
        if (dflag)
2214
            gen_op_movswl_EAX_AX();
2215
        else
2216
            gen_op_movsbw_AX_AL();
2217
        break;
2218
    case 0x99: /* CDQ/CWD */
2219
        if (dflag)
2220
            gen_op_movslq_EDX_EAX();
2221
        else
2222
            gen_op_movswl_DX_AX();
2223
        break;
2224
    case 0x1af: /* imul Gv, Ev */
2225
    case 0x69: /* imul Gv, Ev, I */
2226
    case 0x6b:
2227
        ot = dflag ? OT_LONG : OT_WORD;
2228
        modrm = ldub_code(s->pc++);
2229
        reg = ((modrm >> 3) & 7) + OR_EAX;
2230
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2231
        if (b == 0x69) {
2232
            val = insn_get(s, ot);
2233
            gen_op_movl_T1_im(val);
2234
        } else if (b == 0x6b) {
2235
            val = insn_get(s, OT_BYTE);
2236
            gen_op_movl_T1_im(val);
2237
        } else {
2238
            gen_op_mov_TN_reg[ot][1][reg]();
2239
        }
2240

    
2241
        if (ot == OT_LONG) {
2242
            gen_op_imull_T0_T1();
2243
        } else {
2244
            gen_op_imulw_T0_T1();
2245
        }
2246
        gen_op_mov_reg_T0[ot][reg]();
2247
        s->cc_op = CC_OP_MULB + ot;
2248
        break;
2249
    case 0x1c0:
2250
    case 0x1c1: /* xadd Ev, Gv */
2251
        if ((b & 1) == 0)
2252
            ot = OT_BYTE;
2253
        else
2254
            ot = dflag ? OT_LONG : OT_WORD;
2255
        modrm = ldub_code(s->pc++);
2256
        reg = (modrm >> 3) & 7;
2257
        mod = (modrm >> 6) & 3;
2258
        if (mod == 3) {
2259
            rm = modrm & 7;
2260
            gen_op_mov_TN_reg[ot][0][reg]();
2261
            gen_op_mov_TN_reg[ot][1][rm]();
2262
            gen_op_addl_T0_T1();
2263
            gen_op_mov_reg_T0[ot][rm]();
2264
            gen_op_mov_reg_T1[ot][reg]();
2265
        } else {
2266
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2267
            gen_op_mov_TN_reg[ot][0][reg]();
2268
            gen_op_ld_T1_A0[ot + s->mem_index]();
2269
            gen_op_addl_T0_T1();
2270
            gen_op_st_T0_A0[ot + s->mem_index]();
2271
            gen_op_mov_reg_T1[ot][reg]();
2272
        }
2273
        gen_op_update2_cc();
2274
        s->cc_op = CC_OP_ADDB + ot;
2275
        break;
2276
    case 0x1b0:
2277
    case 0x1b1: /* cmpxchg Ev, Gv */
2278
        if ((b & 1) == 0)
2279
            ot = OT_BYTE;
2280
        else
2281
            ot = dflag ? OT_LONG : OT_WORD;
2282
        modrm = ldub_code(s->pc++);
2283
        reg = (modrm >> 3) & 7;
2284
        mod = (modrm >> 6) & 3;
2285
        gen_op_mov_TN_reg[ot][1][reg]();
2286
        if (mod == 3) {
2287
            rm = modrm & 7;
2288
            gen_op_mov_TN_reg[ot][0][rm]();
2289
            gen_op_cmpxchg_T0_T1_EAX_cc[ot]();
2290
            gen_op_mov_reg_T0[ot][rm]();
2291
        } else {
2292
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2293
            gen_op_ld_T0_A0[ot + s->mem_index]();
2294
            gen_op_cmpxchg_mem_T0_T1_EAX_cc[ot]();
2295
        }
2296
        s->cc_op = CC_OP_SUBB + ot;
2297
        break;
2298
    case 0x1c7: /* cmpxchg8b */
2299
        modrm = ldub_code(s->pc++);
2300
        mod = (modrm >> 6) & 3;
2301
        if (mod == 3)
2302
            goto illegal_op;
2303
        if (s->cc_op != CC_OP_DYNAMIC)
2304
            gen_op_set_cc_op(s->cc_op);
2305
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2306
        gen_op_cmpxchg8b();
2307
        s->cc_op = CC_OP_EFLAGS;
2308
        break;
2309
        
2310
        /**************************/
2311
        /* push/pop */
2312
    case 0x50 ... 0x57: /* push */
2313
        gen_op_mov_TN_reg[OT_LONG][0][b & 7]();
2314
        gen_push_T0(s);
2315
        break;
2316
    case 0x58 ... 0x5f: /* pop */
2317
        ot = dflag ? OT_LONG : OT_WORD;
2318
        gen_pop_T0(s);
2319
        /* NOTE: order is important for pop %sp */
2320
        gen_pop_update(s);
2321
        gen_op_mov_reg_T0[ot][b & 7]();
2322
        break;
2323
    case 0x60: /* pusha */
2324
        gen_pusha(s);
2325
        break;
2326
    case 0x61: /* popa */
2327
        gen_popa(s);
2328
        break;
2329
    case 0x68: /* push Iv */
2330
    case 0x6a:
2331
        ot = dflag ? OT_LONG : OT_WORD;
2332
        if (b == 0x68)
2333
            val = insn_get(s, ot);
2334
        else
2335
            val = (int8_t)insn_get(s, OT_BYTE);
2336
        gen_op_movl_T0_im(val);
2337
        gen_push_T0(s);
2338
        break;
2339
    case 0x8f: /* pop Ev */
2340
        ot = dflag ? OT_LONG : OT_WORD;
2341
        modrm = ldub_code(s->pc++);
2342
        mod = (modrm >> 6) & 3;
2343
        gen_pop_T0(s);
2344
        if (mod == 3) {
2345
            /* NOTE: order is important for pop %sp */
2346
            gen_pop_update(s);
2347
            rm = modrm & 7;
2348
            gen_op_mov_reg_T0[ot][rm]();
2349
        } else {
2350
            /* NOTE: order is important too for MMU exceptions */
2351
            s->popl_esp_hack = 2 << dflag;
2352
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2353
            s->popl_esp_hack = 0;
2354
            gen_pop_update(s);
2355
        }
2356
        break;
2357
    case 0xc8: /* enter */
2358
        {
2359
            int level;
2360
            val = lduw_code(s->pc);
2361
            s->pc += 2;
2362
            level = ldub_code(s->pc++);
2363
            gen_enter(s, val, level);
2364
        }
2365
        break;
2366
    case 0xc9: /* leave */
2367
        /* XXX: exception not precise (ESP is updated before potential exception) */
2368
        if (s->ss32) {
2369
            gen_op_mov_TN_reg[OT_LONG][0][R_EBP]();
2370
            gen_op_mov_reg_T0[OT_LONG][R_ESP]();
2371
        } else {
2372
            gen_op_mov_TN_reg[OT_WORD][0][R_EBP]();
2373
            gen_op_mov_reg_T0[OT_WORD][R_ESP]();
2374
        }
2375
        gen_pop_T0(s);
2376
        ot = dflag ? OT_LONG : OT_WORD;
2377
        gen_op_mov_reg_T0[ot][R_EBP]();
2378
        gen_pop_update(s);
2379
        break;
2380
    case 0x06: /* push es */
2381
    case 0x0e: /* push cs */
2382
    case 0x16: /* push ss */
2383
    case 0x1e: /* push ds */
2384
        gen_op_movl_T0_seg(b >> 3);
2385
        gen_push_T0(s);
2386
        break;
2387
    case 0x1a0: /* push fs */
2388
    case 0x1a8: /* push gs */
2389
        gen_op_movl_T0_seg((b >> 3) & 7);
2390
        gen_push_T0(s);
2391
        break;
2392
    case 0x07: /* pop es */
2393
    case 0x17: /* pop ss */
2394
    case 0x1f: /* pop ds */
2395
        reg = b >> 3;
2396
        gen_pop_T0(s);
2397
        gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2398
        gen_pop_update(s);
2399
        if (reg == R_SS) {
2400
            /* if reg == SS, inhibit interrupts/trace. */
2401
            /* If several instructions disable interrupts, only the
2402
               _first_ does it */
2403
            if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2404
                gen_op_set_inhibit_irq();
2405
            s->tf = 0;
2406
        }
2407
        if (s->is_jmp) {
2408
            gen_op_jmp_im(s->pc - s->cs_base);
2409
            gen_eob(s);
2410
        }
2411
        break;
2412
    case 0x1a1: /* pop fs */
2413
    case 0x1a9: /* pop gs */
2414
        gen_pop_T0(s);
2415
        gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
2416
        gen_pop_update(s);
2417
        if (s->is_jmp) {
2418
            gen_op_jmp_im(s->pc - s->cs_base);
2419
            gen_eob(s);
2420
        }
2421
        break;
2422

    
2423
        /**************************/
2424
        /* mov */
2425
    case 0x88:
2426
    case 0x89: /* mov Gv, Ev */
2427
        if ((b & 1) == 0)
2428
            ot = OT_BYTE;
2429
        else
2430
            ot = dflag ? OT_LONG : OT_WORD;
2431
        modrm = ldub_code(s->pc++);
2432
        reg = (modrm >> 3) & 7;
2433
        
2434
        /* generate a generic store */
2435
        gen_ldst_modrm(s, modrm, ot, OR_EAX + reg, 1);
2436
        break;
2437
    case 0xc6:
2438
    case 0xc7: /* mov Ev, Iv */
2439
        if ((b & 1) == 0)
2440
            ot = OT_BYTE;
2441
        else
2442
            ot = dflag ? OT_LONG : OT_WORD;
2443
        modrm = ldub_code(s->pc++);
2444
        mod = (modrm >> 6) & 3;
2445
        if (mod != 3)
2446
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2447
        val = insn_get(s, ot);
2448
        gen_op_movl_T0_im(val);
2449
        if (mod != 3)
2450
            gen_op_st_T0_A0[ot + s->mem_index]();
2451
        else
2452
            gen_op_mov_reg_T0[ot][modrm & 7]();
2453
        break;
2454
    case 0x8a:
2455
    case 0x8b: /* mov Ev, Gv */
2456
        if ((b & 1) == 0)
2457
            ot = OT_BYTE;
2458
        else
2459
            ot = dflag ? OT_LONG : OT_WORD;
2460
        modrm = ldub_code(s->pc++);
2461
        reg = (modrm >> 3) & 7;
2462
        
2463
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
2464
        gen_op_mov_reg_T0[ot][reg]();
2465
        break;
2466
    case 0x8e: /* mov seg, Gv */
2467
        modrm = ldub_code(s->pc++);
2468
        reg = (modrm >> 3) & 7;
2469
        if (reg >= 6 || reg == R_CS)
2470
            goto illegal_op;
2471
        gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
2472
        gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
2473
        if (reg == R_SS) {
2474
            /* if reg == SS, inhibit interrupts/trace */
2475
            /* If several instructions disable interrupts, only the
2476
               _first_ does it */
2477
            if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
2478
                gen_op_set_inhibit_irq();
2479
            s->tf = 0;
2480
        }
2481
        if (s->is_jmp) {
2482
            gen_op_jmp_im(s->pc - s->cs_base);
2483
            gen_eob(s);
2484
        }
2485
        break;
2486
    case 0x8c: /* mov Gv, seg */
2487
        modrm = ldub_code(s->pc++);
2488
        reg = (modrm >> 3) & 7;
2489
        mod = (modrm >> 6) & 3;
2490
        if (reg >= 6)
2491
            goto illegal_op;
2492
        gen_op_movl_T0_seg(reg);
2493
        ot = OT_WORD;
2494
        if (mod == 3 && dflag)
2495
            ot = OT_LONG;
2496
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
2497
        break;
2498

    
2499
    case 0x1b6: /* movzbS Gv, Eb */
2500
    case 0x1b7: /* movzwS Gv, Eb */
2501
    case 0x1be: /* movsbS Gv, Eb */
2502
    case 0x1bf: /* movswS Gv, Eb */
2503
        {
2504
            int d_ot;
2505
            /* d_ot is the size of destination */
2506
            d_ot = dflag + OT_WORD;
2507
            /* ot is the size of source */
2508
            ot = (b & 1) + OT_BYTE;
2509
            modrm = ldub_code(s->pc++);
2510
            reg = ((modrm >> 3) & 7) + OR_EAX;
2511
            mod = (modrm >> 6) & 3;
2512
            rm = modrm & 7;
2513
            
2514
            if (mod == 3) {
2515
                gen_op_mov_TN_reg[ot][0][rm]();
2516
                switch(ot | (b & 8)) {
2517
                case OT_BYTE:
2518
                    gen_op_movzbl_T0_T0();
2519
                    break;
2520
                case OT_BYTE | 8:
2521
                    gen_op_movsbl_T0_T0();
2522
                    break;
2523
                case OT_WORD:
2524
                    gen_op_movzwl_T0_T0();
2525
                    break;
2526
                default:
2527
                case OT_WORD | 8:
2528
                    gen_op_movswl_T0_T0();
2529
                    break;
2530
                }
2531
                gen_op_mov_reg_T0[d_ot][reg]();
2532
            } else {
2533
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2534
                if (b & 8) {
2535
                    gen_op_lds_T0_A0[ot + s->mem_index]();
2536
                } else {
2537
                    gen_op_ldu_T0_A0[ot + s->mem_index]();
2538
                }
2539
                gen_op_mov_reg_T0[d_ot][reg]();
2540
            }
2541
        }
2542
        break;
2543

    
2544
    case 0x8d: /* lea */
2545
        ot = dflag ? OT_LONG : OT_WORD;
2546
        modrm = ldub_code(s->pc++);
2547
        reg = (modrm >> 3) & 7;
2548
        /* we must ensure that no segment is added */
2549
        s->override = -1;
2550
        val = s->addseg;
2551
        s->addseg = 0;
2552
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2553
        s->addseg = val;
2554
        gen_op_mov_reg_A0[ot - OT_WORD][reg]();
2555
        break;
2556
        
2557
    case 0xa0: /* mov EAX, Ov */
2558
    case 0xa1:
2559
    case 0xa2: /* mov Ov, EAX */
2560
    case 0xa3:
2561
        if ((b & 1) == 0)
2562
            ot = OT_BYTE;
2563
        else
2564
            ot = dflag ? OT_LONG : OT_WORD;
2565
        if (s->aflag)
2566
            offset_addr = insn_get(s, OT_LONG);
2567
        else
2568
            offset_addr = insn_get(s, OT_WORD);
2569
        gen_op_movl_A0_im(offset_addr);
2570
        /* handle override */
2571
        {
2572
            int override, must_add_seg;
2573
            must_add_seg = s->addseg;
2574
            if (s->override >= 0) {
2575
                override = s->override;
2576
                must_add_seg = 1;
2577
            } else {
2578
                override = R_DS;
2579
            }
2580
            if (must_add_seg) {
2581
                gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2582
            }
2583
        }
2584
        if ((b & 2) == 0) {
2585
            gen_op_ld_T0_A0[ot + s->mem_index]();
2586
            gen_op_mov_reg_T0[ot][R_EAX]();
2587
        } else {
2588
            gen_op_mov_TN_reg[ot][0][R_EAX]();
2589
            gen_op_st_T0_A0[ot + s->mem_index]();
2590
        }
2591
        break;
2592
    case 0xd7: /* xlat */
2593
        gen_op_movl_A0_reg[R_EBX]();
2594
        gen_op_addl_A0_AL();
2595
        if (s->aflag == 0)
2596
            gen_op_andl_A0_ffff();
2597
        /* handle override */
2598
        {
2599
            int override, must_add_seg;
2600
            must_add_seg = s->addseg;
2601
            override = R_DS;
2602
            if (s->override >= 0) {
2603
                override = s->override;
2604
                must_add_seg = 1;
2605
            } else {
2606
                override = R_DS;
2607
            }
2608
            if (must_add_seg) {
2609
                gen_op_addl_A0_seg(offsetof(CPUX86State,segs[override].base));
2610
            }
2611
        }
2612
        gen_op_ldu_T0_A0[OT_BYTE + s->mem_index]();
2613
        gen_op_mov_reg_T0[OT_BYTE][R_EAX]();
2614
        break;
2615
    case 0xb0 ... 0xb7: /* mov R, Ib */
2616
        val = insn_get(s, OT_BYTE);
2617
        gen_op_movl_T0_im(val);
2618
        gen_op_mov_reg_T0[OT_BYTE][b & 7]();
2619
        break;
2620
    case 0xb8 ... 0xbf: /* mov R, Iv */
2621
        ot = dflag ? OT_LONG : OT_WORD;
2622
        val = insn_get(s, ot);
2623
        reg = OR_EAX + (b & 7);
2624
        gen_op_movl_T0_im(val);
2625
        gen_op_mov_reg_T0[ot][reg]();
2626
        break;
2627

    
2628
    case 0x91 ... 0x97: /* xchg R, EAX */
2629
        ot = dflag ? OT_LONG : OT_WORD;
2630
        reg = b & 7;
2631
        rm = R_EAX;
2632
        goto do_xchg_reg;
2633
    case 0x86:
2634
    case 0x87: /* xchg Ev, Gv */
2635
        if ((b & 1) == 0)
2636
            ot = OT_BYTE;
2637
        else
2638
            ot = dflag ? OT_LONG : OT_WORD;
2639
        modrm = ldub_code(s->pc++);
2640
        reg = (modrm >> 3) & 7;
2641
        mod = (modrm >> 6) & 3;
2642
        if (mod == 3) {
2643
            rm = modrm & 7;
2644
        do_xchg_reg:
2645
            gen_op_mov_TN_reg[ot][0][reg]();
2646
            gen_op_mov_TN_reg[ot][1][rm]();
2647
            gen_op_mov_reg_T0[ot][rm]();
2648
            gen_op_mov_reg_T1[ot][reg]();
2649
        } else {
2650
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2651
            gen_op_mov_TN_reg[ot][0][reg]();
2652
            /* for xchg, lock is implicit */
2653
            if (!(prefixes & PREFIX_LOCK))
2654
                gen_op_lock();
2655
            gen_op_ld_T1_A0[ot + s->mem_index]();
2656
            gen_op_st_T0_A0[ot + s->mem_index]();
2657
            if (!(prefixes & PREFIX_LOCK))
2658
                gen_op_unlock();
2659
            gen_op_mov_reg_T1[ot][reg]();
2660
        }
2661
        break;
2662
    case 0xc4: /* les Gv */
2663
        op = R_ES;
2664
        goto do_lxx;
2665
    case 0xc5: /* lds Gv */
2666
        op = R_DS;
2667
        goto do_lxx;
2668
    case 0x1b2: /* lss Gv */
2669
        op = R_SS;
2670
        goto do_lxx;
2671
    case 0x1b4: /* lfs Gv */
2672
        op = R_FS;
2673
        goto do_lxx;
2674
    case 0x1b5: /* lgs Gv */
2675
        op = R_GS;
2676
    do_lxx:
2677
        ot = dflag ? OT_LONG : OT_WORD;
2678
        modrm = ldub_code(s->pc++);
2679
        reg = (modrm >> 3) & 7;
2680
        mod = (modrm >> 6) & 3;
2681
        if (mod == 3)
2682
            goto illegal_op;
2683
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2684
        gen_op_ld_T1_A0[ot + s->mem_index]();
2685
        gen_op_addl_A0_im(1 << (ot - OT_WORD + 1));
2686
        /* load the segment first to handle exceptions properly */
2687
        gen_op_ldu_T0_A0[OT_WORD + s->mem_index]();
2688
        gen_movl_seg_T0(s, op, pc_start - s->cs_base);
2689
        /* then put the data */
2690
        gen_op_mov_reg_T1[ot][reg]();
2691
        if (s->is_jmp) {
2692
            gen_op_jmp_im(s->pc - s->cs_base);
2693
            gen_eob(s);
2694
        }
2695
        break;
2696
        
2697
        /************************/
2698
        /* shifts */
2699
    case 0xc0:
2700
    case 0xc1:
2701
        /* shift Ev,Ib */
2702
        shift = 2;
2703
    grp2:
2704
        {
2705
            if ((b & 1) == 0)
2706
                ot = OT_BYTE;
2707
            else
2708
                ot = dflag ? OT_LONG : OT_WORD;
2709
            
2710
            modrm = ldub_code(s->pc++);
2711
            mod = (modrm >> 6) & 3;
2712
            rm = modrm & 7;
2713
            op = (modrm >> 3) & 7;
2714
            
2715
            if (mod != 3) {
2716
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2717
                opreg = OR_TMP0;
2718
            } else {
2719
                opreg = rm + OR_EAX;
2720
            }
2721

    
2722
            /* simpler op */
2723
            if (shift == 0) {
2724
                gen_shift(s, op, ot, opreg, OR_ECX);
2725
            } else {
2726
                if (shift == 2) {
2727
                    shift = ldub_code(s->pc++);
2728
                }
2729
                gen_shifti(s, op, ot, opreg, shift);
2730
            }
2731
        }
2732
        break;
2733
    case 0xd0:
2734
    case 0xd1:
2735
        /* shift Ev,1 */
2736
        shift = 1;
2737
        goto grp2;
2738
    case 0xd2:
2739
    case 0xd3:
2740
        /* shift Ev,cl */
2741
        shift = 0;
2742
        goto grp2;
2743

    
2744
    case 0x1a4: /* shld imm */
2745
        op = 0;
2746
        shift = 1;
2747
        goto do_shiftd;
2748
    case 0x1a5: /* shld cl */
2749
        op = 0;
2750
        shift = 0;
2751
        goto do_shiftd;
2752
    case 0x1ac: /* shrd imm */
2753
        op = 1;
2754
        shift = 1;
2755
        goto do_shiftd;
2756
    case 0x1ad: /* shrd cl */
2757
        op = 1;
2758
        shift = 0;
2759
    do_shiftd:
2760
        ot = dflag ? OT_LONG : OT_WORD;
2761
        modrm = ldub_code(s->pc++);
2762
        mod = (modrm >> 6) & 3;
2763
        rm = modrm & 7;
2764
        reg = (modrm >> 3) & 7;
2765
        
2766
        if (mod != 3) {
2767
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2768
            gen_op_ld_T0_A0[ot + s->mem_index]();
2769
        } else {
2770
            gen_op_mov_TN_reg[ot][0][rm]();
2771
        }
2772
        gen_op_mov_TN_reg[ot][1][reg]();
2773
        
2774
        if (shift) {
2775
            val = ldub_code(s->pc++);
2776
            val &= 0x1f;
2777
            if (val) {
2778
                if (mod == 3)
2779
                    gen_op_shiftd_T0_T1_im_cc[ot - OT_WORD][op](val);
2780
                else
2781
                    gen_op_shiftd_mem_T0_T1_im_cc[ot - OT_WORD][op](val);
2782
                if (op == 0 && ot != OT_WORD)
2783
                    s->cc_op = CC_OP_SHLB + ot;
2784
                else
2785
                    s->cc_op = CC_OP_SARB + ot;
2786
            }
2787
        } else {
2788
            if (s->cc_op != CC_OP_DYNAMIC)
2789
                gen_op_set_cc_op(s->cc_op);
2790
            if (mod == 3)
2791
                gen_op_shiftd_T0_T1_ECX_cc[ot - OT_WORD][op]();
2792
            else
2793
                gen_op_shiftd_mem_T0_T1_ECX_cc[ot - OT_WORD][op]();
2794
            s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
2795
        }
2796
        if (mod == 3) {
2797
            gen_op_mov_reg_T0[ot][rm]();
2798
        }
2799
        break;
2800

    
2801
        /************************/
2802
        /* floats */
2803
    case 0xd8 ... 0xdf: 
2804
        modrm = ldub_code(s->pc++);
2805
        mod = (modrm >> 6) & 3;
2806
        rm = modrm & 7;
2807
        op = ((b & 7) << 3) | ((modrm >> 3) & 7);
2808
        
2809
        if (mod != 3) {
2810
            /* memory op */
2811
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
2812
            switch(op) {
2813
            case 0x00 ... 0x07: /* fxxxs */
2814
            case 0x10 ... 0x17: /* fixxxl */
2815
            case 0x20 ... 0x27: /* fxxxl */
2816
            case 0x30 ... 0x37: /* fixxx */
2817
                {
2818
                    int op1;
2819
                    op1 = op & 7;
2820

    
2821
                    switch(op >> 4) {
2822
                    case 0:
2823
                        gen_op_flds_FT0_A0();
2824
                        break;
2825
                    case 1:
2826
                        gen_op_fildl_FT0_A0();
2827
                        break;
2828
                    case 2:
2829
                        gen_op_fldl_FT0_A0();
2830
                        break;
2831
                    case 3:
2832
                    default:
2833
                        gen_op_fild_FT0_A0();
2834
                        break;
2835
                    }
2836
                    
2837
                    gen_op_fp_arith_ST0_FT0[op1]();
2838
                    if (op1 == 3) {
2839
                        /* fcomp needs pop */
2840
                        gen_op_fpop();
2841
                    }
2842
                }
2843
                break;
2844
            case 0x08: /* flds */
2845
            case 0x0a: /* fsts */
2846
            case 0x0b: /* fstps */
2847
            case 0x18: /* fildl */
2848
            case 0x1a: /* fistl */
2849
            case 0x1b: /* fistpl */
2850
            case 0x28: /* fldl */
2851
            case 0x2a: /* fstl */
2852
            case 0x2b: /* fstpl */
2853
            case 0x38: /* filds */
2854
            case 0x3a: /* fists */
2855
            case 0x3b: /* fistps */
2856
                
2857
                switch(op & 7) {
2858
                case 0:
2859
                    switch(op >> 4) {
2860
                    case 0:
2861
                        gen_op_flds_ST0_A0();
2862
                        break;
2863
                    case 1:
2864
                        gen_op_fildl_ST0_A0();
2865
                        break;
2866
                    case 2:
2867
                        gen_op_fldl_ST0_A0();
2868
                        break;
2869
                    case 3:
2870
                    default:
2871
                        gen_op_fild_ST0_A0();
2872
                        break;
2873
                    }
2874
                    break;
2875
                default:
2876
                    switch(op >> 4) {
2877
                    case 0:
2878
                        gen_op_fsts_ST0_A0();
2879
                        break;
2880
                    case 1:
2881
                        gen_op_fistl_ST0_A0();
2882
                        break;
2883
                    case 2:
2884
                        gen_op_fstl_ST0_A0();
2885
                        break;
2886
                    case 3:
2887
                    default:
2888
                        gen_op_fist_ST0_A0();
2889
                        break;
2890
                    }
2891
                    if ((op & 7) == 3)
2892
                        gen_op_fpop();
2893
                    break;
2894
                }
2895
                break;
2896
            case 0x0c: /* fldenv mem */
2897
                gen_op_fldenv_A0(s->dflag);
2898
                break;
2899
            case 0x0d: /* fldcw mem */
2900
                gen_op_fldcw_A0();
2901
                break;
2902
            case 0x0e: /* fnstenv mem */
2903
                gen_op_fnstenv_A0(s->dflag);
2904
                break;
2905
            case 0x0f: /* fnstcw mem */
2906
                gen_op_fnstcw_A0();
2907
                break;
2908
            case 0x1d: /* fldt mem */
2909
                gen_op_fldt_ST0_A0();
2910
                break;
2911
            case 0x1f: /* fstpt mem */
2912
                gen_op_fstt_ST0_A0();
2913
                gen_op_fpop();
2914
                break;
2915
            case 0x2c: /* frstor mem */
2916
                gen_op_frstor_A0(s->dflag);
2917
                break;
2918
            case 0x2e: /* fnsave mem */
2919
                gen_op_fnsave_A0(s->dflag);
2920
                break;
2921
            case 0x2f: /* fnstsw mem */
2922
                gen_op_fnstsw_A0();
2923
                break;
2924
            case 0x3c: /* fbld */
2925
                gen_op_fbld_ST0_A0();
2926
                break;
2927
            case 0x3e: /* fbstp */
2928
                gen_op_fbst_ST0_A0();
2929
                gen_op_fpop();
2930
                break;
2931
            case 0x3d: /* fildll */
2932
                gen_op_fildll_ST0_A0();
2933
                break;
2934
            case 0x3f: /* fistpll */
2935
                gen_op_fistll_ST0_A0();
2936
                gen_op_fpop();
2937
                break;
2938
            default:
2939
                goto illegal_op;
2940
            }
2941
        } else {
2942
            /* register float ops */
2943
            opreg = rm;
2944

    
2945
            switch(op) {
2946
            case 0x08: /* fld sti */
2947
                gen_op_fpush();
2948
                gen_op_fmov_ST0_STN((opreg + 1) & 7);
2949
                break;
2950
            case 0x09: /* fxchg sti */
2951
                gen_op_fxchg_ST0_STN(opreg);
2952
                break;
2953
            case 0x0a: /* grp d9/2 */
2954
                switch(rm) {
2955
                case 0: /* fnop */
2956
                    break;
2957
                default:
2958
                    goto illegal_op;
2959
                }
2960
                break;
2961
            case 0x0c: /* grp d9/4 */
2962
                switch(rm) {
2963
                case 0: /* fchs */
2964
                    gen_op_fchs_ST0();
2965
                    break;
2966
                case 1: /* fabs */
2967
                    gen_op_fabs_ST0();
2968
                    break;
2969
                case 4: /* ftst */
2970
                    gen_op_fldz_FT0();
2971
                    gen_op_fcom_ST0_FT0();
2972
                    break;
2973
                case 5: /* fxam */
2974
                    gen_op_fxam_ST0();
2975
                    break;
2976
                default:
2977
                    goto illegal_op;
2978
                }
2979
                break;
2980
            case 0x0d: /* grp d9/5 */
2981
                {
2982
                    switch(rm) {
2983
                    case 0:
2984
                        gen_op_fpush();
2985
                        gen_op_fld1_ST0();
2986
                        break;
2987
                    case 1:
2988
                        gen_op_fpush();
2989
                        gen_op_fldl2t_ST0();
2990
                        break;
2991
                    case 2:
2992
                        gen_op_fpush();
2993
                        gen_op_fldl2e_ST0();
2994
                        break;
2995
                    case 3:
2996
                        gen_op_fpush();
2997
                        gen_op_fldpi_ST0();
2998
                        break;
2999
                    case 4:
3000
                        gen_op_fpush();
3001
                        gen_op_fldlg2_ST0();
3002
                        break;
3003
                    case 5:
3004
                        gen_op_fpush();
3005
                        gen_op_fldln2_ST0();
3006
                        break;
3007
                    case 6:
3008
                        gen_op_fpush();
3009
                        gen_op_fldz_ST0();
3010
                        break;
3011
                    default:
3012
                        goto illegal_op;
3013
                    }
3014
                }
3015
                break;
3016
            case 0x0e: /* grp d9/6 */
3017
                switch(rm) {
3018
                case 0: /* f2xm1 */
3019
                    gen_op_f2xm1();
3020
                    break;
3021
                case 1: /* fyl2x */
3022
                    gen_op_fyl2x();
3023
                    break;
3024
                case 2: /* fptan */
3025
                    gen_op_fptan();
3026
                    break;
3027
                case 3: /* fpatan */
3028
                    gen_op_fpatan();
3029
                    break;
3030
                case 4: /* fxtract */
3031
                    gen_op_fxtract();
3032
                    break;
3033
                case 5: /* fprem1 */
3034
                    gen_op_fprem1();
3035
                    break;
3036
                case 6: /* fdecstp */
3037
                    gen_op_fdecstp();
3038
                    break;
3039
                default:
3040
                case 7: /* fincstp */
3041
                    gen_op_fincstp();
3042
                    break;
3043
                }
3044
                break;
3045
            case 0x0f: /* grp d9/7 */
3046
                switch(rm) {
3047
                case 0: /* fprem */
3048
                    gen_op_fprem();
3049
                    break;
3050
                case 1: /* fyl2xp1 */
3051
                    gen_op_fyl2xp1();
3052
                    break;
3053
                case 2: /* fsqrt */
3054
                    gen_op_fsqrt();
3055
                    break;
3056
                case 3: /* fsincos */
3057
                    gen_op_fsincos();
3058
                    break;
3059
                case 5: /* fscale */
3060
                    gen_op_fscale();
3061
                    break;
3062
                case 4: /* frndint */
3063
                    gen_op_frndint();
3064
                    break;
3065
                case 6: /* fsin */
3066
                    gen_op_fsin();
3067
                    break;
3068
                default:
3069
                case 7: /* fcos */
3070
                    gen_op_fcos();
3071
                    break;
3072
                }
3073
                break;
3074
            case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
3075
            case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
3076
            case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
3077
                {
3078
                    int op1;
3079
                    
3080
                    op1 = op & 7;
3081
                    if (op >= 0x20) {
3082
                        gen_op_fp_arith_STN_ST0[op1](opreg);
3083
                        if (op >= 0x30)
3084
                            gen_op_fpop();
3085
                    } else {
3086
                        gen_op_fmov_FT0_STN(opreg);
3087
                        gen_op_fp_arith_ST0_FT0[op1]();
3088
                    }
3089
                }
3090
                break;
3091
            case 0x02: /* fcom */
3092
                gen_op_fmov_FT0_STN(opreg);
3093
                gen_op_fcom_ST0_FT0();
3094
                break;
3095
            case 0x03: /* fcomp */
3096
                gen_op_fmov_FT0_STN(opreg);
3097
                gen_op_fcom_ST0_FT0();
3098
                gen_op_fpop();
3099
                break;
3100
            case 0x15: /* da/5 */
3101
                switch(rm) {
3102
                case 1: /* fucompp */
3103
                    gen_op_fmov_FT0_STN(1);
3104
                    gen_op_fucom_ST0_FT0();
3105
                    gen_op_fpop();
3106
                    gen_op_fpop();
3107
                    break;
3108
                default:
3109
                    goto illegal_op;
3110
                }
3111
                break;
3112
            case 0x1c:
3113
                switch(rm) {
3114
                case 0: /* feni (287 only, just do nop here) */
3115
                    break;
3116
                case 1: /* fdisi (287 only, just do nop here) */
3117
                    break;
3118
                case 2: /* fclex */
3119
                    gen_op_fclex();
3120
                    break;
3121
                case 3: /* fninit */
3122
                    gen_op_fninit();
3123
                    break;
3124
                case 4: /* fsetpm (287 only, just do nop here) */
3125
                    break;
3126
                default:
3127
                    goto illegal_op;
3128
                }
3129
                break;
3130
            case 0x1d: /* fucomi */
3131
                if (s->cc_op != CC_OP_DYNAMIC)
3132
                    gen_op_set_cc_op(s->cc_op);
3133
                gen_op_fmov_FT0_STN(opreg);
3134
                gen_op_fucomi_ST0_FT0();
3135
                s->cc_op = CC_OP_EFLAGS;
3136
                break;
3137
            case 0x1e: /* fcomi */
3138
                if (s->cc_op != CC_OP_DYNAMIC)
3139
                    gen_op_set_cc_op(s->cc_op);
3140
                gen_op_fmov_FT0_STN(opreg);
3141
                gen_op_fcomi_ST0_FT0();
3142
                s->cc_op = CC_OP_EFLAGS;
3143
                break;
3144
            case 0x2a: /* fst sti */
3145
                gen_op_fmov_STN_ST0(opreg);
3146
                break;
3147
            case 0x2b: /* fstp sti */
3148
                gen_op_fmov_STN_ST0(opreg);
3149
                gen_op_fpop();
3150
                break;
3151
            case 0x2c: /* fucom st(i) */
3152
                gen_op_fmov_FT0_STN(opreg);
3153
                gen_op_fucom_ST0_FT0();
3154
                break;
3155
            case 0x2d: /* fucomp st(i) */
3156
                gen_op_fmov_FT0_STN(opreg);
3157
                gen_op_fucom_ST0_FT0();
3158
                gen_op_fpop();
3159
                break;
3160
            case 0x33: /* de/3 */
3161
                switch(rm) {
3162
                case 1: /* fcompp */
3163
                    gen_op_fmov_FT0_STN(1);
3164
                    gen_op_fcom_ST0_FT0();
3165
                    gen_op_fpop();
3166
                    gen_op_fpop();
3167
                    break;
3168
                default:
3169
                    goto illegal_op;
3170
                }
3171
                break;
3172
            case 0x3c: /* df/4 */
3173
                switch(rm) {
3174
                case 0:
3175
                    gen_op_fnstsw_EAX();
3176
                    break;
3177
                default:
3178
                    goto illegal_op;
3179
                }
3180
                break;
3181
            case 0x3d: /* fucomip */
3182
                if (s->cc_op != CC_OP_DYNAMIC)
3183
                    gen_op_set_cc_op(s->cc_op);
3184
                gen_op_fmov_FT0_STN(opreg);
3185
                gen_op_fucomi_ST0_FT0();
3186
                gen_op_fpop();
3187
                s->cc_op = CC_OP_EFLAGS;
3188
                break;
3189
            case 0x3e: /* fcomip */
3190
                if (s->cc_op != CC_OP_DYNAMIC)
3191
                    gen_op_set_cc_op(s->cc_op);
3192
                gen_op_fmov_FT0_STN(opreg);
3193
                gen_op_fcomi_ST0_FT0();
3194
                gen_op_fpop();
3195
                s->cc_op = CC_OP_EFLAGS;
3196
                break;
3197
            case 0x10 ... 0x13: /* fcmovxx */
3198
            case 0x18 ... 0x1b:
3199
                {
3200
                    int op1;
3201
                    const static uint8_t fcmov_cc[8] = {
3202
                        (JCC_B << 1),
3203
                        (JCC_Z << 1),
3204
                        (JCC_BE << 1),
3205
                        (JCC_P << 1),
3206
                    };
3207
                    op1 = fcmov_cc[op & 3] | ((op >> 3) & 1);
3208
                    gen_setcc(s, op1);
3209
                    gen_op_fcmov_ST0_STN_T0(opreg);
3210
                }
3211
                break;
3212
            default:
3213
                goto illegal_op;
3214
            }
3215
        }
3216
        break;
3217
        /************************/
3218
        /* string ops */
3219

    
3220
    case 0xa4: /* movsS */
3221
    case 0xa5:
3222
        if ((b & 1) == 0)
3223
            ot = OT_BYTE;
3224
        else
3225
            ot = dflag ? OT_LONG : OT_WORD;
3226

    
3227
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3228
            gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3229
        } else {
3230
            gen_movs(s, ot);
3231
        }
3232
        break;
3233
        
3234
    case 0xaa: /* stosS */
3235
    case 0xab:
3236
        if ((b & 1) == 0)
3237
            ot = OT_BYTE;
3238
        else
3239
            ot = dflag ? OT_LONG : OT_WORD;
3240

    
3241
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3242
            gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3243
        } else {
3244
            gen_stos(s, ot);
3245
        }
3246
        break;
3247
    case 0xac: /* lodsS */
3248
    case 0xad:
3249
        if ((b & 1) == 0)
3250
            ot = OT_BYTE;
3251
        else
3252
            ot = dflag ? OT_LONG : OT_WORD;
3253
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3254
            gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3255
        } else {
3256
            gen_lods(s, ot);
3257
        }
3258
        break;
3259
    case 0xae: /* scasS */
3260
    case 0xaf:
3261
        if ((b & 1) == 0)
3262
            ot = OT_BYTE;
3263
        else
3264
                ot = dflag ? OT_LONG : OT_WORD;
3265
        if (prefixes & PREFIX_REPNZ) {
3266
            gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3267
        } else if (prefixes & PREFIX_REPZ) {
3268
            gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3269
        } else {
3270
            gen_scas(s, ot);
3271
            s->cc_op = CC_OP_SUBB + ot;
3272
        }
3273
        break;
3274

    
3275
    case 0xa6: /* cmpsS */
3276
    case 0xa7:
3277
        if ((b & 1) == 0)
3278
            ot = OT_BYTE;
3279
        else
3280
            ot = dflag ? OT_LONG : OT_WORD;
3281
        if (prefixes & PREFIX_REPNZ) {
3282
            gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
3283
        } else if (prefixes & PREFIX_REPZ) {
3284
            gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
3285
        } else {
3286
            gen_cmps(s, ot);
3287
            s->cc_op = CC_OP_SUBB + ot;
3288
        }
3289
        break;
3290
    case 0x6c: /* insS */
3291
    case 0x6d:
3292
        if ((b & 1) == 0)
3293
            ot = OT_BYTE;
3294
        else
3295
            ot = dflag ? OT_LONG : OT_WORD;
3296
        gen_check_io(s, ot, 1, pc_start - s->cs_base);
3297
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3298
            gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3299
        } else {
3300
            gen_ins(s, ot);
3301
        }
3302
        break;
3303
    case 0x6e: /* outsS */
3304
    case 0x6f:
3305
        if ((b & 1) == 0)
3306
            ot = OT_BYTE;
3307
        else
3308
            ot = dflag ? OT_LONG : OT_WORD;
3309
        gen_check_io(s, ot, 1, pc_start - s->cs_base);
3310
        if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
3311
            gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
3312
        } else {
3313
            gen_outs(s, ot);
3314
        }
3315
        break;
3316

    
3317
        /************************/
3318
        /* port I/O */
3319
    case 0xe4:
3320
    case 0xe5:
3321
        if ((b & 1) == 0)
3322
            ot = OT_BYTE;
3323
        else
3324
            ot = dflag ? OT_LONG : OT_WORD;
3325
        val = ldub_code(s->pc++);
3326
        gen_op_movl_T0_im(val);
3327
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3328
        gen_op_in[ot]();
3329
        gen_op_mov_reg_T1[ot][R_EAX]();
3330
        break;
3331
    case 0xe6:
3332
    case 0xe7:
3333
        if ((b & 1) == 0)
3334
            ot = OT_BYTE;
3335
        else
3336
            ot = dflag ? OT_LONG : OT_WORD;
3337
        val = ldub_code(s->pc++);
3338
        gen_op_movl_T0_im(val);
3339
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3340
        gen_op_mov_TN_reg[ot][1][R_EAX]();
3341
        gen_op_out[ot]();
3342
        break;
3343
    case 0xec:
3344
    case 0xed:
3345
        if ((b & 1) == 0)
3346
            ot = OT_BYTE;
3347
        else
3348
            ot = dflag ? OT_LONG : OT_WORD;
3349
        gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3350
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3351
        gen_op_in[ot]();
3352
        gen_op_mov_reg_T1[ot][R_EAX]();
3353
        break;
3354
    case 0xee:
3355
    case 0xef:
3356
        if ((b & 1) == 0)
3357
            ot = OT_BYTE;
3358
        else
3359
            ot = dflag ? OT_LONG : OT_WORD;
3360
        gen_op_mov_TN_reg[OT_WORD][0][R_EDX]();
3361
        gen_check_io(s, ot, 0, pc_start - s->cs_base);
3362
        gen_op_mov_TN_reg[ot][1][R_EAX]();
3363
        gen_op_out[ot]();
3364
        break;
3365

    
3366
        /************************/
3367
        /* control */
3368
    case 0xc2: /* ret im */
3369
        val = ldsw_code(s->pc);
3370
        s->pc += 2;
3371
        gen_pop_T0(s);
3372
        gen_stack_update(s, val + (2 << s->dflag));
3373
        if (s->dflag == 0)
3374
            gen_op_andl_T0_ffff();
3375
        gen_op_jmp_T0();
3376
        gen_eob(s);
3377
        break;
3378
    case 0xc3: /* ret */
3379
        gen_pop_T0(s);
3380
        gen_pop_update(s);
3381
        if (s->dflag == 0)
3382
            gen_op_andl_T0_ffff();
3383
        gen_op_jmp_T0();
3384
        gen_eob(s);
3385
        break;
3386
    case 0xca: /* lret im */
3387
        val = ldsw_code(s->pc);
3388
        s->pc += 2;
3389
    do_lret:
3390
        if (s->pe && !s->vm86) {
3391
            if (s->cc_op != CC_OP_DYNAMIC)
3392
                gen_op_set_cc_op(s->cc_op);
3393
            gen_op_jmp_im(pc_start - s->cs_base);
3394
            gen_op_lret_protected(s->dflag, val);
3395
        } else {
3396
            gen_stack_A0(s);
3397
            /* pop offset */
3398
            gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3399
            if (s->dflag == 0)
3400
                gen_op_andl_T0_ffff();
3401
            /* NOTE: keeping EIP updated is not a problem in case of
3402
               exception */
3403
            gen_op_jmp_T0();
3404
            /* pop selector */
3405
            gen_op_addl_A0_im(2 << s->dflag);
3406
            gen_op_ld_T0_A0[1 + s->dflag + s->mem_index]();
3407
            gen_op_movl_seg_T0_vm(offsetof(CPUX86State,segs[R_CS]));
3408
            /* add stack offset */
3409
            gen_stack_update(s, val + (4 << s->dflag));
3410
        }
3411
        gen_eob(s);
3412
        break;
3413
    case 0xcb: /* lret */
3414
        val = 0;
3415
        goto do_lret;
3416
    case 0xcf: /* iret */
3417
        if (!s->pe) {
3418
            /* real mode */
3419
            gen_op_iret_real(s->dflag);
3420
            s->cc_op = CC_OP_EFLAGS;
3421
        } else if (s->vm86) {
3422
            if (s->iopl != 3) {
3423
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3424
            } else {
3425
                gen_op_iret_real(s->dflag);
3426
                s->cc_op = CC_OP_EFLAGS;
3427
            }
3428
        } else {
3429
            if (s->cc_op != CC_OP_DYNAMIC)
3430
                gen_op_set_cc_op(s->cc_op);
3431
            gen_op_jmp_im(pc_start - s->cs_base);
3432
            gen_op_iret_protected(s->dflag);
3433
            s->cc_op = CC_OP_EFLAGS;
3434
        }
3435
        gen_eob(s);
3436
        break;
3437
    case 0xe8: /* call im */
3438
        {
3439
            unsigned int next_eip;
3440
            ot = dflag ? OT_LONG : OT_WORD;
3441
            val = insn_get(s, ot);
3442
            next_eip = s->pc - s->cs_base;
3443
            val += next_eip;
3444
            if (s->dflag == 0)
3445
                val &= 0xffff;
3446
            gen_op_movl_T0_im(next_eip);
3447
            gen_push_T0(s);
3448
            gen_jmp(s, val);
3449
        }
3450
        break;
3451
    case 0x9a: /* lcall im */
3452
        {
3453
            unsigned int selector, offset;
3454

    
3455
            ot = dflag ? OT_LONG : OT_WORD;
3456
            offset = insn_get(s, ot);
3457
            selector = insn_get(s, OT_WORD);
3458
            
3459
            gen_op_movl_T0_im(selector);
3460
            gen_op_movl_T1_im(offset);
3461
        }
3462
        goto do_lcall;
3463
    case 0xe9: /* jmp */
3464
        ot = dflag ? OT_LONG : OT_WORD;
3465
        val = insn_get(s, ot);
3466
        val += s->pc - s->cs_base;
3467
        if (s->dflag == 0)
3468
            val = val & 0xffff;
3469
        gen_jmp(s, val);
3470
        break;
3471
    case 0xea: /* ljmp im */
3472
        {
3473
            unsigned int selector, offset;
3474

    
3475
            ot = dflag ? OT_LONG : OT_WORD;
3476
            offset = insn_get(s, ot);
3477
            selector = insn_get(s, OT_WORD);
3478
            
3479
            gen_op_movl_T0_im(selector);
3480
            gen_op_movl_T1_im(offset);
3481
        }
3482
        goto do_ljmp;
3483
    case 0xeb: /* jmp Jb */
3484
        val = (int8_t)insn_get(s, OT_BYTE);
3485
        val += s->pc - s->cs_base;
3486
        if (s->dflag == 0)
3487
            val = val & 0xffff;
3488
        gen_jmp(s, val);
3489
        break;
3490
    case 0x70 ... 0x7f: /* jcc Jb */
3491
        val = (int8_t)insn_get(s, OT_BYTE);
3492
        goto do_jcc;
3493
    case 0x180 ... 0x18f: /* jcc Jv */
3494
        if (dflag) {
3495
            val = insn_get(s, OT_LONG);
3496
        } else {
3497
            val = (int16_t)insn_get(s, OT_WORD); 
3498
        }
3499
    do_jcc:
3500
        next_eip = s->pc - s->cs_base;
3501
        val += next_eip;
3502
        if (s->dflag == 0)
3503
            val &= 0xffff;
3504
        gen_jcc(s, b, val, next_eip);
3505
        break;
3506

    
3507
    case 0x190 ... 0x19f: /* setcc Gv */
3508
        modrm = ldub_code(s->pc++);
3509
        gen_setcc(s, b);
3510
        gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
3511
        break;
3512
    case 0x140 ... 0x14f: /* cmov Gv, Ev */
3513
        ot = dflag ? OT_LONG : OT_WORD;
3514
        modrm = ldub_code(s->pc++);
3515
        reg = (modrm >> 3) & 7;
3516
        mod = (modrm >> 6) & 3;
3517
        gen_setcc(s, b);
3518
        if (mod != 3) {
3519
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3520
            gen_op_ld_T1_A0[ot + s->mem_index]();
3521
        } else {
3522
            rm = modrm & 7;
3523
            gen_op_mov_TN_reg[ot][1][rm]();
3524
        }
3525
        gen_op_cmov_reg_T1_T0[ot - OT_WORD][reg]();
3526
        break;
3527
        
3528
        /************************/
3529
        /* flags */
3530
    case 0x9c: /* pushf */
3531
        if (s->vm86 && s->iopl != 3) {
3532
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3533
        } else {
3534
            if (s->cc_op != CC_OP_DYNAMIC)
3535
                gen_op_set_cc_op(s->cc_op);
3536
            gen_op_movl_T0_eflags();
3537
            gen_push_T0(s);
3538
        }
3539
        break;
3540
    case 0x9d: /* popf */
3541
        if (s->vm86 && s->iopl != 3) {
3542
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3543
        } else {
3544
            gen_pop_T0(s);
3545
            if (s->cpl == 0) {
3546
                if (s->dflag) {
3547
                    gen_op_movl_eflags_T0_cpl0();
3548
                } else {
3549
                    gen_op_movw_eflags_T0_cpl0();
3550
                }
3551
            } else {
3552
                if (s->cpl <= s->iopl) {
3553
                    if (s->dflag) {
3554
                        gen_op_movl_eflags_T0_io();
3555
                    } else {
3556
                        gen_op_movw_eflags_T0_io();
3557
                    }
3558
                } else {
3559
                    if (s->dflag) {
3560
                        gen_op_movl_eflags_T0();
3561
                    } else {
3562
                        gen_op_movw_eflags_T0();
3563
                    }
3564
                }
3565
            }
3566
            gen_pop_update(s);
3567
            s->cc_op = CC_OP_EFLAGS;
3568
            /* abort translation because TF flag may change */
3569
            gen_op_jmp_im(s->pc - s->cs_base);
3570
            gen_eob(s);
3571
        }
3572
        break;
3573
    case 0x9e: /* sahf */
3574
        gen_op_mov_TN_reg[OT_BYTE][0][R_AH]();
3575
        if (s->cc_op != CC_OP_DYNAMIC)
3576
            gen_op_set_cc_op(s->cc_op);
3577
        gen_op_movb_eflags_T0();
3578
        s->cc_op = CC_OP_EFLAGS;
3579
        break;
3580
    case 0x9f: /* lahf */
3581
        if (s->cc_op != CC_OP_DYNAMIC)
3582
            gen_op_set_cc_op(s->cc_op);
3583
        gen_op_movl_T0_eflags();
3584
        gen_op_mov_reg_T0[OT_BYTE][R_AH]();
3585
        break;
3586
    case 0xf5: /* cmc */
3587
        if (s->cc_op != CC_OP_DYNAMIC)
3588
            gen_op_set_cc_op(s->cc_op);
3589
        gen_op_cmc();
3590
        s->cc_op = CC_OP_EFLAGS;
3591
        break;
3592
    case 0xf8: /* clc */
3593
        if (s->cc_op != CC_OP_DYNAMIC)
3594
            gen_op_set_cc_op(s->cc_op);
3595
        gen_op_clc();
3596
        s->cc_op = CC_OP_EFLAGS;
3597
        break;
3598
    case 0xf9: /* stc */
3599
        if (s->cc_op != CC_OP_DYNAMIC)
3600
            gen_op_set_cc_op(s->cc_op);
3601
        gen_op_stc();
3602
        s->cc_op = CC_OP_EFLAGS;
3603
        break;
3604
    case 0xfc: /* cld */
3605
        gen_op_cld();
3606
        break;
3607
    case 0xfd: /* std */
3608
        gen_op_std();
3609
        break;
3610

    
3611
        /************************/
3612
        /* bit operations */
3613
    case 0x1ba: /* bt/bts/btr/btc Gv, im */
3614
        ot = dflag ? OT_LONG : OT_WORD;
3615
        modrm = ldub_code(s->pc++);
3616
        op = (modrm >> 3) & 7;
3617
        mod = (modrm >> 6) & 3;
3618
        rm = modrm & 7;
3619
        if (mod != 3) {
3620
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3621
            gen_op_ld_T0_A0[ot + s->mem_index]();
3622
        } else {
3623
            gen_op_mov_TN_reg[ot][0][rm]();
3624
        }
3625
        /* load shift */
3626
        val = ldub_code(s->pc++);
3627
        gen_op_movl_T1_im(val);
3628
        if (op < 4)
3629
            goto illegal_op;
3630
        op -= 4;
3631
        gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3632
        s->cc_op = CC_OP_SARB + ot;
3633
        if (op != 0) {
3634
            if (mod != 3)
3635
                gen_op_st_T0_A0[ot + s->mem_index]();
3636
            else
3637
                gen_op_mov_reg_T0[ot][rm]();
3638
            gen_op_update_bt_cc();
3639
        }
3640
        break;
3641
    case 0x1a3: /* bt Gv, Ev */
3642
        op = 0;
3643
        goto do_btx;
3644
    case 0x1ab: /* bts */
3645
        op = 1;
3646
        goto do_btx;
3647
    case 0x1b3: /* btr */
3648
        op = 2;
3649
        goto do_btx;
3650
    case 0x1bb: /* btc */
3651
        op = 3;
3652
    do_btx:
3653
        ot = dflag ? OT_LONG : OT_WORD;
3654
        modrm = ldub_code(s->pc++);
3655
        reg = (modrm >> 3) & 7;
3656
        mod = (modrm >> 6) & 3;
3657
        rm = modrm & 7;
3658
        gen_op_mov_TN_reg[OT_LONG][1][reg]();
3659
        if (mod != 3) {
3660
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3661
            /* specific case: we need to add a displacement */
3662
            if (ot == OT_WORD)
3663
                gen_op_add_bitw_A0_T1();
3664
            else
3665
                gen_op_add_bitl_A0_T1();
3666
            gen_op_ld_T0_A0[ot + s->mem_index]();
3667
        } else {
3668
            gen_op_mov_TN_reg[ot][0][rm]();
3669
        }
3670
        gen_op_btx_T0_T1_cc[ot - OT_WORD][op]();
3671
        s->cc_op = CC_OP_SARB + ot;
3672
        if (op != 0) {
3673
            if (mod != 3)
3674
                gen_op_st_T0_A0[ot + s->mem_index]();
3675
            else
3676
                gen_op_mov_reg_T0[ot][rm]();
3677
            gen_op_update_bt_cc();
3678
        }
3679
        break;
3680
    case 0x1bc: /* bsf */
3681
    case 0x1bd: /* bsr */
3682
        ot = dflag ? OT_LONG : OT_WORD;
3683
        modrm = ldub_code(s->pc++);
3684
        reg = (modrm >> 3) & 7;
3685
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3686
        gen_op_bsx_T0_cc[ot - OT_WORD][b & 1]();
3687
        /* NOTE: we always write back the result. Intel doc says it is
3688
           undefined if T0 == 0 */
3689
        gen_op_mov_reg_T0[ot][reg]();
3690
        s->cc_op = CC_OP_LOGICB + ot;
3691
        break;
3692
        /************************/
3693
        /* bcd */
3694
    case 0x27: /* daa */
3695
        if (s->cc_op != CC_OP_DYNAMIC)
3696
            gen_op_set_cc_op(s->cc_op);
3697
        gen_op_daa();
3698
        s->cc_op = CC_OP_EFLAGS;
3699
        break;
3700
    case 0x2f: /* das */
3701
        if (s->cc_op != CC_OP_DYNAMIC)
3702
            gen_op_set_cc_op(s->cc_op);
3703
        gen_op_das();
3704
        s->cc_op = CC_OP_EFLAGS;
3705
        break;
3706
    case 0x37: /* aaa */
3707
        if (s->cc_op != CC_OP_DYNAMIC)
3708
            gen_op_set_cc_op(s->cc_op);
3709
        gen_op_aaa();
3710
        s->cc_op = CC_OP_EFLAGS;
3711
        break;
3712
    case 0x3f: /* aas */
3713
        if (s->cc_op != CC_OP_DYNAMIC)
3714
            gen_op_set_cc_op(s->cc_op);
3715
        gen_op_aas();
3716
        s->cc_op = CC_OP_EFLAGS;
3717
        break;
3718
    case 0xd4: /* aam */
3719
        val = ldub_code(s->pc++);
3720
        gen_op_aam(val);
3721
        s->cc_op = CC_OP_LOGICB;
3722
        break;
3723
    case 0xd5: /* aad */
3724
        val = ldub_code(s->pc++);
3725
        gen_op_aad(val);
3726
        s->cc_op = CC_OP_LOGICB;
3727
        break;
3728
        /************************/
3729
        /* misc */
3730
    case 0x90: /* nop */
3731
        break;
3732
    case 0x9b: /* fwait */
3733
        break;
3734
    case 0xcc: /* int3 */
3735
        gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
3736
        break;
3737
    case 0xcd: /* int N */
3738
        val = ldub_code(s->pc++);
3739
        if (s->vm86 && s->iopl != 3) {
3740
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base); 
3741
        } else {
3742
            gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
3743
        }
3744
        break;
3745
    case 0xce: /* into */
3746
        if (s->cc_op != CC_OP_DYNAMIC)
3747
            gen_op_set_cc_op(s->cc_op);
3748
        gen_op_into(s->pc - s->cs_base);
3749
        break;
3750
    case 0xf1: /* icebp (undocumented, exits to external debugger) */
3751
        gen_debug(s, pc_start - s->cs_base);
3752
        break;
3753
    case 0xfa: /* cli */
3754
        if (!s->vm86) {
3755
            if (s->cpl <= s->iopl) {
3756
                gen_op_cli();
3757
            } else {
3758
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3759
            }
3760
        } else {
3761
            if (s->iopl == 3) {
3762
                gen_op_cli();
3763
            } else {
3764
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3765
            }
3766
        }
3767
        break;
3768
    case 0xfb: /* sti */
3769
        if (!s->vm86) {
3770
            if (s->cpl <= s->iopl) {
3771
            gen_sti:
3772
                gen_op_sti();
3773
                /* interruptions are enabled only the first insn after sti */
3774
                /* If several instructions disable interrupts, only the
3775
                   _first_ does it */
3776
                if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
3777
                    gen_op_set_inhibit_irq();
3778
                /* give a chance to handle pending irqs */
3779
                gen_op_jmp_im(s->pc - s->cs_base);
3780
                gen_eob(s);
3781
            } else {
3782
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3783
            }
3784
        } else {
3785
            if (s->iopl == 3) {
3786
                goto gen_sti;
3787
            } else {
3788
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3789
            }
3790
        }
3791
        break;
3792
    case 0x62: /* bound */
3793
        ot = dflag ? OT_LONG : OT_WORD;
3794
        modrm = ldub_code(s->pc++);
3795
        reg = (modrm >> 3) & 7;
3796
        mod = (modrm >> 6) & 3;
3797
        if (mod == 3)
3798
            goto illegal_op;
3799
        gen_op_mov_reg_T0[ot][reg]();
3800
        gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3801
        if (ot == OT_WORD)
3802
            gen_op_boundw(pc_start - s->cs_base);
3803
        else
3804
            gen_op_boundl(pc_start - s->cs_base);
3805
        break;
3806
    case 0x1c8 ... 0x1cf: /* bswap reg */
3807
        reg = b & 7;
3808
        gen_op_mov_TN_reg[OT_LONG][0][reg]();
3809
        gen_op_bswapl_T0();
3810
        gen_op_mov_reg_T0[OT_LONG][reg]();
3811
        break;
3812
    case 0xd6: /* salc */
3813
        if (s->cc_op != CC_OP_DYNAMIC)
3814
            gen_op_set_cc_op(s->cc_op);
3815
        gen_op_salc();
3816
        break;
3817
    case 0xe0: /* loopnz */
3818
    case 0xe1: /* loopz */
3819
        if (s->cc_op != CC_OP_DYNAMIC)
3820
            gen_op_set_cc_op(s->cc_op);
3821
        /* FALL THRU */
3822
    case 0xe2: /* loop */
3823
    case 0xe3: /* jecxz */
3824
        val = (int8_t)insn_get(s, OT_BYTE);
3825
        next_eip = s->pc - s->cs_base;
3826
        val += next_eip;
3827
        if (s->dflag == 0)
3828
            val &= 0xffff;
3829
        gen_op_loop[s->aflag][b & 3](val, next_eip);
3830
        gen_eob(s);
3831
        break;
3832
    case 0x130: /* wrmsr */
3833
    case 0x132: /* rdmsr */
3834
        if (s->cpl != 0) {
3835
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3836
        } else {
3837
            if (b & 2)
3838
                gen_op_rdmsr();
3839
            else
3840
                gen_op_wrmsr();
3841
        }
3842
        break;
3843
    case 0x131: /* rdtsc */
3844
        gen_op_rdtsc();
3845
        break;
3846
    case 0x1a2: /* cpuid */
3847
        gen_op_cpuid();
3848
        break;
3849
    case 0xf4: /* hlt */
3850
        if (s->cpl != 0) {
3851
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3852
        } else {
3853
            if (s->cc_op != CC_OP_DYNAMIC)
3854
                gen_op_set_cc_op(s->cc_op);
3855
            gen_op_jmp_im(s->pc - s->cs_base);
3856
            gen_op_hlt();
3857
            s->is_jmp = 3;
3858
        }
3859
        break;
3860
    case 0x100:
3861
        modrm = ldub_code(s->pc++);
3862
        mod = (modrm >> 6) & 3;
3863
        op = (modrm >> 3) & 7;
3864
        switch(op) {
3865
        case 0: /* sldt */
3866
            if (!s->pe || s->vm86)
3867
                goto illegal_op;
3868
            gen_op_movl_T0_env(offsetof(CPUX86State,ldt.selector));
3869
            ot = OT_WORD;
3870
            if (mod == 3)
3871
                ot += s->dflag;
3872
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3873
            break;
3874
        case 2: /* lldt */
3875
            if (!s->pe || s->vm86)
3876
                goto illegal_op;
3877
            if (s->cpl != 0) {
3878
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3879
            } else {
3880
                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3881
                gen_op_jmp_im(pc_start - s->cs_base);
3882
                gen_op_lldt_T0();
3883
            }
3884
            break;
3885
        case 1: /* str */
3886
            if (!s->pe || s->vm86)
3887
                goto illegal_op;
3888
            gen_op_movl_T0_env(offsetof(CPUX86State,tr.selector));
3889
            ot = OT_WORD;
3890
            if (mod == 3)
3891
                ot += s->dflag;
3892
            gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
3893
            break;
3894
        case 3: /* ltr */
3895
            if (!s->pe || s->vm86)
3896
                goto illegal_op;
3897
            if (s->cpl != 0) {
3898
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3899
            } else {
3900
                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3901
                gen_op_jmp_im(pc_start - s->cs_base);
3902
                gen_op_ltr_T0();
3903
            }
3904
            break;
3905
        case 4: /* verr */
3906
        case 5: /* verw */
3907
            if (!s->pe || s->vm86)
3908
                goto illegal_op;
3909
            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3910
            if (s->cc_op != CC_OP_DYNAMIC)
3911
                gen_op_set_cc_op(s->cc_op);
3912
            if (op == 4)
3913
                gen_op_verr();
3914
            else
3915
                gen_op_verw();
3916
            s->cc_op = CC_OP_EFLAGS;
3917
            break;
3918
        default:
3919
            goto illegal_op;
3920
        }
3921
        break;
3922
    case 0x101:
3923
        modrm = ldub_code(s->pc++);
3924
        mod = (modrm >> 6) & 3;
3925
        op = (modrm >> 3) & 7;
3926
        switch(op) {
3927
        case 0: /* sgdt */
3928
        case 1: /* sidt */
3929
            if (mod == 3)
3930
                goto illegal_op;
3931
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3932
            if (op == 0)
3933
                gen_op_movl_T0_env(offsetof(CPUX86State,gdt.limit));
3934
            else
3935
                gen_op_movl_T0_env(offsetof(CPUX86State,idt.limit));
3936
            gen_op_st_T0_A0[OT_WORD + s->mem_index]();
3937
            gen_op_addl_A0_im(2);
3938
            if (op == 0)
3939
                gen_op_movl_T0_env(offsetof(CPUX86State,gdt.base));
3940
            else
3941
                gen_op_movl_T0_env(offsetof(CPUX86State,idt.base));
3942
            if (!s->dflag)
3943
                gen_op_andl_T0_im(0xffffff);
3944
            gen_op_st_T0_A0[OT_LONG + s->mem_index]();
3945
            break;
3946
        case 2: /* lgdt */
3947
        case 3: /* lidt */
3948
            if (mod == 3)
3949
                goto illegal_op;
3950
            if (s->cpl != 0) {
3951
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3952
            } else {
3953
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3954
                gen_op_ld_T1_A0[OT_WORD + s->mem_index]();
3955
                gen_op_addl_A0_im(2);
3956
                gen_op_ld_T0_A0[OT_LONG + s->mem_index]();
3957
                if (!s->dflag)
3958
                    gen_op_andl_T0_im(0xffffff);
3959
                if (op == 2) {
3960
                    gen_op_movl_env_T0(offsetof(CPUX86State,gdt.base));
3961
                    gen_op_movl_env_T1(offsetof(CPUX86State,gdt.limit));
3962
                } else {
3963
                    gen_op_movl_env_T0(offsetof(CPUX86State,idt.base));
3964
                    gen_op_movl_env_T1(offsetof(CPUX86State,idt.limit));
3965
                }
3966
            }
3967
            break;
3968
        case 4: /* smsw */
3969
            gen_op_movl_T0_env(offsetof(CPUX86State,cr[0]));
3970
            gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
3971
            break;
3972
        case 6: /* lmsw */
3973
            if (s->cpl != 0) {
3974
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3975
            } else {
3976
                gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3977
                gen_op_lmsw_T0();
3978
                gen_op_jmp_im(s->pc - s->cs_base);
3979
                gen_eob(s);
3980
            }
3981
            break;
3982
        case 7: /* invlpg */
3983
            if (s->cpl != 0) {
3984
                gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
3985
            } else {
3986
                if (mod == 3)
3987
                    goto illegal_op;
3988
                gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3989
                gen_op_invlpg_A0();
3990
                gen_op_jmp_im(s->pc - s->cs_base);
3991
                gen_eob(s);
3992
            }
3993
            break;
3994
        default:
3995
            goto illegal_op;
3996
        }
3997
        break;
3998
    case 0x108: /* invd */
3999
    case 0x109: /* wbinvd */
4000
        if (s->cpl != 0) {
4001
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4002
        } else {
4003
            /* nothing to do */
4004
        }
4005
        break;
4006
    case 0x63: /* arpl */
4007
        if (!s->pe || s->vm86)
4008
            goto illegal_op;
4009
        ot = dflag ? OT_LONG : OT_WORD;
4010
        modrm = ldub_code(s->pc++);
4011
        reg = (modrm >> 3) & 7;
4012
        mod = (modrm >> 6) & 3;
4013
        rm = modrm & 7;
4014
        if (mod != 3) {
4015
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4016
            gen_op_ld_T0_A0[ot + s->mem_index]();
4017
        } else {
4018
            gen_op_mov_TN_reg[ot][0][rm]();
4019
        }
4020
        if (s->cc_op != CC_OP_DYNAMIC)
4021
            gen_op_set_cc_op(s->cc_op);
4022
        gen_op_arpl();
4023
        s->cc_op = CC_OP_EFLAGS;
4024
        if (mod != 3) {
4025
            gen_op_st_T0_A0[ot + s->mem_index]();
4026
        } else {
4027
            gen_op_mov_reg_T0[ot][rm]();
4028
        }
4029
        gen_op_arpl_update();
4030
        break;
4031
    case 0x102: /* lar */
4032
    case 0x103: /* lsl */
4033
        if (!s->pe || s->vm86)
4034
            goto illegal_op;
4035
        ot = dflag ? OT_LONG : OT_WORD;
4036
        modrm = ldub_code(s->pc++);
4037
        reg = (modrm >> 3) & 7;
4038
        gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4039
        gen_op_mov_TN_reg[ot][1][reg]();
4040
        if (s->cc_op != CC_OP_DYNAMIC)
4041
            gen_op_set_cc_op(s->cc_op);
4042
        if (b == 0x102)
4043
            gen_op_lar();
4044
        else
4045
            gen_op_lsl();
4046
        s->cc_op = CC_OP_EFLAGS;
4047
        gen_op_mov_reg_T1[ot][reg]();
4048
        break;
4049
    case 0x118:
4050
        modrm = ldub_code(s->pc++);
4051
        mod = (modrm >> 6) & 3;
4052
        op = (modrm >> 3) & 7;
4053
        switch(op) {
4054
        case 0: /* prefetchnta */
4055
        case 1: /* prefetchnt0 */
4056
        case 2: /* prefetchnt0 */
4057
        case 3: /* prefetchnt0 */
4058
            if (mod == 3)
4059
                goto illegal_op;
4060
            gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4061
            /* nothing more to do */
4062
            break;
4063
        default:
4064
            goto illegal_op;
4065
        }
4066
        break;
4067
    case 0x120: /* mov reg, crN */
4068
    case 0x122: /* mov crN, reg */
4069
        if (s->cpl != 0) {
4070
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4071
        } else {
4072
            modrm = ldub_code(s->pc++);
4073
            if ((modrm & 0xc0) != 0xc0)
4074
                goto illegal_op;
4075
            rm = modrm & 7;
4076
            reg = (modrm >> 3) & 7;
4077
            switch(reg) {
4078
            case 0:
4079
            case 2:
4080
            case 3:
4081
            case 4:
4082
                if (b & 2) {
4083
                    gen_op_mov_TN_reg[OT_LONG][0][rm]();
4084
                    gen_op_movl_crN_T0(reg);
4085
                    gen_op_jmp_im(s->pc - s->cs_base);
4086
                    gen_eob(s);
4087
                } else {
4088
                    gen_op_movl_T0_env(offsetof(CPUX86State,cr[reg]));
4089
                    gen_op_mov_reg_T0[OT_LONG][rm]();
4090
                }
4091
                break;
4092
            default:
4093
                goto illegal_op;
4094
            }
4095
        }
4096
        break;
4097
    case 0x121: /* mov reg, drN */
4098
    case 0x123: /* mov drN, reg */
4099
        if (s->cpl != 0) {
4100
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4101
        } else {
4102
            modrm = ldub_code(s->pc++);
4103
            if ((modrm & 0xc0) != 0xc0)
4104
                goto illegal_op;
4105
            rm = modrm & 7;
4106
            reg = (modrm >> 3) & 7;
4107
            /* XXX: do it dynamically with CR4.DE bit */
4108
            if (reg == 4 || reg == 5)
4109
                goto illegal_op;
4110
            if (b & 2) {
4111
                gen_op_mov_TN_reg[OT_LONG][0][rm]();
4112
                gen_op_movl_drN_T0(reg);
4113
                gen_op_jmp_im(s->pc - s->cs_base);
4114
                gen_eob(s);
4115
            } else {
4116
                gen_op_movl_T0_env(offsetof(CPUX86State,dr[reg]));
4117
                gen_op_mov_reg_T0[OT_LONG][rm]();
4118
            }
4119
        }
4120
        break;
4121
    case 0x106: /* clts */
4122
        if (s->cpl != 0) {
4123
            gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
4124
        } else {
4125
            gen_op_clts();
4126
        }
4127
        break;
4128
    default:
4129
        goto illegal_op;
4130
    }
4131
    /* lock generation */
4132
    if (s->prefix & PREFIX_LOCK)
4133
        gen_op_unlock();
4134
    return s->pc;
4135
 illegal_op:
4136
    /* XXX: ensure that no lock was generated */
4137
    gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
4138
    return s->pc;
4139
}
4140

    
4141
#define CC_OSZAPC (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C)
4142
#define CC_OSZAP (CC_O | CC_S | CC_Z | CC_A | CC_P)
4143

    
4144
/* flags read by an operation */
4145
static uint16_t opc_read_flags[NB_OPS] = { 
4146
    [INDEX_op_aas] = CC_A,
4147
    [INDEX_op_aaa] = CC_A,
4148
    [INDEX_op_das] = CC_A | CC_C,
4149
    [INDEX_op_daa] = CC_A | CC_C,
4150

    
4151
    [INDEX_op_adcb_T0_T1_cc] = CC_C,
4152
    [INDEX_op_adcw_T0_T1_cc] = CC_C,
4153
    [INDEX_op_adcl_T0_T1_cc] = CC_C,
4154
    [INDEX_op_sbbb_T0_T1_cc] = CC_C,
4155
    [INDEX_op_sbbw_T0_T1_cc] = CC_C,
4156
    [INDEX_op_sbbl_T0_T1_cc] = CC_C,
4157

    
4158
    [INDEX_op_adcb_mem_T0_T1_cc] = CC_C,
4159
    [INDEX_op_adcw_mem_T0_T1_cc] = CC_C,
4160
    [INDEX_op_adcl_mem_T0_T1_cc] = CC_C,
4161
    [INDEX_op_sbbb_mem_T0_T1_cc] = CC_C,
4162
    [INDEX_op_sbbw_mem_T0_T1_cc] = CC_C,
4163
    [INDEX_op_sbbl_mem_T0_T1_cc] = CC_C,
4164

    
4165
    /* subtle: due to the incl/decl implementation, C is used */
4166
    [INDEX_op_update_inc_cc] = CC_C, 
4167

    
4168
    [INDEX_op_into] = CC_O,
4169

    
4170
    [INDEX_op_jb_subb] = CC_C,
4171
    [INDEX_op_jb_subw] = CC_C,
4172
    [INDEX_op_jb_subl] = CC_C,
4173

    
4174
    [INDEX_op_jz_subb] = CC_Z,
4175
    [INDEX_op_jz_subw] = CC_Z,
4176
    [INDEX_op_jz_subl] = CC_Z,
4177

    
4178
    [INDEX_op_jbe_subb] = CC_Z | CC_C,
4179
    [INDEX_op_jbe_subw] = CC_Z | CC_C,
4180
    [INDEX_op_jbe_subl] = CC_Z | CC_C,
4181

    
4182
    [INDEX_op_js_subb] = CC_S,
4183
    [INDEX_op_js_subw] = CC_S,
4184
    [INDEX_op_js_subl] = CC_S,
4185

    
4186
    [INDEX_op_jl_subb] = CC_O | CC_S,
4187
    [INDEX_op_jl_subw] = CC_O | CC_S,
4188
    [INDEX_op_jl_subl] = CC_O | CC_S,
4189

    
4190
    [INDEX_op_jle_subb] = CC_O | CC_S | CC_Z,
4191
    [INDEX_op_jle_subw] = CC_O | CC_S | CC_Z,
4192
    [INDEX_op_jle_subl] = CC_O | CC_S | CC_Z,
4193

    
4194
    [INDEX_op_loopnzw] = CC_Z,
4195
    [INDEX_op_loopnzl] = CC_Z,
4196
    [INDEX_op_loopzw] = CC_Z,
4197
    [INDEX_op_loopzl] = CC_Z,
4198

    
4199
    [INDEX_op_seto_T0_cc] = CC_O,
4200
    [INDEX_op_setb_T0_cc] = CC_C,
4201
    [INDEX_op_setz_T0_cc] = CC_Z,
4202
    [INDEX_op_setbe_T0_cc] = CC_Z | CC_C,
4203
    [INDEX_op_sets_T0_cc] = CC_S,
4204
    [INDEX_op_setp_T0_cc] = CC_P,
4205
    [INDEX_op_setl_T0_cc] = CC_O | CC_S,
4206
    [INDEX_op_setle_T0_cc] = CC_O | CC_S | CC_Z,
4207

    
4208
    [INDEX_op_setb_T0_subb] = CC_C,
4209
    [INDEX_op_setb_T0_subw] = CC_C,
4210
    [INDEX_op_setb_T0_subl] = CC_C,
4211

    
4212
    [INDEX_op_setz_T0_subb] = CC_Z,
4213
    [INDEX_op_setz_T0_subw] = CC_Z,
4214
    [INDEX_op_setz_T0_subl] = CC_Z,
4215

    
4216
    [INDEX_op_setbe_T0_subb] = CC_Z | CC_C,
4217
    [INDEX_op_setbe_T0_subw] = CC_Z | CC_C,
4218
    [INDEX_op_setbe_T0_subl] = CC_Z | CC_C,
4219

    
4220
    [INDEX_op_sets_T0_subb] = CC_S,
4221
    [INDEX_op_sets_T0_subw] = CC_S,
4222
    [INDEX_op_sets_T0_subl] = CC_S,
4223

    
4224
    [INDEX_op_setl_T0_subb] = CC_O | CC_S,
4225
    [INDEX_op_setl_T0_subw] = CC_O | CC_S,
4226
    [INDEX_op_setl_T0_subl] = CC_O | CC_S,
4227

    
4228
    [INDEX_op_setle_T0_subb] = CC_O | CC_S | CC_Z,
4229
    [INDEX_op_setle_T0_subw] = CC_O | CC_S | CC_Z,
4230
    [INDEX_op_setle_T0_subl] = CC_O | CC_S | CC_Z,
4231

    
4232
    [INDEX_op_movl_T0_eflags] = CC_OSZAPC,
4233
    [INDEX_op_cmc] = CC_C,
4234
    [INDEX_op_salc] = CC_C,
4235

    
4236
    [INDEX_op_rclb_T0_T1_cc] = CC_C,
4237
    [INDEX_op_rclw_T0_T1_cc] = CC_C,
4238
    [INDEX_op_rcll_T0_T1_cc] = CC_C,
4239
    [INDEX_op_rcrb_T0_T1_cc] = CC_C,
4240
    [INDEX_op_rcrw_T0_T1_cc] = CC_C,
4241
    [INDEX_op_rcrl_T0_T1_cc] = CC_C,
4242

    
4243
    [INDEX_op_rclb_mem_T0_T1_cc] = CC_C,
4244
    [INDEX_op_rclw_mem_T0_T1_cc] = CC_C,
4245
    [INDEX_op_rcll_mem_T0_T1_cc] = CC_C,
4246
    [INDEX_op_rcrb_mem_T0_T1_cc] = CC_C,
4247
    [INDEX_op_rcrw_mem_T0_T1_cc] = CC_C,
4248
    [INDEX_op_rcrl_mem_T0_T1_cc] = CC_C,
4249
};
4250

    
4251
/* flags written by an operation */
4252
static uint16_t opc_write_flags[NB_OPS] = { 
4253
    [INDEX_op_update2_cc] = CC_OSZAPC,
4254
    [INDEX_op_update1_cc] = CC_OSZAPC,
4255
    [INDEX_op_cmpl_T0_T1_cc] = CC_OSZAPC,
4256
    [INDEX_op_update_neg_cc] = CC_OSZAPC,
4257
    /* subtle: due to the incl/decl implementation, C is used */
4258
    [INDEX_op_update_inc_cc] = CC_OSZAPC, 
4259
    [INDEX_op_testl_T0_T1_cc] = CC_OSZAPC,
4260

    
4261
    [INDEX_op_adcb_T0_T1_cc] = CC_OSZAPC,
4262
    [INDEX_op_adcw_T0_T1_cc] = CC_OSZAPC,
4263
    [INDEX_op_adcl_T0_T1_cc] = CC_OSZAPC,
4264
    [INDEX_op_sbbb_T0_T1_cc] = CC_OSZAPC,
4265
    [INDEX_op_sbbw_T0_T1_cc] = CC_OSZAPC,
4266
    [INDEX_op_sbbl_T0_T1_cc] = CC_OSZAPC,
4267

    
4268
    [INDEX_op_adcb_mem_T0_T1_cc] = CC_OSZAPC,
4269
    [INDEX_op_adcw_mem_T0_T1_cc] = CC_OSZAPC,
4270
    [INDEX_op_adcl_mem_T0_T1_cc] = CC_OSZAPC,
4271
    [INDEX_op_sbbb_mem_T0_T1_cc] = CC_OSZAPC,
4272
    [INDEX_op_sbbw_mem_T0_T1_cc] = CC_OSZAPC,
4273
    [INDEX_op_sbbl_mem_T0_T1_cc] = CC_OSZAPC,
4274

    
4275
    [INDEX_op_mulb_AL_T0] = CC_OSZAPC,
4276
    [INDEX_op_imulb_AL_T0] = CC_OSZAPC,
4277
    [INDEX_op_mulw_AX_T0] = CC_OSZAPC,
4278
    [INDEX_op_imulw_AX_T0] = CC_OSZAPC,
4279
    [INDEX_op_mull_EAX_T0] = CC_OSZAPC,
4280
    [INDEX_op_imull_EAX_T0] = CC_OSZAPC,
4281
    [INDEX_op_imulw_T0_T1] = CC_OSZAPC,
4282
    [INDEX_op_imull_T0_T1] = CC_OSZAPC,
4283
    
4284
    /* bcd */
4285
    [INDEX_op_aam] = CC_OSZAPC,
4286
    [INDEX_op_aad] = CC_OSZAPC,
4287
    [INDEX_op_aas] = CC_OSZAPC,
4288
    [INDEX_op_aaa] = CC_OSZAPC,
4289
    [INDEX_op_das] = CC_OSZAPC,
4290
    [INDEX_op_daa] = CC_OSZAPC,
4291

    
4292
    [INDEX_op_movb_eflags_T0] = CC_S | CC_Z | CC_A | CC_P | CC_C,
4293
    [INDEX_op_movw_eflags_T0] = CC_OSZAPC,
4294
    [INDEX_op_movl_eflags_T0] = CC_OSZAPC,
4295
    [INDEX_op_movw_eflags_T0_io] = CC_OSZAPC,
4296
    [INDEX_op_movl_eflags_T0_io] = CC_OSZAPC,
4297
    [INDEX_op_movw_eflags_T0_cpl0] = CC_OSZAPC,
4298
    [INDEX_op_movl_eflags_T0_cpl0] = CC_OSZAPC,
4299
    [INDEX_op_clc] = CC_C,
4300
    [INDEX_op_stc] = CC_C,
4301
    [INDEX_op_cmc] = CC_C,
4302

    
4303
    [INDEX_op_rolb_T0_T1_cc] = CC_O | CC_C,
4304
    [INDEX_op_rolw_T0_T1_cc] = CC_O | CC_C,
4305
    [INDEX_op_roll_T0_T1_cc] = CC_O | CC_C,
4306
    [INDEX_op_rorb_T0_T1_cc] = CC_O | CC_C,
4307
    [INDEX_op_rorw_T0_T1_cc] = CC_O | CC_C,
4308
    [INDEX_op_rorl_T0_T1_cc] = CC_O | CC_C,
4309

    
4310
    [INDEX_op_rclb_T0_T1_cc] = CC_O | CC_C,
4311
    [INDEX_op_rclw_T0_T1_cc] = CC_O | CC_C,
4312
    [INDEX_op_rcll_T0_T1_cc] = CC_O | CC_C,
4313
    [INDEX_op_rcrb_T0_T1_cc] = CC_O | CC_C,
4314
    [INDEX_op_rcrw_T0_T1_cc] = CC_O | CC_C,
4315
    [INDEX_op_rcrl_T0_T1_cc] = CC_O | CC_C,
4316

    
4317
    [INDEX_op_shlb_T0_T1_cc] = CC_OSZAPC,
4318
    [INDEX_op_shlw_T0_T1_cc] = CC_OSZAPC,
4319
    [INDEX_op_shll_T0_T1_cc] = CC_OSZAPC,
4320

    
4321
    [INDEX_op_shrb_T0_T1_cc] = CC_OSZAPC,
4322
    [INDEX_op_shrw_T0_T1_cc] = CC_OSZAPC,
4323
    [INDEX_op_shrl_T0_T1_cc] = CC_OSZAPC,
4324

    
4325
    [INDEX_op_sarb_T0_T1_cc] = CC_OSZAPC,
4326
    [INDEX_op_sarw_T0_T1_cc] = CC_OSZAPC,
4327
    [INDEX_op_sarl_T0_T1_cc] = CC_OSZAPC,
4328

    
4329
    [INDEX_op_shldw_T0_T1_ECX_cc] = CC_OSZAPC,
4330
    [INDEX_op_shldl_T0_T1_ECX_cc] = CC_OSZAPC,
4331
    [INDEX_op_shldw_T0_T1_im_cc] = CC_OSZAPC,
4332
    [INDEX_op_shldl_T0_T1_im_cc] = CC_OSZAPC,
4333

    
4334
    [INDEX_op_shrdw_T0_T1_ECX_cc] = CC_OSZAPC,
4335
    [INDEX_op_shrdl_T0_T1_ECX_cc] = CC_OSZAPC,
4336
    [INDEX_op_shrdw_T0_T1_im_cc] = CC_OSZAPC,
4337
    [INDEX_op_shrdl_T0_T1_im_cc] = CC_OSZAPC,
4338

    
4339
    [INDEX_op_rolb_mem_T0_T1_cc] = CC_O | CC_C,
4340
    [INDEX_op_rolw_mem_T0_T1_cc] = CC_O | CC_C,
4341
    [INDEX_op_roll_mem_T0_T1_cc] = CC_O | CC_C,
4342
    [INDEX_op_rorb_mem_T0_T1_cc] = CC_O | CC_C,
4343
    [INDEX_op_rorw_mem_T0_T1_cc] = CC_O | CC_C,
4344
    [INDEX_op_rorl_mem_T0_T1_cc] = CC_O | CC_C,
4345

    
4346
    [INDEX_op_rclb_mem_T0_T1_cc] = CC_O | CC_C,
4347
    [INDEX_op_rclw_mem_T0_T1_cc] = CC_O | CC_C,
4348
    [INDEX_op_rcll_mem_T0_T1_cc] = CC_O | CC_C,
4349
    [INDEX_op_rcrb_mem_T0_T1_cc] = CC_O | CC_C,
4350
    [INDEX_op_rcrw_mem_T0_T1_cc] = CC_O | CC_C,
4351
    [INDEX_op_rcrl_mem_T0_T1_cc] = CC_O | CC_C,
4352

    
4353
    [INDEX_op_shlb_mem_T0_T1_cc] = CC_OSZAPC,
4354
    [INDEX_op_shlw_mem_T0_T1_cc] = CC_OSZAPC,
4355
    [INDEX_op_shll_mem_T0_T1_cc] = CC_OSZAPC,
4356

    
4357
    [INDEX_op_shrb_mem_T0_T1_cc] = CC_OSZAPC,
4358
    [INDEX_op_shrw_mem_T0_T1_cc] = CC_OSZAPC,
4359
    [INDEX_op_shrl_mem_T0_T1_cc] = CC_OSZAPC,
4360

    
4361
    [INDEX_op_sarb_mem_T0_T1_cc] = CC_OSZAPC,
4362
    [INDEX_op_sarw_mem_T0_T1_cc] = CC_OSZAPC,
4363
    [INDEX_op_sarl_mem_T0_T1_cc] = CC_OSZAPC,
4364

    
4365
    [INDEX_op_shldw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4366
    [INDEX_op_shldl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4367
    [INDEX_op_shldw_mem_T0_T1_im_cc] = CC_OSZAPC,
4368
    [INDEX_op_shldl_mem_T0_T1_im_cc] = CC_OSZAPC,
4369

    
4370
    [INDEX_op_shrdw_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4371
    [INDEX_op_shrdl_mem_T0_T1_ECX_cc] = CC_OSZAPC,
4372
    [INDEX_op_shrdw_mem_T0_T1_im_cc] = CC_OSZAPC,
4373
    [INDEX_op_shrdl_mem_T0_T1_im_cc] = CC_OSZAPC,
4374

    
4375
    [INDEX_op_btw_T0_T1_cc] = CC_OSZAPC,
4376
    [INDEX_op_btl_T0_T1_cc] = CC_OSZAPC,
4377
    [INDEX_op_btsw_T0_T1_cc] = CC_OSZAPC,
4378
    [INDEX_op_btsl_T0_T1_cc] = CC_OSZAPC,
4379
    [INDEX_op_btrw_T0_T1_cc] = CC_OSZAPC,
4380
    [INDEX_op_btrl_T0_T1_cc] = CC_OSZAPC,
4381
    [INDEX_op_btcw_T0_T1_cc] = CC_OSZAPC,
4382
    [INDEX_op_btcl_T0_T1_cc] = CC_OSZAPC,
4383

    
4384
    [INDEX_op_bsfw_T0_cc] = CC_OSZAPC,
4385
    [INDEX_op_bsfl_T0_cc] = CC_OSZAPC,
4386
    [INDEX_op_bsrw_T0_cc] = CC_OSZAPC,
4387
    [INDEX_op_bsrl_T0_cc] = CC_OSZAPC,
4388

    
4389
    [INDEX_op_cmpxchgb_T0_T1_EAX_cc] = CC_OSZAPC,
4390
    [INDEX_op_cmpxchgw_T0_T1_EAX_cc] = CC_OSZAPC,
4391
    [INDEX_op_cmpxchgl_T0_T1_EAX_cc] = CC_OSZAPC,
4392

    
4393
    [INDEX_op_cmpxchgb_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4394
    [INDEX_op_cmpxchgw_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4395
    [INDEX_op_cmpxchgl_mem_T0_T1_EAX_cc] = CC_OSZAPC,
4396

    
4397
    [INDEX_op_cmpxchg8b] = CC_Z,
4398
    [INDEX_op_lar] = CC_Z,
4399
    [INDEX_op_lsl] = CC_Z,
4400
    [INDEX_op_fcomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4401
    [INDEX_op_fucomi_ST0_FT0] = CC_Z | CC_P | CC_C,
4402
};
4403

    
4404
/* simpler form of an operation if no flags need to be generated */
4405
static uint16_t opc_simpler[NB_OPS] = { 
4406
    [INDEX_op_update2_cc] = INDEX_op_nop,
4407
    [INDEX_op_update1_cc] = INDEX_op_nop,
4408
    [INDEX_op_update_neg_cc] = INDEX_op_nop,
4409
#if 0
4410
    /* broken: CC_OP logic must be rewritten */
4411
    [INDEX_op_update_inc_cc] = INDEX_op_nop,
4412
#endif
4413
    [INDEX_op_rolb_T0_T1_cc] = INDEX_op_rolb_T0_T1,
4414
    [INDEX_op_rolw_T0_T1_cc] = INDEX_op_rolw_T0_T1,
4415
    [INDEX_op_roll_T0_T1_cc] = INDEX_op_roll_T0_T1,
4416

    
4417
    [INDEX_op_rorb_T0_T1_cc] = INDEX_op_rorb_T0_T1,
4418
    [INDEX_op_rorw_T0_T1_cc] = INDEX_op_rorw_T0_T1,
4419
    [INDEX_op_rorl_T0_T1_cc] = INDEX_op_rorl_T0_T1,
4420

    
4421
    [INDEX_op_rolb_mem_T0_T1_cc] = INDEX_op_rolb_mem_T0_T1,
4422
    [INDEX_op_rolw_mem_T0_T1_cc] = INDEX_op_rolw_mem_T0_T1,
4423
    [INDEX_op_roll_mem_T0_T1_cc] = INDEX_op_roll_mem_T0_T1,
4424

    
4425
    [INDEX_op_rorb_mem_T0_T1_cc] = INDEX_op_rorb_mem_T0_T1,
4426
    [INDEX_op_rorw_mem_T0_T1_cc] = INDEX_op_rorw_mem_T0_T1,
4427
    [INDEX_op_rorl_mem_T0_T1_cc] = INDEX_op_rorl_mem_T0_T1,
4428

    
4429
    [INDEX_op_shlb_T0_T1_cc] = INDEX_op_shlb_T0_T1,
4430
    [INDEX_op_shlw_T0_T1_cc] = INDEX_op_shlw_T0_T1,
4431
    [INDEX_op_shll_T0_T1_cc] = INDEX_op_shll_T0_T1,
4432

    
4433
    [INDEX_op_shrb_T0_T1_cc] = INDEX_op_shrb_T0_T1,
4434
    [INDEX_op_shrw_T0_T1_cc] = INDEX_op_shrw_T0_T1,
4435
    [INDEX_op_shrl_T0_T1_cc] = INDEX_op_shrl_T0_T1,
4436

    
4437
    [INDEX_op_sarb_T0_T1_cc] = INDEX_op_sarb_T0_T1,
4438
    [INDEX_op_sarw_T0_T1_cc] = INDEX_op_sarw_T0_T1,
4439
    [INDEX_op_sarl_T0_T1_cc] = INDEX_op_sarl_T0_T1,
4440
};
4441

    
4442
void optimize_flags_init(void)
4443
{
4444
    int i;
4445
    /* put default values in arrays */
4446
    for(i = 0; i < NB_OPS; i++) {
4447
        if (opc_simpler[i] == 0)
4448
            opc_simpler[i] = i;
4449
    }
4450
}
4451

    
4452
/* CPU flags computation optimization: we move backward thru the
4453
   generated code to see which flags are needed. The operation is
4454
   modified if suitable */
4455
static void optimize_flags(uint16_t *opc_buf, int opc_buf_len)
4456
{
4457
    uint16_t *opc_ptr;
4458
    int live_flags, write_flags, op;
4459

    
4460
    opc_ptr = opc_buf + opc_buf_len;
4461
    /* live_flags contains the flags needed by the next instructions
4462
       in the code. At the end of the bloc, we consider that all the
4463
       flags are live. */
4464
    live_flags = CC_OSZAPC;
4465
    while (opc_ptr > opc_buf) {
4466
        op = *--opc_ptr;
4467
        /* if none of the flags written by the instruction is used,
4468
           then we can try to find a simpler instruction */
4469
        write_flags = opc_write_flags[op];
4470
        if ((live_flags & write_flags) == 0) {
4471
            *opc_ptr = opc_simpler[op];
4472
        }
4473
        /* compute the live flags before the instruction */
4474
        live_flags &= ~write_flags;
4475
        live_flags |= opc_read_flags[op];
4476
    }
4477
}
4478

    
4479
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
4480
   basic block 'tb'. If search_pc is TRUE, also generate PC
4481
   information for each intermediate instruction. */
4482
static inline int gen_intermediate_code_internal(CPUState *env,
4483
                                                 TranslationBlock *tb, 
4484
                                                 int search_pc)
4485
{
4486
    DisasContext dc1, *dc = &dc1;
4487
    uint8_t *pc_ptr;
4488
    uint16_t *gen_opc_end;
4489
    int flags, j, lj;
4490
    uint8_t *pc_start;
4491
    uint8_t *cs_base;
4492
    
4493
    /* generate intermediate code */
4494
    pc_start = (uint8_t *)tb->pc;
4495
    cs_base = (uint8_t *)tb->cs_base;
4496
    flags = tb->flags;
4497
       
4498
    dc->pe = env->cr[0] & CR0_PE_MASK;
4499
    dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
4500
    dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
4501
    dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
4502
    dc->f_st = 0;
4503
    dc->vm86 = (flags >> VM_SHIFT) & 1;
4504
    dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
4505
    dc->iopl = (flags >> IOPL_SHIFT) & 3;
4506
    dc->tf = (flags >> TF_SHIFT) & 1;
4507
    dc->singlestep_enabled = env->singlestep_enabled;
4508
    dc->cc_op = CC_OP_DYNAMIC;
4509
    dc->cs_base = cs_base;
4510
    dc->tb = tb;
4511
    dc->popl_esp_hack = 0;
4512
    /* select memory access functions */
4513
    dc->mem_index = 0;
4514
    if (flags & HF_SOFTMMU_MASK) {
4515
        if (dc->cpl == 3)
4516
            dc->mem_index = 6;
4517
        else
4518
            dc->mem_index = 3;
4519
    }
4520
    dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
4521
                    (flags & HF_INHIBIT_IRQ_MASK)
4522
#ifndef CONFIG_SOFTMMU
4523
                    || (flags & HF_SOFTMMU_MASK)
4524
#endif
4525
                    );
4526
    gen_opc_ptr = gen_opc_buf;
4527
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
4528
    gen_opparam_ptr = gen_opparam_buf;
4529

    
4530
    dc->is_jmp = DISAS_NEXT;
4531
    pc_ptr = pc_start;
4532
    lj = -1;
4533

    
4534
    for(;;) {
4535
        if (env->nb_breakpoints > 0) {
4536
            for(j = 0; j < env->nb_breakpoints; j++) {
4537
                if (env->breakpoints[j] == (unsigned long)pc_ptr) {
4538
                    gen_debug(dc, pc_ptr - dc->cs_base);
4539
                    break;
4540
                }
4541
            }
4542
        }
4543
        if (search_pc) {
4544
            j = gen_opc_ptr - gen_opc_buf;
4545
            if (lj < j) {
4546
                lj++;
4547
                while (lj < j)
4548
                    gen_opc_instr_start[lj++] = 0;
4549
            }
4550
            gen_opc_pc[lj] = (uint32_t)pc_ptr;
4551
            gen_opc_cc_op[lj] = dc->cc_op;
4552
            gen_opc_instr_start[lj] = 1;
4553
        }
4554
        pc_ptr = disas_insn(dc, pc_ptr);
4555
        /* stop translation if indicated */
4556
        if (dc->is_jmp)
4557
            break;
4558
        /* if single step mode, we generate only one instruction and
4559
           generate an exception */
4560
        /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
4561
           the flag and abort the translation to give the irqs a
4562
           change to be happen */
4563
        if (dc->tf || dc->singlestep_enabled || 
4564
            (flags & HF_INHIBIT_IRQ_MASK)) {
4565
            gen_op_jmp_im(pc_ptr - dc->cs_base);
4566
            gen_eob(dc);
4567
            break;
4568
        }
4569
        /* if too long translation, stop generation too */
4570
        if (gen_opc_ptr >= gen_opc_end ||
4571
            (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32)) {
4572
            gen_op_jmp_im(pc_ptr - dc->cs_base);
4573
            gen_eob(dc);
4574
            break;
4575
        }
4576
    }
4577
    *gen_opc_ptr = INDEX_op_end;
4578
    /* we don't forget to fill the last values */
4579
    if (search_pc) {
4580
        j = gen_opc_ptr - gen_opc_buf;
4581
        lj++;
4582
        while (lj <= j)
4583
            gen_opc_instr_start[lj++] = 0;
4584
    }
4585
        
4586
#ifdef DEBUG_DISAS
4587
    if (loglevel) {
4588
        fprintf(logfile, "----------------\n");
4589
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
4590
        disas(logfile, pc_start, pc_ptr - pc_start, 0, !dc->code32);
4591
        fprintf(logfile, "\n");
4592

    
4593
        fprintf(logfile, "OP:\n");
4594
        dump_ops(gen_opc_buf, gen_opparam_buf);
4595
        fprintf(logfile, "\n");
4596
    }
4597
#endif
4598

    
4599
    /* optimize flag computations */
4600
    optimize_flags(gen_opc_buf, gen_opc_ptr - gen_opc_buf);
4601

    
4602
#ifdef DEBUG_DISAS
4603
    if (loglevel) {
4604
        fprintf(logfile, "AFTER FLAGS OPT:\n");
4605
        dump_ops(gen_opc_buf, gen_opparam_buf);
4606
        fprintf(logfile, "\n");
4607
    }
4608
#endif
4609
    if (!search_pc)
4610
        tb->size = pc_ptr - pc_start;
4611
    return 0;
4612
}
4613

    
4614
int gen_intermediate_code(CPUState *env, TranslationBlock *tb)
4615
{
4616
    return gen_intermediate_code_internal(env, tb, 0);
4617
}
4618

    
4619
int gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
4620
{
4621
    return gen_intermediate_code_internal(env, tb, 1);
4622
}
4623