Revision 3464c589
b/hw/sh7750.c | ||
---|---|---|
51 | 51 |
uint16_t periph_pdtrb; /* Imposed by the peripherals */ |
52 | 52 |
uint16_t periph_portdirb; /* Direction seen from the peripherals */ |
53 | 53 |
sh7750_io_device *devices[NB_DEVICES]; /* External peripherals */ |
54 |
|
|
55 |
uint16_t icr; |
|
56 |
uint16_t ipra; |
|
57 |
uint16_t iprb; |
|
58 |
uint16_t iprc; |
|
59 |
uint16_t iprd; |
|
60 |
uint32_t intpri00; |
|
61 |
uint32_t intmsk00; |
|
54 | 62 |
/* Cache */ |
55 | 63 |
uint32_t ccr; |
56 | 64 |
|
... | ... | |
207 | 215 |
return porta_lines(s); |
208 | 216 |
case SH7750_PDTRB_A7: |
209 | 217 |
return portb_lines(s); |
218 |
case 0x1fd00000: |
|
219 |
return s->icr; |
|
220 |
case 0x1fd00004: |
|
221 |
return s->ipra; |
|
222 |
case 0x1fd00008: |
|
223 |
return s->iprb; |
|
224 |
case 0x1fd0000c: |
|
225 |
return s->iprc; |
|
226 |
case 0x1fd00010: |
|
227 |
return s->iprd; |
|
210 | 228 |
default: |
211 | 229 |
error_access("word read", addr); |
212 | 230 |
assert(0); |
... | ... | |
242 | 260 |
return 0x00110000; /* Minimum caches */ |
243 | 261 |
case 0x1f000044: /* Processor version PRR */ |
244 | 262 |
return 0x00000100; /* SH7750R */ |
263 |
case 0x1e080000: |
|
264 |
return s->intpri00; |
|
265 |
case 0x1e080020: |
|
266 |
return 0; |
|
267 |
case 0x1e080040: |
|
268 |
return s->intmsk00; |
|
269 |
case 0x1e080060: |
|
270 |
return 0; |
|
245 | 271 |
default: |
246 | 272 |
error_access("long read", addr); |
247 | 273 |
assert(0); |
... | ... | |
300 | 326 |
assert(0); |
301 | 327 |
} |
302 | 328 |
return; |
329 |
case 0x1fd00000: |
|
330 |
s->icr = mem_value; |
|
331 |
return; |
|
332 |
case 0x1fd00004: |
|
333 |
s->ipra = mem_value; |
|
334 |
return; |
|
335 |
case 0x1fd00008: |
|
336 |
s->iprb = mem_value; |
|
337 |
return; |
|
338 |
case 0x1fd0000c: |
|
339 |
s->iprc = mem_value; |
|
340 |
return; |
|
341 |
case 0x1fd00010: |
|
342 |
s->iprd = mem_value; |
|
343 |
return; |
|
303 | 344 |
default: |
304 | 345 |
error_access("word write", addr); |
305 | 346 |
assert(0); |
... | ... | |
364 | 405 |
case SH7750_CCR_A7: |
365 | 406 |
s->ccr = mem_value; |
366 | 407 |
return; |
408 |
case 0x1e080000: |
|
409 |
s->intpri00 = mem_value; |
|
410 |
return; |
|
411 |
case 0x1e080020: |
|
412 |
return; |
|
413 |
case 0x1e080040: |
|
414 |
s->intmsk00 = mem_value; |
|
415 |
return; |
|
416 |
case 0x1e080060: |
|
417 |
return; |
|
367 | 418 |
default: |
368 | 419 |
error_access("long write", addr); |
369 | 420 |
assert(0); |
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