root / target-sparc / fbranch_template.h @ 3475187d
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1 | 3475187d | bellard | /* FCC1:FCC0: 0 =, 1 <, 2 >, 3 u */
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2 | 3475187d | bellard | |
3 | 3475187d | bellard | void OPPROTO glue(op_eval_fbne, FCC)(void) |
4 | 3475187d | bellard | { |
5 | 3475187d | bellard | // !0
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6 | 3475187d | bellard | T2 = FFLAG_SET(FSR_FCC0) | FFLAG_SET(FSR_FCC1); /* L or G or U */
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7 | 3475187d | bellard | } |
8 | 3475187d | bellard | |
9 | 3475187d | bellard | void OPPROTO glue(op_eval_fblg, FCC)(void) |
10 | 3475187d | bellard | { |
11 | 3475187d | bellard | // 1 or 2
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12 | 3475187d | bellard | T2 = FFLAG_SET(FSR_FCC0) ^ FFLAG_SET(FSR_FCC1); |
13 | 3475187d | bellard | } |
14 | 3475187d | bellard | |
15 | 3475187d | bellard | void OPPROTO glue(op_eval_fbul, FCC)(void) |
16 | 3475187d | bellard | { |
17 | 3475187d | bellard | // 1 or 3
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18 | 3475187d | bellard | T2 = FFLAG_SET(FSR_FCC0); |
19 | 3475187d | bellard | } |
20 | 3475187d | bellard | |
21 | 3475187d | bellard | void OPPROTO glue(op_eval_fbl, FCC)(void) |
22 | 3475187d | bellard | { |
23 | 3475187d | bellard | // 1
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24 | 3475187d | bellard | T2 = FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1); |
25 | 3475187d | bellard | } |
26 | 3475187d | bellard | |
27 | 3475187d | bellard | void OPPROTO glue(op_eval_fbug, FCC)(void) |
28 | 3475187d | bellard | { |
29 | 3475187d | bellard | // 2 or 3
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30 | 3475187d | bellard | T2 = FFLAG_SET(FSR_FCC1); |
31 | 3475187d | bellard | } |
32 | 3475187d | bellard | |
33 | 3475187d | bellard | void OPPROTO glue(op_eval_fbg, FCC)(void) |
34 | 3475187d | bellard | { |
35 | 3475187d | bellard | // 2
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36 | 3475187d | bellard | T2 = !FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1); |
37 | 3475187d | bellard | } |
38 | 3475187d | bellard | |
39 | 3475187d | bellard | void OPPROTO glue(op_eval_fbu, FCC)(void) |
40 | 3475187d | bellard | { |
41 | 3475187d | bellard | // 3
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42 | 3475187d | bellard | T2 = FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1); |
43 | 3475187d | bellard | } |
44 | 3475187d | bellard | |
45 | 3475187d | bellard | void OPPROTO glue(op_eval_fbe, FCC)(void) |
46 | 3475187d | bellard | { |
47 | 3475187d | bellard | // 0
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48 | 3475187d | bellard | T2 = !FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1); |
49 | 3475187d | bellard | } |
50 | 3475187d | bellard | |
51 | 3475187d | bellard | void OPPROTO glue(op_eval_fbue, FCC)(void) |
52 | 3475187d | bellard | { |
53 | 3475187d | bellard | // 0 or 3
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54 | 3475187d | bellard | T2 = !(FFLAG_SET(FSR_FCC1) ^ FFLAG_SET(FSR_FCC0)); |
55 | 3475187d | bellard | FORCE_RET(); |
56 | 3475187d | bellard | } |
57 | 3475187d | bellard | |
58 | 3475187d | bellard | void OPPROTO glue(op_eval_fbge, FCC)(void) |
59 | 3475187d | bellard | { |
60 | 3475187d | bellard | // 0 or 2
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61 | 3475187d | bellard | T2 = !FFLAG_SET(FSR_FCC0); |
62 | 3475187d | bellard | } |
63 | 3475187d | bellard | |
64 | 3475187d | bellard | void OPPROTO glue(op_eval_fbuge, FCC)(void) |
65 | 3475187d | bellard | { |
66 | 3475187d | bellard | // !1
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67 | 3475187d | bellard | T2 = !(FFLAG_SET(FSR_FCC0) & !FFLAG_SET(FSR_FCC1)); |
68 | 3475187d | bellard | } |
69 | 3475187d | bellard | |
70 | 3475187d | bellard | void OPPROTO glue(op_eval_fble, FCC)(void) |
71 | 3475187d | bellard | { |
72 | 3475187d | bellard | // 0 or 1
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73 | 3475187d | bellard | T2 = !FFLAG_SET(FSR_FCC1); |
74 | 3475187d | bellard | } |
75 | 3475187d | bellard | |
76 | 3475187d | bellard | void OPPROTO glue(op_eval_fbule, FCC)(void) |
77 | 3475187d | bellard | { |
78 | 3475187d | bellard | // !2
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79 | 3475187d | bellard | T2 = !(!FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1)); |
80 | 3475187d | bellard | } |
81 | 3475187d | bellard | |
82 | 3475187d | bellard | void OPPROTO glue(op_eval_fbo, FCC)(void) |
83 | 3475187d | bellard | { |
84 | 3475187d | bellard | // !3
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85 | 3475187d | bellard | T2 = !(FFLAG_SET(FSR_FCC0) & FFLAG_SET(FSR_FCC1)); |
86 | 3475187d | bellard | } |
87 | 3475187d | bellard | |
88 | 3475187d | bellard | #undef FCC
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89 | 3475187d | bellard | #undef FFLAG_SET |