Archipelago » qemu

  - SPARC64 progress (Blue Swirl)

ifeq ($(TARGET_ARCH), sparc64)

VL_OBJS+= sun4u.o m48t08.o magic-load.o slavio_serial.o

else

VL_OBJS+= sun4m.o tcx.o lance.o iommu.o m48t08.o magic-load.o slavio_intctl.o slavio_timer.o slavio_serial.o slavio_misc.o fdc.o esp.o

endif

op.o: op.c op_template.h op_mem.h fop_template.h fbranch_template.h

magic_load.o: elf_op.h

#ifndef TARGET_SPARC

#define reg_T2

#endif

    int saved_T0, saved_T1;

#if defined(reg_T2)

    int saved_T2;

#endif

#if defined(TARGET_I386)

#elif defined(TARGET_SPARC)

#if defined(reg_REGWPTR)

    uint32_t *saved_regwptr;

#endif

#endif

#if defined(reg_T2)

#endif

#if defined(reg_REGWPTR)

    saved_regwptr = REGWPTR;

#endif

		    REGWPTR = env->regbase + (env->cwp * 16);

		    env->regwptr = REGWPTR;

                    cpu_dump_state(env, logfile, fprintf, 0);

#ifdef TARGET_SPARC64

                flags = (env->pstate << 2) | ((env->lsu & (DMMU_E | IMMU_E)) >> 2);

#else

                flags = env->psrs | ((env->mmuregs[0] & (MMU_E | MMU_NF)) << 1);

#endif

#if defined(reg_REGWPTR)

    REGWPTR = saved_regwptr;

#endif

#if defined(reg_T2)

#endif

#ifdef TARGET_SPARC64

    disasm_info.mach = bfd_mach_sparc_v9b;

#endif    

 * Copyright (c) 2003-2005 Fabrice Bellard

    target_ulong *registers = (target_ulong *)mem_buf;

#ifndef TARGET_SPARC64

    {

	target_ulong tmp;

	tmp = GET_PSR(env);

	registers[65] = tswapl(tmp);

    }

    return 73 * sizeof(target_ulong);

#else

    for (i = 0; i < 32; i += 2) {

        registers[i/2 + 64] = tswapl(*((uint64_t *)&env->fpr[i]));

    }

    registers[81] = tswapl(env->pc);

    registers[82] = tswapl(env->npc);

    registers[83] = tswapl(env->tstate[env->tl]);

    registers[84] = tswapl(env->fsr);

    registers[85] = tswapl(env->fprs);

    registers[86] = tswapl(env->y);

    return 87 * sizeof(target_ulong);

#endif

    target_ulong *registers = (target_ulong *)mem_buf;

        env->regwptr[i] = tswapl(registers[i + 8]);

#ifndef TARGET_SPARC64

#else

    for (i = 0; i < 32; i += 2) {

	uint64_t tmp;

	tmp = tswapl(registers[i/2 + 64]) << 32;

	tmp |= tswapl(registers[i/2 + 64 + 1]);

        *((uint64_t *)&env->fpr[i]) = tmp;

    }

    env->pc = tswapl(registers[81]);

    env->npc = tswapl(registers[82]);

    env->tstate[env->tl] = tswapl(registers[83]);

    env->fsr = tswapl(registers[84]);

    env->fprs = tswapl(registers[85]);

    env->y = tswapl(registers[86]);

#endif

#ifdef BSWAP_NEEDED

static void glue(bswap_ehdr, SZ)(struct elfhdr *ehdr)

{

    bswap16s(&ehdr->e_type);			/* Object file type */

    bswap16s(&ehdr->e_machine);		/* Architecture */

    bswap32s(&ehdr->e_version);		/* Object file version */

    bswapSZs(&ehdr->e_entry);		/* Entry point virtual address */

    bswapSZs(&ehdr->e_phoff);		/* Program header table file offset */

    bswapSZs(&ehdr->e_shoff);		/* Section header table file offset */

    bswap32s(&ehdr->e_flags);		/* Processor-specific flags */

    bswap16s(&ehdr->e_ehsize);		/* ELF header size in bytes */

    bswap16s(&ehdr->e_phentsize);		/* Program header table entry size */

    bswap16s(&ehdr->e_phnum);		/* Program header table entry count */

    bswap16s(&ehdr->e_shentsize);		/* Section header table entry size */

    bswap16s(&ehdr->e_shnum);		/* Section header table entry count */

    bswap16s(&ehdr->e_shstrndx);		/* Section header string table index */

}

static void glue(bswap_phdr, SZ)(struct elf_phdr *phdr)

{

    bswap32s(&phdr->p_type);			/* Segment type */

    bswapSZs(&phdr->p_offset);		/* Segment file offset */

    bswapSZs(&phdr->p_vaddr);		/* Segment virtual address */

    bswapSZs(&phdr->p_paddr);		/* Segment physical address */

    bswapSZs(&phdr->p_filesz);		/* Segment size in file */

    bswapSZs(&phdr->p_memsz);		/* Segment size in memory */

    bswap32s(&phdr->p_flags);		/* Segment flags */

    bswapSZs(&phdr->p_align);		/* Segment alignment */

}

static void glue(bswap_shdr, SZ)(struct elf_shdr *shdr)

{

    bswap32s(&shdr->sh_name);

    bswap32s(&shdr->sh_type);

    bswapSZs(&shdr->sh_flags);

    bswapSZs(&shdr->sh_addr);

    bswapSZs(&shdr->sh_offset);

    bswapSZs(&shdr->sh_size);

    bswap32s(&shdr->sh_link);

    bswap32s(&shdr->sh_info);

    bswapSZs(&shdr->sh_addralign);

    bswapSZs(&shdr->sh_entsize);

}

static void glue(bswap_sym, SZ)(struct elf_sym *sym)

{

    bswap32s(&sym->st_name);

    bswapSZs(&sym->st_value);

    bswapSZs(&sym->st_size);

    bswap16s(&sym->st_shndx);

}

#endif

static int glue(find_phdr, SZ)(struct elfhdr *ehdr, int fd, struct elf_phdr *phdr, elf_word type)

{

    int i, retval;

    retval = lseek(fd, ehdr->e_phoff, SEEK_SET);

    if (retval < 0)

	return -1;

    for (i = 0; i < ehdr->e_phnum; i++) {

	retval = read(fd, phdr, sizeof(*phdr));

	if (retval < 0)

	    return -1;

	glue(bswap_phdr, SZ)(phdr);

	if (phdr->p_type == type)

	    return 0;

    }

    return -1;

}

static void * glue(find_shdr, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, elf_word type)

{

    int i, retval;

    retval = lseek(fd, ehdr->e_shoff, SEEK_SET);

    if (retval < 0)

	return NULL;

    for (i = 0; i < ehdr->e_shnum; i++) {

	retval = read(fd, shdr, sizeof(*shdr));

	if (retval < 0)

	    return NULL;

	glue(bswap_shdr, SZ)(shdr);

	if (shdr->sh_type == type)

	    return qemu_malloc(shdr->sh_size);

    }

    return NULL;

}

static void * glue(find_strtab, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, struct elf_shdr *symtab)

{

    int retval;

    retval = lseek(fd, ehdr->e_shoff + sizeof(struct elf_shdr) * symtab->sh_link, SEEK_SET);

    if (retval < 0)

	return NULL;

    retval = read(fd, shdr, sizeof(*shdr));

    if (retval < 0)

	return NULL;

    glue(bswap_shdr, SZ)(shdr);

    if (shdr->sh_type == SHT_STRTAB)

	return qemu_malloc(shdr->sh_size);;

    return NULL;

}

static int glue(read_program, SZ)(int fd, struct elf_phdr *phdr, void *dst, elf_word entry)

{

    int retval;

    retval = lseek(fd, phdr->p_offset + entry - phdr->p_vaddr, SEEK_SET);

    if (retval < 0)

	return -1;

    return read(fd, dst, phdr->p_filesz);

}

static int glue(read_section, SZ)(int fd, struct elf_shdr *s, void *dst)

{

    int retval;

    retval = lseek(fd, s->sh_offset, SEEK_SET);

    if (retval < 0)

	return -1;

    retval = read(fd, dst, s->sh_size);

    if (retval < 0)

	return -1;

    return 0;

}

static void * glue(process_section, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, elf_word type)

{

    void *dst;

    dst = glue(find_shdr, SZ)(ehdr, fd, shdr, type);

    if (!dst)

	goto error;

    if (glue(read_section, SZ)(fd, shdr, dst))

	goto error;

    return dst;

 error:

    qemu_free(dst);

    return NULL;

}

static void * glue(process_strtab, SZ)(struct elfhdr *ehdr, int fd, struct elf_shdr *shdr, struct elf_shdr *symtab)

{

    void *dst;

    dst = glue(find_strtab, SZ)(ehdr, fd, shdr, symtab);

    if (!dst)

	goto error;

    if (glue(read_section, SZ)(fd, shdr, dst))

	goto error;

    return dst;

 error:

    qemu_free(dst);

    return NULL;

}

static void glue(load_symbols, SZ)(struct elfhdr *ehdr, int fd)

{

    struct elf_shdr symtab, strtab;

    struct elf_sym *syms;

#if (SZ == 64)

    struct elf32_sym *syms32;

#endif

    struct syminfo *s;

    int nsyms, i;

    char *str;

    /* Symbol table */

    syms = glue(process_section, SZ)(ehdr, fd, &symtab, SHT_SYMTAB);

    if (!syms)

	return;

    nsyms = symtab.sh_size / sizeof(struct elf_sym);

#if (SZ == 64)

    syms32 = qemu_mallocz(nsyms * sizeof(struct elf32_sym));

#endif

    for (i = 0; i < nsyms; i++) {

	glue(bswap_sym, SZ)(&syms[i]);

#if (SZ == 64)

	syms32[i].st_name = syms[i].st_name;

	syms32[i].st_info = syms[i].st_info;

	syms32[i].st_other = syms[i].st_other;

	syms32[i].st_shndx = syms[i].st_shndx;

	syms32[i].st_value = syms[i].st_value & 0xffffffff;

	syms32[i].st_size = syms[i].st_size & 0xffffffff;

#endif

    }

    /* String table */

    str = glue(process_strtab, SZ)(ehdr, fd, &strtab, &symtab);

    if (!str)

	goto error_freesyms;

    /* Commit */

    s = qemu_mallocz(sizeof(*s));

#if (SZ == 64)

    s->disas_symtab = syms32;

    qemu_free(syms);

#else

    s->disas_symtab = syms;

#endif

    s->disas_num_syms = nsyms;

    s->disas_strtab = str;

    s->next = syminfos;

    syminfos = s;

    return;

 error_freesyms:

#if (SZ == 64)

    qemu_free(syms32);

#endif

    qemu_free(syms);

    return;

}

#ifndef BSWAP_NEEDED

#define bswap_ehdr32(e) do { } while (0)

#define bswap_phdr32(e) do { } while (0)

#define bswap_shdr32(e) do { } while (0)

#define bswap_sym32(e) do { } while (0)

#ifdef TARGET_SPARC64

#define bswap_ehdr64(e) do { } while (0)

#define bswap_phdr64(e) do { } while (0)

#define bswap_shdr64(e) do { } while (0)

#define bswap_sym64(e) do { } while (0)

#endif

#define SZ		32

#define elf_word        uint32_t

#define bswapSZs	bswap32s

#include "elf_ops.h"

#ifdef TARGET_SPARC64

#undef elfhdr

#undef elf_phdr

#undef elf_shdr

#undef elf_sym

#undef elf_note

#undef elf_word

#undef bswapSZs

#undef SZ

#define elfhdr		elf64_hdr

#define elf_phdr	elf64_phdr

#define elf_note	elf64_note

#define elf_shdr	elf64_shdr

#define elf_sym		elf64_sym

#define elf_word        uint64_t

#define bswapSZs	bswap64s

#define SZ		64

#include "elf_ops.h"

#endif

    struct elf32_hdr ehdr;

    Elf32_Half machine;

	|| ehdr.e_ident[2] != 'L' || ehdr.e_ident[3] != 'F')

    machine = tswap16(ehdr.e_machine);

    if (machine == EM_SPARC || machine == EM_SPARC32PLUS) {

	struct elf32_phdr phdr;

	bswap_ehdr32(&ehdr);

	if (find_phdr32(&ehdr, fd, &phdr, PT_LOAD))

	    goto error;

	retval = read_program32(fd, &phdr, addr, ehdr.e_entry);

	if (retval < 0)

	    goto error;

	load_symbols32(&ehdr, fd);

    }

#ifdef TARGET_SPARC64

    else if (machine == EM_SPARCV9) {

	struct elf64_hdr ehdr64;

	struct elf64_phdr phdr;

	lseek(fd, 0, SEEK_SET);

	retval = read(fd, &ehdr64, sizeof(ehdr64));

	if (retval < 0)

	    goto error;

	bswap_ehdr64(&ehdr64);

	if (find_phdr64(&ehdr64, fd, &phdr, PT_LOAD))

	    goto error;

	retval = read_program64(fd, &phdr, addr, ehdr64.e_entry);

	if (retval < 0)

	    goto error;

	load_symbols64(&ehdr64, fd);

    }

#endif

	val &= ~0x4fb2007f;

	val &= ~0x4fb2007f;

    6, 0, 4, 10, 8, 0, 11, 0,	0, 0, 0, 0, 15, 0, 15, 0,

/*

 * QEMU Sparc SLAVIO aux io port emulation

 * 

 * Copyright (c) 2005 Fabrice Bellard

 * 

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "vl.h"

/* debug misc */

//#define DEBUG_MISC

/*

 * This is the auxio port, chip control and system control part of

 * chip STP2001 (Slave I/O), also produced as NCR89C105. See

 * http://www.ibiblio.org/pub/historic-linux/early-ports/Sparc/NCR/NCR89C105.txt

 *

 * This also includes the PMC CPU idle controller.

 */

#ifdef DEBUG_MISC

#define MISC_DPRINTF(fmt, args...) \

do { printf("MISC: " fmt , ##args); } while (0)

#else

#define MISC_DPRINTF(fmt, args...)

#endif

typedef struct MiscState {

    int irq;

    uint8_t config;

    uint8_t aux1, aux2;

    uint8_t diag, mctrl;

} MiscState;

#define MISC_MAXADDR 1

static void slavio_misc_update_irq(void *opaque)

{

    MiscState *s = opaque;

    if ((s->aux2 & 0x4) && (s->config & 0x8)) {

        pic_set_irq(s->irq, 1);

    } else {

        pic_set_irq(s->irq, 0);

    }

}

static void slavio_misc_reset(void *opaque)

{

    MiscState *s = opaque;

    // Diagnostic register not cleared in reset

    s->config = s->aux1 = s->aux2 = s->mctrl = 0;

}

void slavio_set_power_fail(void *opaque, int power_failing)

{

    MiscState *s = opaque;

    MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);

    if (power_failing && (s->config & 0x8)) {

	s->aux2 |= 0x4;

    } else {

	s->aux2 &= ~0x4;

    }

    slavio_misc_update_irq(s);

}

static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)

{

    MiscState *s = opaque;

    switch (addr & 0xfff0000) {

    case 0x1800000:

	MISC_DPRINTF("Write config %2.2x\n", val & 0xff);

	s->config = val & 0xff;

	slavio_misc_update_irq(s);

	break;

    case 0x1900000:

	MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);

	s->aux1 = val & 0xff;

	break;

    case 0x1910000:

	val &= 0x3;

	MISC_DPRINTF("Write aux2 %2.2x\n", val);

	val |= s->aux2 & 0x4;

	if (val & 0x2) // Clear Power Fail int

	    val &= 0x1;

	s->aux2 = val;

	if (val & 1)

	    qemu_system_shutdown_request();

	slavio_misc_update_irq(s);

	break;

    case 0x1a00000:

	MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);

	s->diag = val & 0xff;

	break;

    case 0x1b00000:

	MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);

	s->mctrl = val & 0xff;

	break;

    case 0x1f00000:

	MISC_DPRINTF("Write system control %2.2x\n", val & 0xff);

	if (val & 1)

	    qemu_system_reset_request();

	break;

    case 0xa000000:

	MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);

#if 0

	// XXX: halting CPU does not work

	raise_exception(EXCP_HLT);

	cpu_loop_exit();

#endif

	break;

    }

}

static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)

{

    MiscState *s = opaque;

    uint32_t ret = 0;

    switch (addr & 0xfff0000) {

    case 0x1800000:

	ret = s->config;

	MISC_DPRINTF("Read config %2.2x\n", ret);

	break;

    case 0x1900000:

	ret = s->aux1;

	MISC_DPRINTF("Read aux1 %2.2x\n", ret);

	break;

    case 0x1910000:

	ret = s->aux2;

	MISC_DPRINTF("Read aux2 %2.2x\n", ret);

	break;

    case 0x1a00000:

	ret = s->diag;

	MISC_DPRINTF("Read diag %2.2x\n", ret);

	break;

    case 0x1b00000:

	ret = s->mctrl;

	MISC_DPRINTF("Read modem control %2.2x\n", ret);

	break;

    case 0x1f00000:

	MISC_DPRINTF("Read system control %2.2x\n", ret);

	break;

    case 0xa000000:

	MISC_DPRINTF("Read power management %2.2x\n", ret);

	break;

    }

    return ret;

}

static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {

    slavio_misc_mem_readb,

    slavio_misc_mem_readb,

    slavio_misc_mem_readb,

};

static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {

    slavio_misc_mem_writeb,

    slavio_misc_mem_writeb,

    slavio_misc_mem_writeb,

};

static void slavio_misc_save(QEMUFile *f, void *opaque)

{

    MiscState *s = opaque;

    qemu_put_be32s(f, &s->irq);

    qemu_put_8s(f, &s->config);

    qemu_put_8s(f, &s->aux1);

    qemu_put_8s(f, &s->aux2);

    qemu_put_8s(f, &s->diag);

    qemu_put_8s(f, &s->mctrl);

}

static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)

{

    MiscState *s = opaque;

    if (version_id != 1)

        return -EINVAL;

    qemu_get_be32s(f, &s->irq);

    qemu_get_8s(f, &s->config);

    qemu_get_8s(f, &s->aux1);

    qemu_get_8s(f, &s->aux2);

    qemu_get_8s(f, &s->diag);

    qemu_get_8s(f, &s->mctrl);

    return 0;

}

void *slavio_misc_init(uint32_t base, int irq)

{

    int slavio_misc_io_memory;

    MiscState *s;

    s = qemu_mallocz(sizeof(MiscState));

    if (!s)

        return NULL;

    slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read, slavio_misc_mem_write, s);

    // Slavio control

    cpu_register_physical_memory(base + 0x1800000, MISC_MAXADDR, slavio_misc_io_memory);

    // AUX 1

    cpu_register_physical_memory(base + 0x1900000, MISC_MAXADDR, slavio_misc_io_memory);

    // AUX 2

    cpu_register_physical_memory(base + 0x1910000, MISC_MAXADDR, slavio_misc_io_memory);

    // Diagnostics

    cpu_register_physical_memory(base + 0x1a00000, MISC_MAXADDR, slavio_misc_io_memory);

    // Modem control

    cpu_register_physical_memory(base + 0x1b00000, MISC_MAXADDR, slavio_misc_io_memory);

    // System control

    cpu_register_physical_memory(base + 0x1f00000, MISC_MAXADDR, slavio_misc_io_memory);

    // Power management

    cpu_register_physical_memory(base + 0xa000000, MISC_MAXADDR, slavio_misc_io_memory);

    s->irq = irq;

    register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load, s);

    qemu_register_reset(slavio_misc_reset, s);

    slavio_misc_reset(s);

    return s;

}

#define PHYS_JJ_SLAVIO	0x70000000	/* Slavio base */

#define PHYS_JJ_ME_IRQ 30		/* Module error, power fail */

static void *slavio_misc;

void qemu_system_powerdown(void)

{

    slavio_set_power_fail(slavio_misc, 1);

}

    slavio_misc = slavio_misc_init(PHYS_JJ_SLAVIO, PHYS_JJ_ME_IRQ);

/*

 * QEMU Sun4u System Emulator

 * 

 * Copyright (c) 2005 Fabrice Bellard

 * 

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "vl.h"

#include "m48t08.h"

#define KERNEL_LOAD_ADDR     0x00004000

#define CMDLINE_ADDR         0x007ff000

#define INITRD_LOAD_ADDR     0x00800000

#define PROM_ADDR	     0xffd00000

#define PROM_FILENAMEB	     "proll-sparc64.bin"

#define PROM_FILENAMEE	     "proll-sparc64.elf"

#define PHYS_JJ_EEPROM	0x71200000	/* m48t08 */

#define PHYS_JJ_IDPROM_OFF	0x1FD8

#define PHYS_JJ_EEPROM_SIZE	0x2000

// IRQs are not PIL ones, but master interrupt controller register

// bits

#define PHYS_JJ_MS_KBD	0x71000000	/* Mouse and keyboard */

#define PHYS_JJ_MS_KBD_IRQ    14

#define PHYS_JJ_SER	0x71100000	/* Serial */

#define PHYS_JJ_SER_IRQ    15

/* TSC handling */

uint64_t cpu_get_tsc()

{

    return qemu_get_clock(vm_clock);

}

int DMA_get_channel_mode (int nchan)

{

    return 0;

}

int DMA_read_memory (int nchan, void *buf, int pos, int size)

{

    return 0;

}

int DMA_write_memory (int nchan, void *buf, int pos, int size)

{

    return 0;

}

void DMA_hold_DREQ (int nchan) {}

void DMA_release_DREQ (int nchan) {}

void DMA_schedule(int nchan) {}

void DMA_run (void) {}

void DMA_init (int high_page_enable) {}

void DMA_register_channel (int nchan,

                           DMA_transfer_handler transfer_handler,

                           void *opaque)

{

}

static void nvram_set_word (m48t08_t *nvram, uint32_t addr, uint16_t value)

{

    m48t08_write(nvram, addr++, (value >> 8) & 0xff);

    m48t08_write(nvram, addr++, value & 0xff);

}

static void nvram_set_lword (m48t08_t *nvram, uint32_t addr, uint32_t value)

{

    m48t08_write(nvram, addr++, value >> 24);

    m48t08_write(nvram, addr++, (value >> 16) & 0xff);

    m48t08_write(nvram, addr++, (value >> 8) & 0xff);

    m48t08_write(nvram, addr++, value & 0xff);

}

static void nvram_set_string (m48t08_t *nvram, uint32_t addr,

                       const unsigned char *str, uint32_t max)

{

    unsigned int i;

    for (i = 0; i < max && str[i] != '\0'; i++) {

        m48t08_write(nvram, addr + i, str[i]);

    }

    m48t08_write(nvram, addr + max - 1, '\0');

}

static m48t08_t *nvram;

extern int nographic;

static void nvram_init(m48t08_t *nvram, uint8_t *macaddr, const char *cmdline,

		       int boot_device, uint32_t RAM_size,

		       uint32_t kernel_size,

		       int width, int height, int depth)

{

    unsigned char tmp = 0;

    int i, j;

    // Try to match PPC NVRAM

    nvram_set_string(nvram, 0x00, "QEMU_BIOS", 16);

    nvram_set_lword(nvram,  0x10, 0x00000001); /* structure v1 */

    // NVRAM_size, arch not applicable

    m48t08_write(nvram, 0x2F, nographic & 0xff);

    nvram_set_lword(nvram,  0x30, RAM_size);

    m48t08_write(nvram, 0x34, boot_device & 0xff);

    nvram_set_lword(nvram,  0x38, KERNEL_LOAD_ADDR);

    nvram_set_lword(nvram,  0x3C, kernel_size);

    if (cmdline) {

	strcpy(phys_ram_base + CMDLINE_ADDR, cmdline);

	nvram_set_lword(nvram,  0x40, CMDLINE_ADDR);

        nvram_set_lword(nvram,  0x44, strlen(cmdline));

    }

    // initrd_image, initrd_size passed differently

    nvram_set_word(nvram,   0x54, width);

    nvram_set_word(nvram,   0x56, height);

    nvram_set_word(nvram,   0x58, depth);

    // Sun4m specific use

    i = 0x1fd8;

    m48t08_write(nvram, i++, 0x01);

    m48t08_write(nvram, i++, 0x80); /* Sun4m OBP */

    j = 0;

    m48t08_write(nvram, i++, macaddr[j++]);

    m48t08_write(nvram, i++, macaddr[j++]);

    m48t08_write(nvram, i++, macaddr[j++]);

    m48t08_write(nvram, i++, macaddr[j++]);

    m48t08_write(nvram, i++, macaddr[j++]);

    m48t08_write(nvram, i, macaddr[j]);

    /* Calculate checksum */

    for (i = 0x1fd8; i < 0x1fe7; i++) {

	tmp ^= m48t08_read(nvram, i);

    }

    m48t08_write(nvram, 0x1fe7, tmp);

}

void pic_info()

{

}

void irq_info()

{

}

void pic_set_irq(int irq, int level)

{

}

void vga_update_display()

{

}

void vga_invalidate_display()

{

}

void vga_screen_dump(const char *filename)

{

}

void qemu_system_powerdown(void)

{

}

/* Sun4u hardware initialisation */

static void sun4u_init(int ram_size, int vga_ram_size, int boot_device,

             DisplayState *ds, const char **fd_filename, int snapshot,

             const char *kernel_filename, const char *kernel_cmdline,

             const char *initrd_filename)

{

    char buf[1024];

    int ret, linux_boot;

    unsigned int i;

    long vram_size = 0x100000, prom_offset, initrd_size, kernel_size;

    linux_boot = (kernel_filename != NULL);

    /* allocate RAM */

    cpu_register_physical_memory(0, ram_size, 0);

    nvram = m48t08_init(PHYS_JJ_EEPROM, PHYS_JJ_EEPROM_SIZE);

    // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device

    // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device

    slavio_serial_init(PHYS_JJ_SER, PHYS_JJ_SER_IRQ, serial_hds[1], serial_hds[0]);

    prom_offset = ram_size + vram_size;

    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEE);

    ret = load_elf(buf, phys_ram_base + prom_offset);

    if (ret < 0) {

	snprintf(buf, sizeof(buf), "%s/%s", bios_dir, PROM_FILENAMEB);

	ret = load_image(buf, phys_ram_base + prom_offset);

    }

    if (ret < 0) {

	fprintf(stderr, "qemu: could not load prom '%s'\n", 

		buf);

	exit(1);

    }

    cpu_register_physical_memory(PROM_ADDR, (ret + TARGET_PAGE_SIZE) & TARGET_PAGE_MASK, 

                                 prom_offset | IO_MEM_ROM);

    kernel_size = 0;

    if (linux_boot) {

        kernel_size = load_elf(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);

        if (kernel_size < 0)

	    kernel_size = load_aout(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);

	if (kernel_size < 0)

	    kernel_size = load_image(kernel_filename, phys_ram_base + KERNEL_LOAD_ADDR);

        if (kernel_size < 0) {

            fprintf(stderr, "qemu: could not load kernel '%s'\n", 

                    kernel_filename);

	    exit(1);

        }

        /* load initrd */

        initrd_size = 0;

        if (initrd_filename) {

            initrd_size = load_image(initrd_filename, phys_ram_base + INITRD_LOAD_ADDR);

            if (initrd_size < 0) {

                fprintf(stderr, "qemu: could not load initial ram disk '%s'\n", 

                        initrd_filename);

                exit(1);

            }

        }

        if (initrd_size > 0) {

	    for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {

		if (ldl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i)

		    == 0x48647253) { // HdrS

		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);

		    stl_raw(phys_ram_base + KERNEL_LOAD_ADDR + i + 20, initrd_size);

		    break;

		}

	    }

        }

    }

    nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline, boot_device, ram_size, kernel_size, graphic_width, graphic_height, graphic_depth);

}

QEMUMachine sun4u_machine = {

    "sun4u",

    "Sun4u platform",

    sun4u_init,

};

#ifndef TARGET_SPARC64

#else

	    // XXX

#endif

static void do_system_powerdown(void)

{

    qemu_system_powerdown_request();

}

    { "system_powerdown", "", do_system_powerdown, 

      "", "send system power down event" },

@item Sun4m (32-bit Sparc processor)

@item Sun4u (64-bit Sparc processor, in progress)

For user emulation, x86, PowerPC, ARM, and Sparc32/64 CPUs are supported.

@chapter Sparc32 System emulator invocation

(sun4m architecture). The emulation is somewhat complete.

@item

Slave I/O: timers, interrupt controllers, Zilog serial ports, keyboard

and power/reset logic

@item

ESP SCSI controller with hard disk and CD-ROM support

@item

Floppy drive

The number of peripherals is fixed in the architecture.

@url{http://people.redhat.com/zaitcev/linux/}. The required

QEMU-specific patches are included with the sources.

A sample Linux 2.6 series kernel and ram disk image are available on

the QEMU web site. Please note that currently neither Linux 2.4

series, NetBSD, nor OpenBSD kernels work.

@c man begin OPTIONS

The following options are specific to the Sparc emulation:

@table @option

@item -g WxH

Set the initial TCX graphic mode. The default is 1024x768.

@end table