Revision 3475187d target-sparc/cpu.h

b/target-sparc/cpu.h
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#if !defined(TARGET_SPARC64)
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#define TARGET_LONG_BITS 32
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#define TARGET_FPREGS 32
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#define TARGET_FPREG_T float
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#else
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#define TARGET_LONG_BITS 64
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#define TARGET_FPREGS 64
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#define TARGET_FPREG_T double
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#endif
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#define TARGET_FPREG_T float
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#include "cpu-defs.h"
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......
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/*#define EXCP_INTERRUPT 0x100*/
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/* trap definitions */
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#ifndef TARGET_SPARC64
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#define TT_TFAULT   0x01
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#define TT_ILL_INSN 0x02
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#define TT_PRIV_INSN 0x03
......
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#define TT_EXTINT   0x10
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#define TT_DIV_ZERO 0x2a
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#define TT_TRAP     0x80
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#else
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#define TT_TFAULT   0x08
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#define TT_ILL_INSN 0x10
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#define TT_PRIV_INSN 0x11
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#define TT_NFPU_INSN 0x20
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#define TT_FP_EXCP  0x21
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#define TT_CLRWIN   0x24
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#define TT_DIV_ZERO 0x28
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#define TT_DFAULT   0x30
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#define TT_EXTINT   0x40
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#define TT_SPILL    0x80
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#define TT_FILL     0xc0
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#define TT_WOTHER   0x10
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#define TT_TRAP     0x100
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#endif
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#define PSR_NEG   (1<<23)
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#define PSR_ZERO  (1<<22)
......
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/* Trap base register */
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#define TBR_BASE_MASK 0xfffff000
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#if defined(TARGET_SPARC64)
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#define PS_PEF   (1<<4)
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#define PS_AM    (1<<3)
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#define PS_PRIV  (1<<2)
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#define PS_IE    (1<<1)
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#endif
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/* Fcc */
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#define FSR_RD1        (1<<31)
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#define FSR_RD0        (1<<30)
......
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    target_ulong npc;      /* next program counter */
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    target_ulong y;        /* multiply/divide register */
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    uint32_t psr;      /* processor state register */
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    uint32_t fsr;      /* FPU state register */
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    target_ulong fsr;      /* FPU state register */
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    uint32_t cwp;      /* index of current register window (extracted
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                          from PSR) */
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    uint32_t wim;      /* window invalid mask */
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    uint32_t tbr;      /* trap base register */
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    target_ulong tbr;  /* trap base register */
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    int      psrs;     /* supervisor mode (extracted from PSR) */
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    int      psrps;    /* previous supervisor mode */
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    int      psret;    /* enable traps */
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    int      psrpil;   /* interrupt level */
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    uint32_t psrpil;   /* interrupt level */
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    int      psref;    /* enable fpu */
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    jmp_buf  jmp_env;
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    int user_mode_only;
......
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    CPUTLBEntry tlb_read[2][CPU_TLB_SIZE];
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    CPUTLBEntry tlb_write[2][CPU_TLB_SIZE];
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    /* MMU regs */
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#if defined(TARGET_SPARC64)
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    uint64_t lsu;
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#define DMMU_E 0x8
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#define IMMU_E 0x4
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    uint64_t immuregs[16];
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    uint64_t dmmuregs[16];
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    uint64_t itlb_tag[64];
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    uint64_t itlb_tte[64];
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    uint64_t dtlb_tag[64];
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    uint64_t dtlb_tte[64];
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#else
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    uint32_t mmuregs[16];
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#endif
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    /* temporary float registers */
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    float ft0, ft1, ft2;
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    double dt0, dt1, dt2;
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    float ft0, ft1;
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    double dt0, dt1;
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    float_status fp_status;
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#if defined(TARGET_SPARC64)
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    target_ulong t0, t1, t2;
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#define MAXTL 4
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    uint64_t t0, t1, t2;
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    uint64_t tpc[MAXTL];
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    uint64_t tnpc[MAXTL];
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    uint64_t tstate[MAXTL];
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    uint32_t tt[MAXTL];
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    uint32_t xcc;		/* Extended integer condition codes */
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    uint32_t asi;
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    uint32_t pstate;
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    uint32_t tl;
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    uint32_t cansave, canrestore, otherwin, wstate, cleanwin;
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    target_ulong agregs[8]; /* alternate general registers */
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    target_ulong igregs[8]; /* interrupt general registers */
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    target_ulong mgregs[8]; /* mmu general registers */
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    uint64_t version;
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    uint64_t fprs;
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#endif
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#if !defined(TARGET_SPARC64) && !defined(reg_T2)
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    target_ulong t2;
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#endif
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    /* ice debug support */
......
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    int singlestep_enabled; /* XXX: should use CPU single step mode instead */
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} CPUSPARCState;
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#if defined(TARGET_SPARC64)
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#define GET_FSR32(env) (env->fsr & 0xcfc1ffff)
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val;			\
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	env->fsr = (_tmp & 0xcfc1c3ff) | (env->fsr & 0x3f00000000ULL);	\
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    } while (0)
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#define GET_FSR64(env) (env->fsr & 0x3fcfc1ffffULL)
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#define PUT_FSR64(env, val) do { uint64_t _tmp = val;	\
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	env->fsr = _tmp & 0x3fcfc1c3ffULL;		\
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    } while (0)
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// Manuf 0x17, version 0x11, mask 0 (UltraSparc-II)
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#define GET_VER(env) ((0x17ULL << 48) | (0x11ULL << 32) |		\
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		      (0 << 24) | (MAXTL << 8) | (NWINDOWS - 1))
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#else
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#define GET_FSR32(env) (env->fsr)
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#define PUT_FSR32(env, val) do { uint32_t _tmp = val;	\
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	env->fsr = _tmp & 0xcfc1ffff;			\
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    } while (0)
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#endif
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CPUSPARCState *cpu_sparc_init(void);
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int cpu_sparc_exec(CPUSPARCState *s);
......
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	cpu_set_cwp(env, _tmp & PSR_CWP & (NWINDOWS - 1));		\
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    } while (0)
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#ifdef TARGET_SPARC64
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#define GET_CCR(env) ((env->xcc << 4) | (env->psr & PSR_ICC))
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#define PUT_CCR(env, val) do { int _tmp = val;				\
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	env->xcc = _tmp >> 4;						\
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	env->psr = (_tmp & 0xf) << 20;					\
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    } while (0)
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#endif
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struct siginfo;
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int cpu_sparc_signal_handler(int hostsignum, struct siginfo *info, void *puc);
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