Revision 3475187d vl.c
| b/vl.c | ||
|---|---|---|
| 2375 | 2375 |
qemu_put_betls(f, &env->y); |
| 2376 | 2376 |
tmp = GET_PSR(env); |
| 2377 | 2377 |
qemu_put_be32(f, tmp); |
| 2378 |
qemu_put_be32s(f, &env->fsr); |
|
| 2378 |
qemu_put_betls(f, &env->fsr); |
|
| 2379 |
qemu_put_betls(f, &env->tbr); |
|
| 2380 |
#ifndef TARGET_SPARC64 |
|
| 2379 | 2381 |
qemu_put_be32s(f, &env->wim); |
| 2380 |
qemu_put_be32s(f, &env->tbr); |
|
| 2381 | 2382 |
/* MMU */ |
| 2382 | 2383 |
for(i = 0; i < 16; i++) |
| 2383 | 2384 |
qemu_put_be32s(f, &env->mmuregs[i]); |
| 2385 |
#endif |
|
| 2384 | 2386 |
} |
| 2385 | 2387 |
|
| 2386 | 2388 |
int cpu_load(QEMUFile *f, void *opaque, int version_id) |
| ... | ... | |
| 2411 | 2413 |
env->cwp = 0; /* needed to ensure that the wrapping registers are |
| 2412 | 2414 |
correctly updated */ |
| 2413 | 2415 |
PUT_PSR(env, tmp); |
| 2414 |
qemu_get_be32s(f, &env->fsr); |
|
| 2416 |
qemu_get_betls(f, &env->fsr); |
|
| 2417 |
qemu_get_betls(f, &env->tbr); |
|
| 2418 |
#ifndef TARGET_SPARC64 |
|
| 2415 | 2419 |
qemu_get_be32s(f, &env->wim); |
| 2416 |
qemu_get_be32s(f, &env->tbr); |
|
| 2417 | 2420 |
/* MMU */ |
| 2418 | 2421 |
for(i = 0; i < 16; i++) |
| 2419 | 2422 |
qemu_get_be32s(f, &env->mmuregs[i]); |
| 2420 |
|
|
| 2423 |
#endif |
|
| 2421 | 2424 |
tlb_flush(env, 1); |
| 2422 | 2425 |
return 0; |
| 2423 | 2426 |
} |
| ... | ... | |
| 2577 | 2580 |
static QEMUResetEntry *first_reset_entry; |
| 2578 | 2581 |
static int reset_requested; |
| 2579 | 2582 |
static int shutdown_requested; |
| 2583 |
static int powerdown_requested; |
|
| 2580 | 2584 |
|
| 2581 | 2585 |
void qemu_register_reset(QEMUResetHandler *func, void *opaque) |
| 2582 | 2586 |
{
|
| ... | ... | |
| 2614 | 2618 |
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT); |
| 2615 | 2619 |
} |
| 2616 | 2620 |
|
| 2621 |
void qemu_system_powerdown_request(void) |
|
| 2622 |
{
|
|
| 2623 |
powerdown_requested = 1; |
|
| 2624 |
cpu_interrupt(cpu_single_env, CPU_INTERRUPT_EXIT); |
|
| 2625 |
} |
|
| 2626 |
|
|
| 2617 | 2627 |
static void main_cpu_reset(void *opaque) |
| 2618 | 2628 |
{
|
| 2619 | 2629 |
#if defined(TARGET_I386) || defined(TARGET_SPARC) |
| ... | ... | |
| 2728 | 2738 |
if (vm_running) {
|
| 2729 | 2739 |
ret = cpu_exec(env); |
| 2730 | 2740 |
if (shutdown_requested) {
|
| 2731 |
ret = EXCP_INTERRUPT;
|
|
| 2741 |
ret = EXCP_INTERRUPT; |
|
| 2732 | 2742 |
break; |
| 2733 | 2743 |
} |
| 2734 | 2744 |
if (reset_requested) {
|
| 2735 | 2745 |
reset_requested = 0; |
| 2736 | 2746 |
qemu_system_reset(); |
| 2737 |
ret = EXCP_INTERRUPT; |
|
| 2747 |
ret = EXCP_INTERRUPT; |
|
| 2748 |
} |
|
| 2749 |
if (powerdown_requested) {
|
|
| 2750 |
powerdown_requested = 0; |
|
| 2751 |
qemu_system_powerdown(); |
|
| 2752 |
ret = EXCP_INTERRUPT; |
|
| 2738 | 2753 |
} |
| 2739 | 2754 |
if (ret == EXCP_DEBUG) {
|
| 2740 | 2755 |
vm_stop(EXCP_DEBUG); |
| 2741 | 2756 |
} |
| 2742 | 2757 |
/* if hlt instruction, we wait until the next IRQ */ |
| 2743 | 2758 |
/* XXX: use timeout computed from timers */ |
| 2744 |
if (ret == EXCP_HLT)
|
|
| 2759 |
if (ret == EXCP_HLT) |
|
| 2745 | 2760 |
timeout = 10; |
| 2746 | 2761 |
else |
| 2747 | 2762 |
timeout = 0; |
| ... | ... | |
| 3044 | 3059 |
qemu_register_machine(&core99_machine); |
| 3045 | 3060 |
qemu_register_machine(&prep_machine); |
| 3046 | 3061 |
#elif defined(TARGET_SPARC) |
| 3062 |
#ifdef TARGET_SPARC64 |
|
| 3063 |
qemu_register_machine(&sun4u_machine); |
|
| 3064 |
#else |
|
| 3047 | 3065 |
qemu_register_machine(&sun4m_machine); |
| 3048 | 3066 |
#endif |
| 3067 |
#endif |
|
| 3049 | 3068 |
} |
| 3050 | 3069 |
|
| 3051 | 3070 |
#define NET_IF_TUN 0 |
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