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/*
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* sparc helpers
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*
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* Copyright (c) 2003 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "exec.h" |
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|
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//#define DEBUG_PCALL
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//#define DEBUG_MMU
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|
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/* Sparc MMU emulation */
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|
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/* thread support */
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|
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spinlock_t global_cpu_lock = SPIN_LOCK_UNLOCKED; |
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|
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void cpu_lock(void) |
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{
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spin_lock(&global_cpu_lock); |
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} |
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|
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void cpu_unlock(void) |
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{
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spin_unlock(&global_cpu_lock); |
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} |
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|
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#if defined(CONFIG_USER_ONLY)
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|
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int cpu_sparc_handle_mmu_fault(CPUState *env, target_ulong address, int rw, |
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int is_user, int is_softmmu) |
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{
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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#else
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|
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#define MMUSUFFIX _mmu
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#define GETPC() (__builtin_return_address(0)) |
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|
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#define SHIFT 0 |
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#include "softmmu_template.h" |
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|
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#define SHIFT 1 |
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#include "softmmu_template.h" |
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#define SHIFT 2 |
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#include "softmmu_template.h" |
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|
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#define SHIFT 3 |
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#include "softmmu_template.h" |
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/* try to fill the TLB and return an exception if error. If retaddr is
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NULL, it means that the function was called in C code (i.e. not
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from generated code or from helper.c) */
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/* XXX: fix it to restore all registers */
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void tlb_fill(target_ulong addr, int is_write, int is_user, void *retaddr) |
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{
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TranslationBlock *tb; |
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int ret;
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unsigned long pc; |
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CPUState *saved_env; |
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|
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/* XXX: hack to restore env in all cases, even if not called from
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generated code */
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saved_env = env; |
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env = cpu_single_env; |
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|
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ret = cpu_sparc_handle_mmu_fault(env, addr, is_write, is_user, 1);
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if (ret) {
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if (retaddr) {
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/* now we have a real cpu fault */
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pc = (unsigned long)retaddr; |
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tb = tb_find_pc(pc); |
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if (tb) {
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/* the PC is inside the translated code. It means that we have
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a virtual CPU fault */
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cpu_restore_state(tb, env, pc, (void *)T2);
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} |
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} |
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cpu_loop_exit(); |
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} |
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env = saved_env; |
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} |
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|
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#ifndef TARGET_SPARC64
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static const int access_table[8][8] = { |
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{ 0, 0, 0, 0, 2, 0, 3, 3 },
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{ 0, 0, 0, 0, 2, 0, 0, 0 },
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{ 2, 2, 0, 0, 0, 2, 3, 3 },
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{ 2, 2, 0, 0, 0, 2, 0, 0 },
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{ 2, 0, 2, 0, 2, 2, 3, 3 },
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{ 2, 0, 2, 0, 2, 0, 2, 0 },
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{ 2, 2, 2, 0, 2, 2, 3, 3 },
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{ 2, 2, 2, 0, 2, 2, 2, 0 }
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}; |
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|
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/* 1 = write OK */
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static const int rw_table[2][8] = { |
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{ 0, 1, 0, 1, 0, 1, 0, 1 },
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{ 0, 1, 0, 1, 0, 0, 0, 0 }
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}; |
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|
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int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot, |
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int *access_index, target_ulong address, int rw, |
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int is_user)
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{
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int access_perms = 0; |
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target_phys_addr_t pde_ptr; |
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uint32_t pde; |
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target_ulong virt_addr; |
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int error_code = 0, is_dirty; |
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unsigned long page_offset; |
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|
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virt_addr = address & TARGET_PAGE_MASK; |
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if ((env->mmuregs[0] & MMU_E) == 0) { /* MMU disabled */ |
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*physical = address; |
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*prot = PAGE_READ | PAGE_WRITE; |
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return 0; |
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} |
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|
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*access_index = ((rw & 1) << 2) | (rw & 2) | (is_user? 0 : 1); |
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*physical = 0xfffff000;
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|
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/* SPARC reference MMU table walk: Context table->L1->L2->PTE */
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/* Context base + context number */
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pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
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pde = ldl_phys(pde_ptr); |
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|
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/* Ctx pde */
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return 1 << 2; |
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case 2: /* L0 PTE, maybe should not happen? */ |
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case 3: /* Reserved */ |
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return 4 << 2; |
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case 1: /* L0 PDE */ |
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pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (1 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (1 << 8) | (4 << 2); |
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case 1: /* L1 PDE */ |
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pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (2 << 8) | (1 << 2); |
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case 3: /* Reserved */ |
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return (2 << 8) | (4 << 2); |
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case 1: /* L2 PDE */ |
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pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
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pde = ldl_phys(pde_ptr); |
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|
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switch (pde & PTE_ENTRYTYPE_MASK) {
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default:
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case 0: /* Invalid */ |
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return (3 << 8) | (1 << 2); |
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case 1: /* PDE, should not happen */ |
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case 3: /* Reserved */ |
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return (3 << 8) | (4 << 2); |
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case 2: /* L3 PTE */ |
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virt_addr = address & TARGET_PAGE_MASK; |
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page_offset = (address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1);
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} |
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break;
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case 2: /* L2 PTE */ |
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virt_addr = address & ~0x3ffff;
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page_offset = address & 0x3ffff;
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} |
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break;
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case 2: /* L1 PTE */ |
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virt_addr = address & ~0xffffff;
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page_offset = address & 0xffffff;
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} |
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} |
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|
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/* update page modified and dirty bits */
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is_dirty = (rw & 1) && !(pde & PG_MODIFIED_MASK);
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if (!(pde & PG_ACCESSED_MASK) || is_dirty) {
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pde |= PG_ACCESSED_MASK; |
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if (is_dirty)
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pde |= PG_MODIFIED_MASK; |
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stl_phys_notdirty(pde_ptr, pde); |
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} |
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/* check access */
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access_perms = (pde & PTE_ACCESS_MASK) >> PTE_ACCESS_SHIFT; |
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error_code = access_table[*access_index][access_perms]; |
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if (error_code && !(env->mmuregs[0] & MMU_NF)) |
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return error_code;
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|
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/* the page can be put in the TLB */
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*prot = PAGE_READ; |
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if (pde & PG_MODIFIED_MASK) {
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/* only set write access if already dirty... otherwise wait
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for dirty access */
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if (rw_table[is_user][access_perms])
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*prot |= PAGE_WRITE; |
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} |
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/* Even if large ptes, we map only one 4KB page in the cache to
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avoid filling it too fast */
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*physical = ((pde & PTE_ADDR_MASK) << 4) + page_offset;
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return error_code;
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} |
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|
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/* Perform address translation */
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int is_user, int is_softmmu) |
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{
|
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target_ulong virt_addr; |
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target_phys_addr_t paddr; |
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unsigned long vaddr; |
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int error_code = 0, prot, ret = 0, access_index; |
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|
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
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if (error_code == 0) { |
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virt_addr = address & TARGET_PAGE_MASK; |
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vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
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return ret;
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} |
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|
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if (env->mmuregs[3]) /* Fault status register */ |
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env->mmuregs[3] = 1; /* overflow (not read before another fault) */ |
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env->mmuregs[3] |= (access_index << 5) | error_code | 2; |
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env->mmuregs[4] = address; /* Fault address register */ |
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|
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if ((env->mmuregs[0] & MMU_NF) || env->psret == 0) { |
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// No fault mode: if a mapping is available, just override
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// permissions. If no mapping is available, redirect accesses to
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// neverland. Fake/overridden mappings will be flushed when
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// switching to normal mode.
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vaddr = address & TARGET_PAGE_MASK; |
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prot = PAGE_READ | PAGE_WRITE; |
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
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return ret;
|
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} else {
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if (rw & 2) |
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env->exception_index = TT_TFAULT; |
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else
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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} |
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#else
|
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static int get_physical_address_data(CPUState *env, target_phys_addr_t *physical, int *prot, |
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int *access_index, target_ulong address, int rw, |
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int is_user)
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{
|
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target_ulong mask; |
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unsigned int i; |
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|
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if ((env->lsu & DMMU_E) == 0) { /* DMMU disabled */ |
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*physical = address & 0xffffffff;
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*prot = PAGE_READ | PAGE_WRITE; |
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return 0; |
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} |
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|
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for (i = 0; i < 64; i++) { |
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if ((env->dtlb_tte[i] & 0x8000000000000000ULL) != 0) { |
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switch (env->dtlb_tte[i] >> 60) { |
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default:
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case 0x4: // 8k |
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mask = 0xffffffffffffe000ULL;
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break;
|
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case 0x5: // 64k |
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mask = 0xffffffffffff0000ULL;
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break;
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case 0x6: // 512k |
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mask = 0xfffffffffff80000ULL;
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break;
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case 0x7: // 4M |
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mask = 0xffffffffffc00000ULL;
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break;
|
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} |
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// ctx match, vaddr match?
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if (env->dmmuregs[1] == (env->dtlb_tag[i] & 0x1fff) && |
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(address & mask) == (env->dtlb_tag[i] & ~0x1fffULL)) {
|
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// access ok?
|
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if (((env->dtlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) || |
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(!(env->dtlb_tte[i] & 0x2) && (rw == 1))) { |
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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*physical = env->dtlb_tte[i] & 0xffffe000;
|
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*prot = PAGE_READ; |
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if (env->dtlb_tte[i] & 0x2) |
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*prot |= PAGE_WRITE; |
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return 0; |
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} |
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} |
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} |
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env->exception_index = TT_DFAULT; |
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return 1; |
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} |
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|
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static int get_physical_address_code(CPUState *env, target_phys_addr_t *physical, int *prot, |
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int *access_index, target_ulong address, int rw, |
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int is_user)
|
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{
|
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target_ulong mask; |
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unsigned int i; |
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|
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if ((env->lsu & IMMU_E) == 0) { /* IMMU disabled */ |
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*physical = address & 0xffffffff;
|
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*prot = PAGE_READ; |
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return 0; |
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} |
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for (i = 0; i < 64; i++) { |
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if ((env->itlb_tte[i] & 0x8000000000000000ULL) != 0) { |
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switch (env->itlb_tte[i] >> 60) { |
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default:
|
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case 0x4: // 8k |
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mask = 0xffffffffffffe000ULL;
|
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break;
|
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case 0x5: // 64k |
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mask = 0xffffffffffff0000ULL;
|
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break;
|
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case 0x6: // 512k |
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mask = 0xfffffffffff80000ULL;
|
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break;
|
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case 0x7: // 4M |
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mask = 0xffffffffffc00000ULL;
|
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break;
|
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} |
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// ctx match, vaddr match?
|
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if (env->immuregs[1] == (env->itlb_tag[i] & 0x1fff) && |
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(address & mask) == (env->itlb_tag[i] & ~0x1fffULL)) {
|
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// access ok?
|
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if ((env->itlb_tte[i] & 0x4) && !(env->pstate & PS_PRIV)) { |
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env->exception_index = TT_TFAULT; |
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return 1; |
| 359 |
} |
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*physical = env->itlb_tte[i] & 0xffffe000;
|
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*prot = PAGE_READ; |
| 362 |
return 0; |
| 363 |
} |
| 364 |
} |
| 365 |
} |
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env->exception_index = TT_TFAULT; |
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return 1; |
| 368 |
} |
| 369 |
|
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int get_physical_address(CPUState *env, target_phys_addr_t *physical, int *prot, |
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int *access_index, target_ulong address, int rw, |
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int is_user)
|
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{
|
| 374 |
if (rw == 2) |
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return get_physical_address_code(env, physical, prot, access_index, address, rw, is_user);
|
| 376 |
else
|
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return get_physical_address_data(env, physical, prot, access_index, address, rw, is_user);
|
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} |
| 379 |
|
| 380 |
/* Perform address translation */
|
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int cpu_sparc_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
| 382 |
int is_user, int is_softmmu) |
| 383 |
{
|
| 384 |
target_ulong virt_addr; |
| 385 |
target_phys_addr_t paddr; |
| 386 |
unsigned long vaddr; |
| 387 |
int error_code = 0, prot, ret = 0, access_index; |
| 388 |
|
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error_code = get_physical_address(env, &paddr, &prot, &access_index, address, rw, is_user); |
| 390 |
if (error_code == 0) { |
| 391 |
virt_addr = address & TARGET_PAGE_MASK; |
| 392 |
vaddr = virt_addr + ((address & TARGET_PAGE_MASK) & (TARGET_PAGE_SIZE - 1));
|
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ret = tlb_set_page(env, vaddr, paddr, prot, is_user, is_softmmu); |
| 394 |
return ret;
|
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} |
| 396 |
// XXX
|
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return 1; |
| 398 |
} |
| 399 |
|
| 400 |
#endif
|
| 401 |
#endif
|
| 402 |
|
| 403 |
void memcpy32(target_ulong *dst, const target_ulong *src) |
| 404 |
{
|
| 405 |
dst[0] = src[0]; |
| 406 |
dst[1] = src[1]; |
| 407 |
dst[2] = src[2]; |
| 408 |
dst[3] = src[3]; |
| 409 |
dst[4] = src[4]; |
| 410 |
dst[5] = src[5]; |
| 411 |
dst[6] = src[6]; |
| 412 |
dst[7] = src[7]; |
| 413 |
} |
| 414 |
|
| 415 |
void set_cwp(int new_cwp) |
| 416 |
{
|
| 417 |
/* put the modified wrap registers at their proper location */
|
| 418 |
if (env->cwp == (NWINDOWS - 1)) |
| 419 |
memcpy32(env->regbase, env->regbase + NWINDOWS * 16);
|
| 420 |
env->cwp = new_cwp; |
| 421 |
/* put the wrap registers at their temporary location */
|
| 422 |
if (new_cwp == (NWINDOWS - 1)) |
| 423 |
memcpy32(env->regbase + NWINDOWS * 16, env->regbase);
|
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env->regwptr = env->regbase + (new_cwp * 16);
|
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REGWPTR = env->regwptr; |
| 426 |
} |
| 427 |
|
| 428 |
void cpu_set_cwp(CPUState *env1, int new_cwp) |
| 429 |
{
|
| 430 |
CPUState *saved_env; |
| 431 |
#ifdef reg_REGWPTR
|
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target_ulong *saved_regwptr; |
| 433 |
#endif
|
| 434 |
|
| 435 |
saved_env = env; |
| 436 |
#ifdef reg_REGWPTR
|
| 437 |
saved_regwptr = REGWPTR; |
| 438 |
#endif
|
| 439 |
env = env1; |
| 440 |
set_cwp(new_cwp); |
| 441 |
env = saved_env; |
| 442 |
#ifdef reg_REGWPTR
|
| 443 |
REGWPTR = saved_regwptr; |
| 444 |
#endif
|
| 445 |
} |
| 446 |
|
| 447 |
#ifdef TARGET_SPARC64
|
| 448 |
void do_interrupt(int intno) |
| 449 |
{
|
| 450 |
#ifdef DEBUG_PCALL
|
| 451 |
if (loglevel & CPU_LOG_INT) {
|
| 452 |
static int count; |
| 453 |
fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
|
| 454 |
count, intno, |
| 455 |
env->pc, |
| 456 |
env->npc, env->regwptr[6]);
|
| 457 |
cpu_dump_state(env, logfile, fprintf, 0);
|
| 458 |
#if 0
|
| 459 |
{
|
| 460 |
int i;
|
| 461 |
uint8_t *ptr;
|
| 462 |
|
| 463 |
fprintf(logfile, " code=");
|
| 464 |
ptr = (uint8_t *)env->pc;
|
| 465 |
for(i = 0; i < 16; i++) {
|
| 466 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
| 467 |
}
|
| 468 |
fprintf(logfile, "\n");
|
| 469 |
}
|
| 470 |
#endif
|
| 471 |
count++; |
| 472 |
} |
| 473 |
#endif
|
| 474 |
#if !defined(CONFIG_USER_ONLY)
|
| 475 |
if (env->pstate & PS_IE) {
|
| 476 |
cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
| 477 |
return;
|
| 478 |
} |
| 479 |
#endif
|
| 480 |
env->tstate[env->tl] = ((uint64_t)GET_CCR(env) << 32) | ((env->asi & 0xff) << 24) | |
| 481 |
((env->pstate & 0xfff) << 8) | (env->cwp & 0xff); |
| 482 |
env->tpc[env->tl] = env->pc; |
| 483 |
env->tnpc[env->tl] = env->npc; |
| 484 |
env->tt[env->tl] = intno; |
| 485 |
env->tbr = env->tbr | (env->tl > 1) ? 1 << 14 : 0 | (intno << 4); |
| 486 |
env->tl++; |
| 487 |
env->pc = env->tbr; |
| 488 |
env->npc = env->pc + 4;
|
| 489 |
env->exception_index = 0;
|
| 490 |
} |
| 491 |
#else
|
| 492 |
void do_interrupt(int intno) |
| 493 |
{
|
| 494 |
int cwp;
|
| 495 |
|
| 496 |
#ifdef DEBUG_PCALL
|
| 497 |
if (loglevel & CPU_LOG_INT) {
|
| 498 |
static int count; |
| 499 |
fprintf(logfile, "%6d: v=%02x pc=%08x npc=%08x SP=%08x\n",
|
| 500 |
count, intno, |
| 501 |
env->pc, |
| 502 |
env->npc, env->regwptr[6]);
|
| 503 |
cpu_dump_state(env, logfile, fprintf, 0);
|
| 504 |
#if 0
|
| 505 |
{
|
| 506 |
int i;
|
| 507 |
uint8_t *ptr;
|
| 508 |
|
| 509 |
fprintf(logfile, " code=");
|
| 510 |
ptr = (uint8_t *)env->pc;
|
| 511 |
for(i = 0; i < 16; i++) {
|
| 512 |
fprintf(logfile, " %02x", ldub(ptr + i));
|
| 513 |
}
|
| 514 |
fprintf(logfile, "\n");
|
| 515 |
}
|
| 516 |
#endif
|
| 517 |
count++; |
| 518 |
} |
| 519 |
#endif
|
| 520 |
#if !defined(CONFIG_USER_ONLY)
|
| 521 |
if (env->psret == 0) { |
| 522 |
cpu_abort(cpu_single_env, "Trap 0x%02x while interrupts disabled, Error state", env->exception_index);
|
| 523 |
return;
|
| 524 |
} |
| 525 |
#endif
|
| 526 |
env->psret = 0;
|
| 527 |
cwp = (env->cwp - 1) & (NWINDOWS - 1); |
| 528 |
set_cwp(cwp); |
| 529 |
env->regwptr[9] = env->pc;
|
| 530 |
env->regwptr[10] = env->npc;
|
| 531 |
env->psrps = env->psrs; |
| 532 |
env->psrs = 1;
|
| 533 |
env->tbr = (env->tbr & TBR_BASE_MASK) | (intno << 4);
|
| 534 |
env->pc = env->tbr; |
| 535 |
env->npc = env->pc + 4;
|
| 536 |
env->exception_index = 0;
|
| 537 |
} |
| 538 |
|
| 539 |
target_ulong mmu_probe(target_ulong address, int mmulev)
|
| 540 |
{
|
| 541 |
target_phys_addr_t pde_ptr; |
| 542 |
uint32_t pde; |
| 543 |
|
| 544 |
/* Context base + context number */
|
| 545 |
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
| 546 |
pde = ldl_phys(pde_ptr); |
| 547 |
|
| 548 |
switch (pde & PTE_ENTRYTYPE_MASK) {
|
| 549 |
default:
|
| 550 |
case 0: /* Invalid */ |
| 551 |
case 2: /* PTE, maybe should not happen? */ |
| 552 |
case 3: /* Reserved */ |
| 553 |
return 0; |
| 554 |
case 1: /* L1 PDE */ |
| 555 |
if (mmulev == 3) |
| 556 |
return pde;
|
| 557 |
pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); |
| 558 |
pde = ldl_phys(pde_ptr); |
| 559 |
|
| 560 |
switch (pde & PTE_ENTRYTYPE_MASK) {
|
| 561 |
default:
|
| 562 |
case 0: /* Invalid */ |
| 563 |
case 3: /* Reserved */ |
| 564 |
return 0; |
| 565 |
case 2: /* L1 PTE */ |
| 566 |
return pde;
|
| 567 |
case 1: /* L2 PDE */ |
| 568 |
if (mmulev == 2) |
| 569 |
return pde;
|
| 570 |
pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); |
| 571 |
pde = ldl_phys(pde_ptr); |
| 572 |
|
| 573 |
switch (pde & PTE_ENTRYTYPE_MASK) {
|
| 574 |
default:
|
| 575 |
case 0: /* Invalid */ |
| 576 |
case 3: /* Reserved */ |
| 577 |
return 0; |
| 578 |
case 2: /* L2 PTE */ |
| 579 |
return pde;
|
| 580 |
case 1: /* L3 PDE */ |
| 581 |
if (mmulev == 1) |
| 582 |
return pde;
|
| 583 |
pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); |
| 584 |
pde = ldl_phys(pde_ptr); |
| 585 |
|
| 586 |
switch (pde & PTE_ENTRYTYPE_MASK) {
|
| 587 |
default:
|
| 588 |
case 0: /* Invalid */ |
| 589 |
case 1: /* PDE, should not happen */ |
| 590 |
case 3: /* Reserved */ |
| 591 |
return 0; |
| 592 |
case 2: /* L3 PTE */ |
| 593 |
return pde;
|
| 594 |
} |
| 595 |
} |
| 596 |
} |
| 597 |
} |
| 598 |
return 0; |
| 599 |
} |
| 600 |
|
| 601 |
#ifdef DEBUG_MMU
|
| 602 |
void dump_mmu(void) |
| 603 |
{
|
| 604 |
target_ulong va, va1, va2; |
| 605 |
unsigned int n, m, o; |
| 606 |
target_phys_addr_t pde_ptr, pa; |
| 607 |
uint32_t pde; |
| 608 |
|
| 609 |
printf("MMU dump:\n");
|
| 610 |
pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); |
| 611 |
pde = ldl_phys(pde_ptr); |
| 612 |
printf("Root ptr: " TARGET_FMT_lx ", ctx: %d\n", env->mmuregs[1] << 4, env->mmuregs[2]); |
| 613 |
for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { |
| 614 |
pde_ptr = mmu_probe(va, 2);
|
| 615 |
if (pde_ptr) {
|
| 616 |
pa = cpu_get_phys_page_debug(env, va); |
| 617 |
printf("VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va, pa, pde_ptr); |
| 618 |
for (m = 0, va1 = va; m < 64; m++, va1 += 256 * 1024) { |
| 619 |
pde_ptr = mmu_probe(va1, 1);
|
| 620 |
if (pde_ptr) {
|
| 621 |
pa = cpu_get_phys_page_debug(env, va1); |
| 622 |
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PDE: " TARGET_FMT_lx "\n", va1, pa, pde_ptr); |
| 623 |
for (o = 0, va2 = va1; o < 64; o++, va2 += 4 * 1024) { |
| 624 |
pde_ptr = mmu_probe(va2, 0);
|
| 625 |
if (pde_ptr) {
|
| 626 |
pa = cpu_get_phys_page_debug(env, va2); |
| 627 |
printf(" VA: " TARGET_FMT_lx ", PA: " TARGET_FMT_lx " PTE: " TARGET_FMT_lx "\n", va2, pa, pde_ptr); |
| 628 |
} |
| 629 |
} |
| 630 |
} |
| 631 |
} |
| 632 |
} |
| 633 |
} |
| 634 |
printf("MMU dump ends\n");
|
| 635 |
} |
| 636 |
#endif
|
| 637 |
#endif
|