root / target-sparc / op_helper.c @ 3475187d
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#include "exec.h" |
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//#define DEBUG_MMU
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void raise_exception(int tt) |
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{
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env->exception_index = tt; |
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cpu_loop_exit(); |
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} |
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#ifdef USE_INT_TO_FLOAT_HELPERS
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void do_fitos(void) |
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{
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FT0 = (float) *((int32_t *)&FT1);
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} |
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void do_fitod(void) |
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{
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DT0 = (double) *((int32_t *)&FT1);
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} |
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#endif
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void do_fabss(void) |
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{
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FT0 = float32_abs(FT1); |
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} |
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#ifdef TARGET_SPARC64
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void do_fabsd(void) |
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{
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DT0 = float64_abs(DT1); |
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} |
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#endif
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void do_fsqrts(void) |
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{
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FT0 = float32_sqrt(FT1, &env->fp_status); |
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} |
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void do_fsqrtd(void) |
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{
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DT0 = float64_sqrt(DT1, &env->fp_status); |
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} |
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#define FS 0 |
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void do_fcmps (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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void do_fcmpd (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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#ifdef TARGET_SPARC64
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#undef FS
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#define FS 22 |
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void do_fcmps_fcc1 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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void do_fcmpd_fcc1 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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#undef FS
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#define FS 24 |
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void do_fcmps_fcc2 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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void do_fcmpd_fcc2 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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#undef FS
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#define FS 26 |
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void do_fcmps_fcc3 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(FT0) || isnan(FT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (FT0 < FT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (FT0 > FT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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void do_fcmpd_fcc3 (void) |
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{
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env->fsr &= ~((FSR_FCC1 | FSR_FCC0) << FS); |
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if (isnan(DT0) || isnan(DT1)) {
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T0 = (FSR_FCC1 | FSR_FCC0) << FS; |
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if (env->fsr & FSR_NVM) {
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env->fsr |= T0; |
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raise_exception(TT_FP_EXCP); |
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} else {
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env->fsr |= FSR_NVA; |
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} |
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} else if (DT0 < DT1) { |
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T0 = FSR_FCC0 << FS; |
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} else if (DT0 > DT1) { |
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T0 = FSR_FCC1 << FS; |
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} else {
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T0 = 0;
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} |
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env->fsr |= T0; |
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} |
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#undef FS
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#endif
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#ifndef TARGET_SPARC64
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void helper_ld_asi(int asi, int size, int sign) |
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{
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uint32_t ret; |
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switch (asi) {
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case 3: /* MMU probe */ |
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{
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int mmulev;
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mmulev = (T0 >> 8) & 15; |
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if (mmulev > 4) |
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ret = 0;
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else {
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ret = mmu_probe(T0, mmulev); |
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//bswap32s(&ret);
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} |
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#ifdef DEBUG_MMU
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printf("mmu_probe: 0x%08x (lev %d) -> 0x%08x\n", T0, mmulev, ret);
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#endif
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} |
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break;
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case 4: /* read MMU regs */ |
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{
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int reg = (T0 >> 8) & 0xf; |
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ret = env->mmuregs[reg]; |
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if (reg == 3) /* Fault status cleared on read */ |
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env->mmuregs[reg] = 0;
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#ifdef DEBUG_MMU
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printf("mmu_read: reg[%d] = 0x%08x\n", reg, ret);
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#endif
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} |
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break;
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case 0x20 ... 0x2f: /* MMU passthrough */ |
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cpu_physical_memory_read(T0, (void *) &ret, size);
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if (size == 4) |
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tswap32s(&ret); |
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else if (size == 2) |
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tswap16s((uint16_t *)&ret); |
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break;
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default:
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ret = 0;
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break;
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} |
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T1 = ret; |
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} |
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void helper_st_asi(int asi, int size, int sign) |
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{
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switch(asi) {
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case 3: /* MMU flush */ |
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{
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int mmulev;
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mmulev = (T0 >> 8) & 15; |
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#ifdef DEBUG_MMU
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printf("mmu flush level %d\n", mmulev);
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#endif
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switch (mmulev) {
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case 0: // flush page |
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tlb_flush_page(env, T0 & 0xfffff000);
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break;
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case 1: // flush segment (256k) |
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case 2: // flush region (16M) |
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case 3: // flush context (4G) |
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case 4: // flush entire |
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tlb_flush(env, 1);
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break;
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default:
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break;
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} |
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#ifdef DEBUG_MMU
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dump_mmu(); |
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#endif
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return;
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} |
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case 4: /* write MMU regs */ |
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{
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int reg = (T0 >> 8) & 0xf, oldreg; |
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oldreg = env->mmuregs[reg]; |
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switch(reg) {
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case 0: |
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env->mmuregs[reg] &= ~(MMU_E | MMU_NF); |
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env->mmuregs[reg] |= T1 & (MMU_E | MMU_NF); |
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// Mappings generated during no-fault mode or MMU
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// disabled mode are invalid in normal mode
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if (oldreg != env->mmuregs[reg])
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tlb_flush(env, 1);
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break;
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case 2: |
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env->mmuregs[reg] = T1; |
| 316 |
if (oldreg != env->mmuregs[reg]) {
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/* we flush when the MMU context changes because
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QEMU has no MMU context support */
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tlb_flush(env, 1);
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} |
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break;
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case 3: |
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case 4: |
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break;
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default:
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env->mmuregs[reg] = T1; |
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break;
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} |
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#ifdef DEBUG_MMU
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if (oldreg != env->mmuregs[reg]) {
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printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->mmuregs[reg]);
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} |
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dump_mmu(); |
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#endif
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return;
|
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} |
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case 0x17: /* Block copy, sta access */ |
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{
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// value (T1) = src
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// address (T0) = dst
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// copy 32 bytes
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int src = T1, dst = T0;
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uint8_t temp[32];
|
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|
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tswap32s(&src); |
| 346 |
|
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cpu_physical_memory_read(src, (void *) &temp, 32); |
| 348 |
cpu_physical_memory_write(dst, (void *) &temp, 32); |
| 349 |
} |
| 350 |
return;
|
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case 0x1f: /* Block fill, stda access */ |
| 352 |
{
|
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// value (T1, T2)
|
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// address (T0) = dst
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// fill 32 bytes
|
| 356 |
int i, dst = T0;
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uint64_t val; |
| 358 |
|
| 359 |
val = (((uint64_t)T1) << 32) | T2;
|
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tswap64s(&val); |
| 361 |
|
| 362 |
for (i = 0; i < 32; i += 8, dst += 8) { |
| 363 |
cpu_physical_memory_write(dst, (void *) &val, 8); |
| 364 |
} |
| 365 |
} |
| 366 |
return;
|
| 367 |
case 0x20 ... 0x2f: /* MMU passthrough */ |
| 368 |
{
|
| 369 |
int temp = T1;
|
| 370 |
if (size == 4) |
| 371 |
tswap32s(&temp); |
| 372 |
else if (size == 2) |
| 373 |
tswap16s((uint16_t *)&temp); |
| 374 |
cpu_physical_memory_write(T0, (void *) &temp, size);
|
| 375 |
} |
| 376 |
return;
|
| 377 |
default:
|
| 378 |
return;
|
| 379 |
} |
| 380 |
} |
| 381 |
|
| 382 |
#else
|
| 383 |
|
| 384 |
void helper_ld_asi(int asi, int size, int sign) |
| 385 |
{
|
| 386 |
uint64_t ret; |
| 387 |
|
| 388 |
if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 389 |
raise_exception(TT_PRIV_INSN); |
| 390 |
|
| 391 |
switch (asi) {
|
| 392 |
case 0x14: // Bypass |
| 393 |
case 0x15: // Bypass, non-cacheable |
| 394 |
{
|
| 395 |
cpu_physical_memory_read(T0, (void *) &ret, size);
|
| 396 |
if (size == 8) |
| 397 |
tswap64s(&ret); |
| 398 |
if (size == 4) |
| 399 |
tswap32s((uint32_t *)&ret); |
| 400 |
else if (size == 2) |
| 401 |
tswap16s((uint16_t *)&ret); |
| 402 |
break;
|
| 403 |
} |
| 404 |
case 0x1c: // Bypass LE |
| 405 |
case 0x1d: // Bypass, non-cacheable LE |
| 406 |
// XXX
|
| 407 |
break;
|
| 408 |
case 0x45: // LSU |
| 409 |
ret = env->lsu; |
| 410 |
break;
|
| 411 |
case 0x50: // I-MMU regs |
| 412 |
{
|
| 413 |
int reg = (T0 >> 3) & 0xf; |
| 414 |
|
| 415 |
ret = env->immuregs[reg]; |
| 416 |
break;
|
| 417 |
} |
| 418 |
case 0x51: // I-MMU 8k TSB pointer |
| 419 |
case 0x52: // I-MMU 64k TSB pointer |
| 420 |
case 0x55: // I-MMU data access |
| 421 |
case 0x56: // I-MMU tag read |
| 422 |
break;
|
| 423 |
case 0x58: // D-MMU regs |
| 424 |
{
|
| 425 |
int reg = (T0 >> 3) & 0xf; |
| 426 |
|
| 427 |
ret = env->dmmuregs[reg]; |
| 428 |
break;
|
| 429 |
} |
| 430 |
case 0x59: // D-MMU 8k TSB pointer |
| 431 |
case 0x5a: // D-MMU 64k TSB pointer |
| 432 |
case 0x5b: // D-MMU data pointer |
| 433 |
case 0x5d: // D-MMU data access |
| 434 |
case 0x5e: // D-MMU tag read |
| 435 |
break;
|
| 436 |
case 0x54: // I-MMU data in, WO |
| 437 |
case 0x57: // I-MMU demap, WO |
| 438 |
case 0x5c: // D-MMU data in, WO |
| 439 |
case 0x5f: // D-MMU demap, WO |
| 440 |
default:
|
| 441 |
ret = 0;
|
| 442 |
break;
|
| 443 |
} |
| 444 |
T1 = ret; |
| 445 |
} |
| 446 |
|
| 447 |
void helper_st_asi(int asi, int size, int sign) |
| 448 |
{
|
| 449 |
if (asi < 0x80 && (env->pstate & PS_PRIV) == 0) |
| 450 |
raise_exception(TT_PRIV_INSN); |
| 451 |
|
| 452 |
switch(asi) {
|
| 453 |
case 0x14: // Bypass |
| 454 |
case 0x15: // Bypass, non-cacheable |
| 455 |
{
|
| 456 |
target_ulong temp = T1; |
| 457 |
if (size == 8) |
| 458 |
tswap64s(&temp); |
| 459 |
else if (size == 4) |
| 460 |
tswap32s((uint32_t *)&temp); |
| 461 |
else if (size == 2) |
| 462 |
tswap16s((uint16_t *)&temp); |
| 463 |
cpu_physical_memory_write(T0, (void *) &temp, size);
|
| 464 |
} |
| 465 |
return;
|
| 466 |
case 0x1c: // Bypass LE |
| 467 |
case 0x1d: // Bypass, non-cacheable LE |
| 468 |
// XXX
|
| 469 |
return;
|
| 470 |
case 0x45: // LSU |
| 471 |
{
|
| 472 |
uint64_t oldreg; |
| 473 |
|
| 474 |
oldreg = env->lsu; |
| 475 |
env->lsu = T1 & (DMMU_E | IMMU_E); |
| 476 |
// Mappings generated during D/I MMU disabled mode are
|
| 477 |
// invalid in normal mode
|
| 478 |
if (oldreg != env->lsu)
|
| 479 |
tlb_flush(env, 1);
|
| 480 |
return;
|
| 481 |
} |
| 482 |
case 0x50: // I-MMU regs |
| 483 |
{
|
| 484 |
int reg = (T0 >> 3) & 0xf; |
| 485 |
uint64_t oldreg; |
| 486 |
|
| 487 |
oldreg = env->immuregs[reg]; |
| 488 |
switch(reg) {
|
| 489 |
case 0: // RO |
| 490 |
case 4: |
| 491 |
return;
|
| 492 |
case 1: // Not in I-MMU |
| 493 |
case 2: |
| 494 |
case 7: |
| 495 |
case 8: |
| 496 |
return;
|
| 497 |
case 3: // SFSR |
| 498 |
if ((T1 & 1) == 0) |
| 499 |
T1 = 0; // Clear SFSR |
| 500 |
break;
|
| 501 |
case 5: // TSB access |
| 502 |
case 6: // Tag access |
| 503 |
default:
|
| 504 |
break;
|
| 505 |
} |
| 506 |
env->immuregs[reg] = T1; |
| 507 |
#ifdef DEBUG_MMU
|
| 508 |
if (oldreg != env->immuregs[reg]) {
|
| 509 |
printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->immuregs[reg]);
|
| 510 |
} |
| 511 |
dump_mmu(); |
| 512 |
#endif
|
| 513 |
return;
|
| 514 |
} |
| 515 |
case 0x54: // I-MMU data in |
| 516 |
{
|
| 517 |
unsigned int i; |
| 518 |
|
| 519 |
// Try finding an invalid entry
|
| 520 |
for (i = 0; i < 64; i++) { |
| 521 |
if ((env->itlb_tte[i] & 0x8000000000000000ULL) == 0) { |
| 522 |
env->itlb_tag[i] = env->immuregs[6];
|
| 523 |
env->itlb_tte[i] = T1; |
| 524 |
return;
|
| 525 |
} |
| 526 |
} |
| 527 |
// Try finding an unlocked entry
|
| 528 |
for (i = 0; i < 64; i++) { |
| 529 |
if ((env->itlb_tte[i] & 0x40) == 0) { |
| 530 |
env->itlb_tag[i] = env->immuregs[6];
|
| 531 |
env->itlb_tte[i] = T1; |
| 532 |
return;
|
| 533 |
} |
| 534 |
} |
| 535 |
// error state?
|
| 536 |
return;
|
| 537 |
} |
| 538 |
case 0x55: // I-MMU data access |
| 539 |
{
|
| 540 |
unsigned int i = (T0 >> 3) & 0x3f; |
| 541 |
|
| 542 |
env->itlb_tag[i] = env->immuregs[6];
|
| 543 |
env->itlb_tte[i] = T1; |
| 544 |
return;
|
| 545 |
} |
| 546 |
case 0x57: // I-MMU demap |
| 547 |
return;
|
| 548 |
case 0x58: // D-MMU regs |
| 549 |
{
|
| 550 |
int reg = (T0 >> 3) & 0xf; |
| 551 |
uint64_t oldreg; |
| 552 |
|
| 553 |
oldreg = env->dmmuregs[reg]; |
| 554 |
switch(reg) {
|
| 555 |
case 0: // RO |
| 556 |
case 4: |
| 557 |
return;
|
| 558 |
case 3: // SFSR |
| 559 |
if ((T1 & 1) == 0) { |
| 560 |
T1 = 0; // Clear SFSR, Fault address |
| 561 |
env->dmmuregs[4] = 0; |
| 562 |
} |
| 563 |
env->dmmuregs[reg] = T1; |
| 564 |
break;
|
| 565 |
case 1: // Primary context |
| 566 |
case 2: // Secondary context |
| 567 |
case 5: // TSB access |
| 568 |
case 6: // Tag access |
| 569 |
case 7: // Virtual Watchpoint |
| 570 |
case 8: // Physical Watchpoint |
| 571 |
default:
|
| 572 |
break;
|
| 573 |
} |
| 574 |
env->dmmuregs[reg] = T1; |
| 575 |
#ifdef DEBUG_MMU
|
| 576 |
if (oldreg != env->dmmuregs[reg]) {
|
| 577 |
printf("mmu change reg[%d]: 0x%08x -> 0x%08x\n", reg, oldreg, env->dmmuregs[reg]);
|
| 578 |
} |
| 579 |
dump_mmu(); |
| 580 |
#endif
|
| 581 |
return;
|
| 582 |
} |
| 583 |
case 0x5c: // D-MMU data in |
| 584 |
{
|
| 585 |
unsigned int i; |
| 586 |
|
| 587 |
// Try finding an invalid entry
|
| 588 |
for (i = 0; i < 64; i++) { |
| 589 |
if ((env->dtlb_tte[i] & 0x8000000000000000ULL) == 0) { |
| 590 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
| 591 |
env->dtlb_tte[i] = T1; |
| 592 |
return;
|
| 593 |
} |
| 594 |
} |
| 595 |
// Try finding an unlocked entry
|
| 596 |
for (i = 0; i < 64; i++) { |
| 597 |
if ((env->dtlb_tte[i] & 0x40) == 0) { |
| 598 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
| 599 |
env->dtlb_tte[i] = T1; |
| 600 |
return;
|
| 601 |
} |
| 602 |
} |
| 603 |
// error state?
|
| 604 |
return;
|
| 605 |
} |
| 606 |
case 0x5d: // D-MMU data access |
| 607 |
{
|
| 608 |
unsigned int i = (T0 >> 3) & 0x3f; |
| 609 |
|
| 610 |
env->dtlb_tag[i] = env->dmmuregs[6];
|
| 611 |
env->dtlb_tte[i] = T1; |
| 612 |
return;
|
| 613 |
} |
| 614 |
case 0x5f: // D-MMU demap |
| 615 |
return;
|
| 616 |
case 0x51: // I-MMU 8k TSB pointer, RO |
| 617 |
case 0x52: // I-MMU 64k TSB pointer, RO |
| 618 |
case 0x56: // I-MMU tag read, RO |
| 619 |
case 0x59: // D-MMU 8k TSB pointer, RO |
| 620 |
case 0x5a: // D-MMU 64k TSB pointer, RO |
| 621 |
case 0x5b: // D-MMU data pointer, RO |
| 622 |
case 0x5e: // D-MMU tag read, RO |
| 623 |
default:
|
| 624 |
return;
|
| 625 |
} |
| 626 |
} |
| 627 |
|
| 628 |
#endif
|
| 629 |
|
| 630 |
#ifndef TARGET_SPARC64
|
| 631 |
void helper_rett()
|
| 632 |
{
|
| 633 |
unsigned int cwp; |
| 634 |
|
| 635 |
env->psret = 1;
|
| 636 |
cwp = (env->cwp + 1) & (NWINDOWS - 1); |
| 637 |
if (env->wim & (1 << cwp)) { |
| 638 |
raise_exception(TT_WIN_UNF); |
| 639 |
} |
| 640 |
set_cwp(cwp); |
| 641 |
env->psrs = env->psrps; |
| 642 |
} |
| 643 |
#endif
|
| 644 |
|
| 645 |
void helper_ldfsr(void) |
| 646 |
{
|
| 647 |
int rnd_mode;
|
| 648 |
switch (env->fsr & FSR_RD_MASK) {
|
| 649 |
case FSR_RD_NEAREST:
|
| 650 |
rnd_mode = float_round_nearest_even; |
| 651 |
break;
|
| 652 |
default:
|
| 653 |
case FSR_RD_ZERO:
|
| 654 |
rnd_mode = float_round_to_zero; |
| 655 |
break;
|
| 656 |
case FSR_RD_POS:
|
| 657 |
rnd_mode = float_round_up; |
| 658 |
break;
|
| 659 |
case FSR_RD_NEG:
|
| 660 |
rnd_mode = float_round_down; |
| 661 |
break;
|
| 662 |
} |
| 663 |
set_float_rounding_mode(rnd_mode, &env->fp_status); |
| 664 |
} |
| 665 |
|
| 666 |
void cpu_get_fp64(uint64_t *pmant, uint16_t *pexp, double f) |
| 667 |
{
|
| 668 |
int exptemp;
|
| 669 |
|
| 670 |
*pmant = ldexp(frexp(f, &exptemp), 53);
|
| 671 |
*pexp = exptemp; |
| 672 |
} |
| 673 |
|
| 674 |
double cpu_put_fp64(uint64_t mant, uint16_t exp)
|
| 675 |
{
|
| 676 |
return ldexp((double) mant, exp - 53); |
| 677 |
} |
| 678 |
|
| 679 |
void helper_debug()
|
| 680 |
{
|
| 681 |
env->exception_index = EXCP_DEBUG; |
| 682 |
cpu_loop_exit(); |
| 683 |
} |
| 684 |
|
| 685 |
#ifndef TARGET_SPARC64
|
| 686 |
void do_wrpsr()
|
| 687 |
{
|
| 688 |
PUT_PSR(env, T0); |
| 689 |
} |
| 690 |
|
| 691 |
void do_rdpsr()
|
| 692 |
{
|
| 693 |
T0 = GET_PSR(env); |
| 694 |
} |
| 695 |
|
| 696 |
#else
|
| 697 |
|
| 698 |
void do_popc()
|
| 699 |
{
|
| 700 |
T0 = (T1 & 0x5555555555555555ULL) + ((T1 >> 1) & 0x5555555555555555ULL); |
| 701 |
T0 = (T0 & 0x3333333333333333ULL) + ((T0 >> 2) & 0x3333333333333333ULL); |
| 702 |
T0 = (T0 & 0x0f0f0f0f0f0f0f0fULL) + ((T0 >> 4) & 0x0f0f0f0f0f0f0f0fULL); |
| 703 |
T0 = (T0 & 0x00ff00ff00ff00ffULL) + ((T0 >> 8) & 0x00ff00ff00ff00ffULL); |
| 704 |
T0 = (T0 & 0x0000ffff0000ffffULL) + ((T0 >> 16) & 0x0000ffff0000ffffULL); |
| 705 |
T0 = (T0 & 0x00000000ffffffffULL) + ((T0 >> 32) & 0x00000000ffffffffULL); |
| 706 |
} |
| 707 |
#endif
|