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1
/*
2
   SPARC translation
3

4
   Copyright (C) 2003 Thomas M. Ogrisegg <tom@fnord.at>
5
   Copyright (C) 2003-2005 Fabrice Bellard
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7
   This library is free software; you can redistribute it and/or
8
   modify it under the terms of the GNU Lesser General Public
9
   License as published by the Free Software Foundation; either
10
   version 2 of the License, or (at your option) any later version.
11

12
   This library is distributed in the hope that it will be useful,
13
   but WITHOUT ANY WARRANTY; without even the implied warranty of
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   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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   Lesser General Public License for more details.
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   You should have received a copy of the GNU Lesser General Public
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   License along with this library; if not, write to the Free Software
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   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
20
 */
21

    
22
/*
23
   TODO-list:
24

25
   Rest of V9 instructions, VIS instructions
26
   NPC/PC static optimisations (use JUMP_TB when possible)
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   Optimize synthetic instructions
28
   Optional alignment check
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   128-bit float
30
   Tagged add/sub
31
*/
32

    
33
#include <stdarg.h>
34
#include <stdlib.h>
35
#include <stdio.h>
36
#include <string.h>
37
#include <inttypes.h>
38

    
39
#include "cpu.h"
40
#include "exec-all.h"
41
#include "disas.h"
42

    
43
#define DEBUG_DISAS
44

    
45
#define DYNAMIC_PC  1 /* dynamic pc value */
46
#define JUMP_PC     2 /* dynamic pc value which takes only two values
47
                         according to jump_pc[T2] */
48

    
49
typedef struct DisasContext {
50
    target_ulong pc;        /* current Program Counter: integer or DYNAMIC_PC */
51
    target_ulong npc;        /* next PC: integer or DYNAMIC_PC or JUMP_PC */
52
    target_ulong jump_pc[2]; /* used when JUMP_PC pc value is used */
53
    int is_br;
54
    int mem_idx;
55
    struct TranslationBlock *tb;
56
} DisasContext;
57

    
58
static uint16_t *gen_opc_ptr;
59
static uint32_t *gen_opparam_ptr;
60
extern FILE *logfile;
61
extern int loglevel;
62

    
63
enum {
64
#define DEF(s,n,copy_size) INDEX_op_ ## s,
65
#include "opc.h"
66
#undef DEF
67
    NB_OPS
68
};
69

    
70
#include "gen-op.h"
71

    
72
// This function uses non-native bit order
73
#define GET_FIELD(X, FROM, TO) \
74
  ((X) >> (31 - (TO)) & ((1 << ((TO) - (FROM) + 1)) - 1))
75

    
76
// This function uses the order in the manuals, i.e. bit 0 is 2^0
77
#define GET_FIELD_SP(X, FROM, TO) \
78
    GET_FIELD(X, 31 - (TO), 31 - (FROM))
79

    
80
#define GET_FIELDs(x,a,b) sign_extend (GET_FIELD(x,a,b), (b) - (a) + 1)
81
#define GET_FIELD_SPs(x,a,b) sign_extend (GET_FIELD_SP(x,a,b), 32 - ((b) - (a) + 1))
82

    
83
#ifdef TARGET_SPARC64
84
#define DFPREG(r) (((r & 1) << 6) | (r & 0x1e))
85
#else
86
#define DFPREG(r) (r)
87
#endif
88

    
89
static int sign_extend(int x, int len)
90
{
91
    len = 32 - len;
92
    return (x << len) >> len;
93
}
94

    
95
#define IS_IMM (insn & (1<<13))
96

    
97
static void disas_sparc_insn(DisasContext * dc);
98

    
99
static GenOpFunc *gen_op_movl_TN_reg[2][32] = {
100
    {
101
     gen_op_movl_g0_T0,
102
     gen_op_movl_g1_T0,
103
     gen_op_movl_g2_T0,
104
     gen_op_movl_g3_T0,
105
     gen_op_movl_g4_T0,
106
     gen_op_movl_g5_T0,
107
     gen_op_movl_g6_T0,
108
     gen_op_movl_g7_T0,
109
     gen_op_movl_o0_T0,
110
     gen_op_movl_o1_T0,
111
     gen_op_movl_o2_T0,
112
     gen_op_movl_o3_T0,
113
     gen_op_movl_o4_T0,
114
     gen_op_movl_o5_T0,
115
     gen_op_movl_o6_T0,
116
     gen_op_movl_o7_T0,
117
     gen_op_movl_l0_T0,
118
     gen_op_movl_l1_T0,
119
     gen_op_movl_l2_T0,
120
     gen_op_movl_l3_T0,
121
     gen_op_movl_l4_T0,
122
     gen_op_movl_l5_T0,
123
     gen_op_movl_l6_T0,
124
     gen_op_movl_l7_T0,
125
     gen_op_movl_i0_T0,
126
     gen_op_movl_i1_T0,
127
     gen_op_movl_i2_T0,
128
     gen_op_movl_i3_T0,
129
     gen_op_movl_i4_T0,
130
     gen_op_movl_i5_T0,
131
     gen_op_movl_i6_T0,
132
     gen_op_movl_i7_T0,
133
     },
134
    {
135
     gen_op_movl_g0_T1,
136
     gen_op_movl_g1_T1,
137
     gen_op_movl_g2_T1,
138
     gen_op_movl_g3_T1,
139
     gen_op_movl_g4_T1,
140
     gen_op_movl_g5_T1,
141
     gen_op_movl_g6_T1,
142
     gen_op_movl_g7_T1,
143
     gen_op_movl_o0_T1,
144
     gen_op_movl_o1_T1,
145
     gen_op_movl_o2_T1,
146
     gen_op_movl_o3_T1,
147
     gen_op_movl_o4_T1,
148
     gen_op_movl_o5_T1,
149
     gen_op_movl_o6_T1,
150
     gen_op_movl_o7_T1,
151
     gen_op_movl_l0_T1,
152
     gen_op_movl_l1_T1,
153
     gen_op_movl_l2_T1,
154
     gen_op_movl_l3_T1,
155
     gen_op_movl_l4_T1,
156
     gen_op_movl_l5_T1,
157
     gen_op_movl_l6_T1,
158
     gen_op_movl_l7_T1,
159
     gen_op_movl_i0_T1,
160
     gen_op_movl_i1_T1,
161
     gen_op_movl_i2_T1,
162
     gen_op_movl_i3_T1,
163
     gen_op_movl_i4_T1,
164
     gen_op_movl_i5_T1,
165
     gen_op_movl_i6_T1,
166
     gen_op_movl_i7_T1,
167
     }
168
};
169

    
170
static GenOpFunc *gen_op_movl_reg_TN[3][32] = {
171
    {
172
     gen_op_movl_T0_g0,
173
     gen_op_movl_T0_g1,
174
     gen_op_movl_T0_g2,
175
     gen_op_movl_T0_g3,
176
     gen_op_movl_T0_g4,
177
     gen_op_movl_T0_g5,
178
     gen_op_movl_T0_g6,
179
     gen_op_movl_T0_g7,
180
     gen_op_movl_T0_o0,
181
     gen_op_movl_T0_o1,
182
     gen_op_movl_T0_o2,
183
     gen_op_movl_T0_o3,
184
     gen_op_movl_T0_o4,
185
     gen_op_movl_T0_o5,
186
     gen_op_movl_T0_o6,
187
     gen_op_movl_T0_o7,
188
     gen_op_movl_T0_l0,
189
     gen_op_movl_T0_l1,
190
     gen_op_movl_T0_l2,
191
     gen_op_movl_T0_l3,
192
     gen_op_movl_T0_l4,
193
     gen_op_movl_T0_l5,
194
     gen_op_movl_T0_l6,
195
     gen_op_movl_T0_l7,
196
     gen_op_movl_T0_i0,
197
     gen_op_movl_T0_i1,
198
     gen_op_movl_T0_i2,
199
     gen_op_movl_T0_i3,
200
     gen_op_movl_T0_i4,
201
     gen_op_movl_T0_i5,
202
     gen_op_movl_T0_i6,
203
     gen_op_movl_T0_i7,
204
     },
205
    {
206
     gen_op_movl_T1_g0,
207
     gen_op_movl_T1_g1,
208
     gen_op_movl_T1_g2,
209
     gen_op_movl_T1_g3,
210
     gen_op_movl_T1_g4,
211
     gen_op_movl_T1_g5,
212
     gen_op_movl_T1_g6,
213
     gen_op_movl_T1_g7,
214
     gen_op_movl_T1_o0,
215
     gen_op_movl_T1_o1,
216
     gen_op_movl_T1_o2,
217
     gen_op_movl_T1_o3,
218
     gen_op_movl_T1_o4,
219
     gen_op_movl_T1_o5,
220
     gen_op_movl_T1_o6,
221
     gen_op_movl_T1_o7,
222
     gen_op_movl_T1_l0,
223
     gen_op_movl_T1_l1,
224
     gen_op_movl_T1_l2,
225
     gen_op_movl_T1_l3,
226
     gen_op_movl_T1_l4,
227
     gen_op_movl_T1_l5,
228
     gen_op_movl_T1_l6,
229
     gen_op_movl_T1_l7,
230
     gen_op_movl_T1_i0,
231
     gen_op_movl_T1_i1,
232
     gen_op_movl_T1_i2,
233
     gen_op_movl_T1_i3,
234
     gen_op_movl_T1_i4,
235
     gen_op_movl_T1_i5,
236
     gen_op_movl_T1_i6,
237
     gen_op_movl_T1_i7,
238
     },
239
    {
240
     gen_op_movl_T2_g0,
241
     gen_op_movl_T2_g1,
242
     gen_op_movl_T2_g2,
243
     gen_op_movl_T2_g3,
244
     gen_op_movl_T2_g4,
245
     gen_op_movl_T2_g5,
246
     gen_op_movl_T2_g6,
247
     gen_op_movl_T2_g7,
248
     gen_op_movl_T2_o0,
249
     gen_op_movl_T2_o1,
250
     gen_op_movl_T2_o2,
251
     gen_op_movl_T2_o3,
252
     gen_op_movl_T2_o4,
253
     gen_op_movl_T2_o5,
254
     gen_op_movl_T2_o6,
255
     gen_op_movl_T2_o7,
256
     gen_op_movl_T2_l0,
257
     gen_op_movl_T2_l1,
258
     gen_op_movl_T2_l2,
259
     gen_op_movl_T2_l3,
260
     gen_op_movl_T2_l4,
261
     gen_op_movl_T2_l5,
262
     gen_op_movl_T2_l6,
263
     gen_op_movl_T2_l7,
264
     gen_op_movl_T2_i0,
265
     gen_op_movl_T2_i1,
266
     gen_op_movl_T2_i2,
267
     gen_op_movl_T2_i3,
268
     gen_op_movl_T2_i4,
269
     gen_op_movl_T2_i5,
270
     gen_op_movl_T2_i6,
271
     gen_op_movl_T2_i7,
272
     }
273
};
274

    
275
static GenOpFunc1 *gen_op_movl_TN_im[3] = {
276
    gen_op_movl_T0_im,
277
    gen_op_movl_T1_im,
278
    gen_op_movl_T2_im
279
};
280

    
281
// Sign extending version
282
static GenOpFunc1 * const gen_op_movl_TN_sim[3] = {
283
    gen_op_movl_T0_sim,
284
    gen_op_movl_T1_sim,
285
    gen_op_movl_T2_sim
286
};
287

    
288
#ifdef TARGET_SPARC64
289
#define GEN32(func, NAME) \
290
static GenOpFunc *NAME ## _table [64] = {                                     \
291
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
292
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
293
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
294
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
295
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
296
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
297
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
298
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
299
NAME ## 32, 0, NAME ## 34, 0, NAME ## 36, 0, NAME ## 38, 0,                   \
300
NAME ## 40, 0, NAME ## 42, 0, NAME ## 44, 0, NAME ## 46, 0,                   \
301
NAME ## 48, 0, NAME ## 50, 0, NAME ## 52, 0, NAME ## 54, 0,                   \
302
NAME ## 56, 0, NAME ## 58, 0, NAME ## 60, 0, NAME ## 62, 0,                   \
303
};                                                                            \
304
static inline void func(int n)                                                \
305
{                                                                             \
306
    NAME ## _table[n]();                                                      \
307
}
308
#else
309
#define GEN32(func, NAME) \
310
static GenOpFunc *NAME ## _table [32] = {                                     \
311
NAME ## 0, NAME ## 1, NAME ## 2, NAME ## 3,                                   \
312
NAME ## 4, NAME ## 5, NAME ## 6, NAME ## 7,                                   \
313
NAME ## 8, NAME ## 9, NAME ## 10, NAME ## 11,                                 \
314
NAME ## 12, NAME ## 13, NAME ## 14, NAME ## 15,                               \
315
NAME ## 16, NAME ## 17, NAME ## 18, NAME ## 19,                               \
316
NAME ## 20, NAME ## 21, NAME ## 22, NAME ## 23,                               \
317
NAME ## 24, NAME ## 25, NAME ## 26, NAME ## 27,                               \
318
NAME ## 28, NAME ## 29, NAME ## 30, NAME ## 31,                               \
319
};                                                                            \
320
static inline void func(int n)                                                \
321
{                                                                             \
322
    NAME ## _table[n]();                                                      \
323
}
324
#endif
325

    
326
/* floating point registers moves */
327
GEN32(gen_op_load_fpr_FT0, gen_op_load_fpr_FT0_fprf);
328
GEN32(gen_op_load_fpr_FT1, gen_op_load_fpr_FT1_fprf);
329
GEN32(gen_op_store_FT0_fpr, gen_op_store_FT0_fpr_fprf);
330
GEN32(gen_op_store_FT1_fpr, gen_op_store_FT1_fpr_fprf);
331

    
332
GEN32(gen_op_load_fpr_DT0, gen_op_load_fpr_DT0_fprf);
333
GEN32(gen_op_load_fpr_DT1, gen_op_load_fpr_DT1_fprf);
334
GEN32(gen_op_store_DT0_fpr, gen_op_store_DT0_fpr_fprf);
335
GEN32(gen_op_store_DT1_fpr, gen_op_store_DT1_fpr_fprf);
336

    
337
#ifdef TARGET_SPARC64
338
// 'a' versions allowed to user depending on asi
339
#if defined(CONFIG_USER_ONLY)
340
#define supervisor(dc) 0
341
#define gen_op_ldst(name)        gen_op_##name##_raw()
342
#define OP_LD_TABLE(width)                                                \
343
    static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
344
    {                                                                        \
345
        int asi, offset;                                                \
346
                                                                        \
347
        if (IS_IMM) {                                                        \
348
            offset = GET_FIELD(insn, 25, 31);                                \
349
            if (is_ld)                                                        \
350
                gen_op_ld_asi_reg(offset, size, sign);                        \
351
            else                                                        \
352
                gen_op_st_asi_reg(offset, size, sign);                        \
353
            return;                                                        \
354
        }                                                                \
355
        asi = GET_FIELD(insn, 19, 26);                                        \
356
        switch (asi) {                                                        \
357
        case 0x80: /* Primary address space */                                \
358
            gen_op_##width##_raw();                                        \
359
            break;                                                        \
360
        default:                                                        \
361
            break;                                                        \
362
        }                                                                \
363
    }
364

    
365
#else
366
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
367
#define OP_LD_TABLE(width)                                                \
368
    static GenOpFunc *gen_op_##width[] = {                                \
369
        &gen_op_##width##_user,                                                \
370
        &gen_op_##width##_kernel,                                        \
371
    };                                                                        \
372
                                                                        \
373
    static void gen_op_##width##a(int insn, int is_ld, int size, int sign) \
374
    {                                                                        \
375
        int asi, offset;                                                \
376
                                                                        \
377
        if (IS_IMM) {                                                        \
378
            offset = GET_FIELD(insn, 25, 31);                                \
379
            if (is_ld)                                                        \
380
                gen_op_ld_asi_reg(offset, size, sign);                        \
381
            else                                                        \
382
                gen_op_st_asi_reg(offset, size, sign);                        \
383
            return;                                                        \
384
        }                                                                \
385
        asi = GET_FIELD(insn, 19, 26);                                        \
386
        if (is_ld)                                                        \
387
            gen_op_ld_asi(asi, size, sign);                                \
388
        else                                                                \
389
            gen_op_st_asi(asi, size, sign);                                \
390
    }
391

    
392
#define supervisor(dc) (dc->mem_idx == 1)
393
#endif
394
#else
395
#if defined(CONFIG_USER_ONLY)
396
#define gen_op_ldst(name)        gen_op_##name##_raw()
397
#define OP_LD_TABLE(width)
398
#define supervisor(dc) 0
399
#else
400
#define gen_op_ldst(name)        (*gen_op_##name[dc->mem_idx])()
401
#define OP_LD_TABLE(width)                                                      \
402
static GenOpFunc *gen_op_##width[] = {                                        \
403
    &gen_op_##width##_user,                                                   \
404
    &gen_op_##width##_kernel,                                                 \
405
};                                                                            \
406
                                                                              \
407
static void gen_op_##width##a(int insn, int is_ld, int size, int sign)        \
408
{                                                                             \
409
    int asi;                                                                  \
410
                                                                              \
411
    asi = GET_FIELD(insn, 19, 26);                                            \
412
    switch (asi) {                                                            \
413
        case 10: /* User data access */                                       \
414
            gen_op_##width##_user();                                          \
415
            break;                                                            \
416
        case 11: /* Supervisor data access */                                 \
417
            gen_op_##width##_kernel();                                        \
418
            break;                                                            \
419
        case 0x20 ... 0x2f: /* MMU passthrough */                              \
420
            if (is_ld)                                                        \
421
                gen_op_ld_asi(asi, size, sign);                                      \
422
            else                                                              \
423
                gen_op_st_asi(asi, size, sign);                                      \
424
            break;                                                            \
425
        default:                                                              \
426
            if (is_ld)                                                        \
427
                gen_op_ld_asi(asi, size, sign);                                      \
428
            else                                                              \
429
                gen_op_st_asi(asi, size, sign);                                      \
430
            break;                                                            \
431
    }                                                                         \
432
}
433

    
434
#define supervisor(dc) (dc->mem_idx == 1)
435
#endif
436
#endif
437

    
438
OP_LD_TABLE(ld);
439
OP_LD_TABLE(st);
440
OP_LD_TABLE(ldub);
441
OP_LD_TABLE(lduh);
442
OP_LD_TABLE(ldsb);
443
OP_LD_TABLE(ldsh);
444
OP_LD_TABLE(stb);
445
OP_LD_TABLE(sth);
446
OP_LD_TABLE(std);
447
OP_LD_TABLE(ldstub);
448
OP_LD_TABLE(swap);
449
OP_LD_TABLE(ldd);
450
OP_LD_TABLE(stf);
451
OP_LD_TABLE(stdf);
452
OP_LD_TABLE(ldf);
453
OP_LD_TABLE(lddf);
454

    
455
#ifdef TARGET_SPARC64
456
OP_LD_TABLE(ldsw);
457
OP_LD_TABLE(ldx);
458
OP_LD_TABLE(stx);
459
OP_LD_TABLE(cas);
460
OP_LD_TABLE(casx);
461
#endif
462

    
463
static inline void gen_movl_imm_TN(int reg, uint32_t imm)
464
{
465
    gen_op_movl_TN_im[reg] (imm);
466
}
467

    
468
static inline void gen_movl_imm_T1(uint32_t val)
469
{
470
    gen_movl_imm_TN(1, val);
471
}
472

    
473
static inline void gen_movl_imm_T0(uint32_t val)
474
{
475
    gen_movl_imm_TN(0, val);
476
}
477

    
478
static inline void gen_movl_simm_TN(int reg, int32_t imm)
479
{
480
    gen_op_movl_TN_sim[reg](imm);
481
}
482

    
483
static inline void gen_movl_simm_T1(int32_t val)
484
{
485
    gen_movl_simm_TN(1, val);
486
}
487

    
488
static inline void gen_movl_simm_T0(int32_t val)
489
{
490
    gen_movl_simm_TN(0, val);
491
}
492

    
493
static inline void gen_movl_reg_TN(int reg, int t)
494
{
495
    if (reg)
496
        gen_op_movl_reg_TN[t][reg] ();
497
    else
498
        gen_movl_imm_TN(t, 0);
499
}
500

    
501
static inline void gen_movl_reg_T0(int reg)
502
{
503
    gen_movl_reg_TN(reg, 0);
504
}
505

    
506
static inline void gen_movl_reg_T1(int reg)
507
{
508
    gen_movl_reg_TN(reg, 1);
509
}
510

    
511
static inline void gen_movl_reg_T2(int reg)
512
{
513
    gen_movl_reg_TN(reg, 2);
514
}
515

    
516
static inline void gen_movl_TN_reg(int reg, int t)
517
{
518
    if (reg)
519
        gen_op_movl_TN_reg[t][reg] ();
520
}
521

    
522
static inline void gen_movl_T0_reg(int reg)
523
{
524
    gen_movl_TN_reg(reg, 0);
525
}
526

    
527
static inline void gen_movl_T1_reg(int reg)
528
{
529
    gen_movl_TN_reg(reg, 1);
530
}
531

    
532
/* call this function before using T2 as it may have been set for a jump */
533
static inline void flush_T2(DisasContext * dc)
534
{
535
    if (dc->npc == JUMP_PC) {
536
        gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
537
        dc->npc = DYNAMIC_PC;
538
    }
539
}
540

    
541
static inline void gen_jmp_im(target_ulong pc)
542
{
543
#ifdef TARGET_SPARC64
544
    if (pc == (uint32_t)pc) {
545
        gen_op_jmp_im(pc);
546
    } else {
547
        gen_op_jmp_im64(pc >> 32, pc);
548
    }
549
#else
550
    gen_op_jmp_im(pc);
551
#endif
552
}
553

    
554
static inline void gen_movl_npc_im(target_ulong npc)
555
{
556
#ifdef TARGET_SPARC64
557
    if (npc == (uint32_t)npc) {
558
        gen_op_movl_npc_im(npc);
559
    } else {
560
        gen_op_movq_npc_im64(npc >> 32, npc);
561
    }
562
#else
563
    gen_op_movl_npc_im(npc);
564
#endif
565
}
566

    
567
static inline void save_npc(DisasContext * dc)
568
{
569
    if (dc->npc == JUMP_PC) {
570
        gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
571
        dc->npc = DYNAMIC_PC;
572
    } else if (dc->npc != DYNAMIC_PC) {
573
        gen_movl_npc_im(dc->npc);
574
    }
575
}
576

    
577
static inline void save_state(DisasContext * dc)
578
{
579
    gen_jmp_im(dc->pc);
580
    save_npc(dc);
581
}
582

    
583
static inline void gen_mov_pc_npc(DisasContext * dc)
584
{
585
    if (dc->npc == JUMP_PC) {
586
        gen_op_generic_branch(dc->jump_pc[0], dc->jump_pc[1]);
587
        gen_op_mov_pc_npc();
588
        dc->pc = DYNAMIC_PC;
589
    } else if (dc->npc == DYNAMIC_PC) {
590
        gen_op_mov_pc_npc();
591
        dc->pc = DYNAMIC_PC;
592
    } else {
593
        dc->pc = dc->npc;
594
    }
595
}
596

    
597
static GenOpFunc * const gen_cond[2][16] = {
598
    {
599
        gen_op_eval_ba,
600
        gen_op_eval_be,
601
        gen_op_eval_ble,
602
        gen_op_eval_bl,
603
        gen_op_eval_bleu,
604
        gen_op_eval_bcs,
605
        gen_op_eval_bneg,
606
        gen_op_eval_bvs,
607
        gen_op_eval_bn,
608
        gen_op_eval_bne,
609
        gen_op_eval_bg,
610
        gen_op_eval_bge,
611
        gen_op_eval_bgu,
612
        gen_op_eval_bcc,
613
        gen_op_eval_bpos,
614
        gen_op_eval_bvc,
615
    },
616
    {
617
#ifdef TARGET_SPARC64
618
        gen_op_eval_ba,
619
        gen_op_eval_xbe,
620
        gen_op_eval_xble,
621
        gen_op_eval_xbl,
622
        gen_op_eval_xbleu,
623
        gen_op_eval_xbcs,
624
        gen_op_eval_xbneg,
625
        gen_op_eval_xbvs,
626
        gen_op_eval_bn,
627
        gen_op_eval_xbne,
628
        gen_op_eval_xbg,
629
        gen_op_eval_xbge,
630
        gen_op_eval_xbgu,
631
        gen_op_eval_xbcc,
632
        gen_op_eval_xbpos,
633
        gen_op_eval_xbvc,
634
#endif
635
    },
636
};
637

    
638
static GenOpFunc * const gen_fcond[4][16] = {
639
    {
640
        gen_op_eval_ba,
641
        gen_op_eval_fbne,
642
        gen_op_eval_fblg,
643
        gen_op_eval_fbul,
644
        gen_op_eval_fbl,
645
        gen_op_eval_fbug,
646
        gen_op_eval_fbg,
647
        gen_op_eval_fbu,
648
        gen_op_eval_bn,
649
        gen_op_eval_fbe,
650
        gen_op_eval_fbue,
651
        gen_op_eval_fbge,
652
        gen_op_eval_fbuge,
653
        gen_op_eval_fble,
654
        gen_op_eval_fbule,
655
        gen_op_eval_fbo,
656
    },
657
#ifdef TARGET_SPARC64
658
    {
659
        gen_op_eval_ba,
660
        gen_op_eval_fbne_fcc1,
661
        gen_op_eval_fblg_fcc1,
662
        gen_op_eval_fbul_fcc1,
663
        gen_op_eval_fbl_fcc1,
664
        gen_op_eval_fbug_fcc1,
665
        gen_op_eval_fbg_fcc1,
666
        gen_op_eval_fbu_fcc1,
667
        gen_op_eval_bn,
668
        gen_op_eval_fbe_fcc1,
669
        gen_op_eval_fbue_fcc1,
670
        gen_op_eval_fbge_fcc1,
671
        gen_op_eval_fbuge_fcc1,
672
        gen_op_eval_fble_fcc1,
673
        gen_op_eval_fbule_fcc1,
674
        gen_op_eval_fbo_fcc1,
675
    },
676
    {
677
        gen_op_eval_ba,
678
        gen_op_eval_fbne_fcc2,
679
        gen_op_eval_fblg_fcc2,
680
        gen_op_eval_fbul_fcc2,
681
        gen_op_eval_fbl_fcc2,
682
        gen_op_eval_fbug_fcc2,
683
        gen_op_eval_fbg_fcc2,
684
        gen_op_eval_fbu_fcc2,
685
        gen_op_eval_bn,
686
        gen_op_eval_fbe_fcc2,
687
        gen_op_eval_fbue_fcc2,
688
        gen_op_eval_fbge_fcc2,
689
        gen_op_eval_fbuge_fcc2,
690
        gen_op_eval_fble_fcc2,
691
        gen_op_eval_fbule_fcc2,
692
        gen_op_eval_fbo_fcc2,
693
    },
694
    {
695
        gen_op_eval_ba,
696
        gen_op_eval_fbne_fcc3,
697
        gen_op_eval_fblg_fcc3,
698
        gen_op_eval_fbul_fcc3,
699
        gen_op_eval_fbl_fcc3,
700
        gen_op_eval_fbug_fcc3,
701
        gen_op_eval_fbg_fcc3,
702
        gen_op_eval_fbu_fcc3,
703
        gen_op_eval_bn,
704
        gen_op_eval_fbe_fcc3,
705
        gen_op_eval_fbue_fcc3,
706
        gen_op_eval_fbge_fcc3,
707
        gen_op_eval_fbuge_fcc3,
708
        gen_op_eval_fble_fcc3,
709
        gen_op_eval_fbule_fcc3,
710
        gen_op_eval_fbo_fcc3,
711
    },
712
#else
713
    {}, {}, {},
714
#endif
715
};
716

    
717
#ifdef TARGET_SPARC64
718
static void gen_cond_reg(int cond)
719
{
720
        switch (cond) {
721
        case 0x1:
722
            gen_op_eval_brz();
723
            break;
724
        case 0x2:
725
            gen_op_eval_brlez();
726
            break;
727
        case 0x3:
728
            gen_op_eval_brlz();
729
            break;
730
        case 0x5:
731
            gen_op_eval_brnz();
732
            break;
733
        case 0x6:
734
            gen_op_eval_brgz();
735
            break;
736
        default:
737
        case 0x7:
738
            gen_op_eval_brgez();
739
            break;
740
        }
741
}
742
#endif
743

    
744
/* XXX: potentially incorrect if dynamic npc */
745
static void do_branch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
746
{
747
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
748
    target_ulong target = dc->pc + offset;
749
        
750
    if (cond == 0x0) {
751
        /* unconditional not taken */
752
        if (a) {
753
            dc->pc = dc->npc + 4; 
754
            dc->npc = dc->pc + 4;
755
        } else {
756
            dc->pc = dc->npc;
757
            dc->npc = dc->pc + 4;
758
        }
759
    } else if (cond == 0x8) {
760
        /* unconditional taken */
761
        if (a) {
762
            dc->pc = target;
763
            dc->npc = dc->pc + 4;
764
        } else {
765
            dc->pc = dc->npc;
766
            dc->npc = target;
767
        }
768
    } else {
769
        flush_T2(dc);
770
        gen_cond[cc][cond]();
771
        if (a) {
772
            gen_op_branch_a((long)dc->tb, target, dc->npc);
773
            dc->is_br = 1;
774
        } else {
775
            dc->pc = dc->npc;
776
            dc->jump_pc[0] = target;
777
            dc->jump_pc[1] = dc->npc + 4;
778
            dc->npc = JUMP_PC;
779
        }
780
    }
781
}
782

    
783
/* XXX: potentially incorrect if dynamic npc */
784
static void do_fbranch(DisasContext * dc, int32_t offset, uint32_t insn, int cc)
785
{
786
    unsigned int cond = GET_FIELD(insn, 3, 6), a = (insn & (1 << 29));
787
    target_ulong target = dc->pc + offset;
788

    
789
    if (cond == 0x0) {
790
        /* unconditional not taken */
791
        if (a) {
792
            dc->pc = dc->npc + 4;
793
            dc->npc = dc->pc + 4;
794
        } else {
795
            dc->pc = dc->npc;
796
            dc->npc = dc->pc + 4;
797
        }
798
    } else if (cond == 0x8) {
799
        /* unconditional taken */
800
        if (a) {
801
            dc->pc = target;
802
            dc->npc = dc->pc + 4;
803
        } else {
804
            dc->pc = dc->npc;
805
            dc->npc = target;
806
        }
807
    } else {
808
        flush_T2(dc);
809
        gen_fcond[cc][cond]();
810
        if (a) {
811
            gen_op_branch_a((long)dc->tb, target, dc->npc);
812
            dc->is_br = 1;
813
        } else {
814
            dc->pc = dc->npc;
815
            dc->jump_pc[0] = target;
816
            dc->jump_pc[1] = dc->npc + 4;
817
            dc->npc = JUMP_PC;
818
        }
819
    }
820
}
821

    
822
#ifdef TARGET_SPARC64
823
/* XXX: potentially incorrect if dynamic npc */
824
static void do_branch_reg(DisasContext * dc, int32_t offset, uint32_t insn)
825
{
826
    unsigned int cond = GET_FIELD_SP(insn, 25, 27), a = (insn & (1 << 29));
827
    target_ulong target = dc->pc + offset;
828

    
829
    flush_T2(dc);
830
    gen_cond_reg(cond);
831
    if (a) {
832
        gen_op_branch_a((long)dc->tb, target, dc->npc);
833
        dc->is_br = 1;
834
    } else {
835
        dc->pc = dc->npc;
836
        dc->jump_pc[0] = target;
837
        dc->jump_pc[1] = dc->npc + 4;
838
        dc->npc = JUMP_PC;
839
    }
840
}
841

    
842
static GenOpFunc * const gen_fcmps[4] = {
843
    gen_op_fcmps,
844
    gen_op_fcmps_fcc1,
845
    gen_op_fcmps_fcc2,
846
    gen_op_fcmps_fcc3,
847
};
848

    
849
static GenOpFunc * const gen_fcmpd[4] = {
850
    gen_op_fcmpd,
851
    gen_op_fcmpd_fcc1,
852
    gen_op_fcmpd_fcc2,
853
    gen_op_fcmpd_fcc3,
854
};
855
#endif
856

    
857
/* before an instruction, dc->pc must be static */
858
static void disas_sparc_insn(DisasContext * dc)
859
{
860
    unsigned int insn, opc, rs1, rs2, rd;
861

    
862
    insn = ldl_code(dc->pc);
863
    opc = GET_FIELD(insn, 0, 1);
864

    
865
    rd = GET_FIELD(insn, 2, 6);
866
    switch (opc) {
867
    case 0:                        /* branches/sethi */
868
        {
869
            unsigned int xop = GET_FIELD(insn, 7, 9);
870
            int32_t target;
871
            switch (xop) {
872
#ifdef TARGET_SPARC64
873
            case 0x1:                /* V9 BPcc */
874
                {
875
                    int cc;
876

    
877
                    target = GET_FIELD_SP(insn, 0, 18);
878
                    target <<= 2;
879
                    target = sign_extend(target, 18);
880
                    cc = GET_FIELD_SP(insn, 20, 21);
881
                    if (cc == 0)
882
                        do_branch(dc, target, insn, 0);
883
                    else if (cc == 2)
884
                        do_branch(dc, target, insn, 1);
885
                    else
886
                        goto illegal_insn;
887
                    goto jmp_insn;
888
                }
889
            case 0x3:                /* V9 BPr */
890
                {
891
                    target = GET_FIELD_SP(insn, 0, 13) | 
892
                        (GET_FIELD_SP(insn, 20, 21) >> 7);
893
                    target <<= 2;
894
                    target = sign_extend(target, 16);
895
                    rs1 = GET_FIELD(insn, 13, 17);
896
                    gen_movl_T0_reg(rs1);
897
                    do_branch_reg(dc, target, insn);
898
                    goto jmp_insn;
899
                }
900
            case 0x5:                /* V9 FBPcc */
901
                {
902
                    int cc = GET_FIELD_SP(insn, 20, 21);
903
#if !defined(CONFIG_USER_ONLY)
904
                    gen_op_trap_ifnofpu();
905
#endif
906
                    target = GET_FIELD_SP(insn, 0, 18);
907
                    target <<= 2;
908
                    target = sign_extend(target, 19);
909
                    do_fbranch(dc, target, insn, cc);
910
                    goto jmp_insn;
911
                }
912
#endif
913
            case 0x2:                /* BN+x */
914
                {
915
                    target = GET_FIELD(insn, 10, 31);
916
                    target <<= 2;
917
                    target = sign_extend(target, 22);
918
                    do_branch(dc, target, insn, 0);
919
                    goto jmp_insn;
920
                }
921
            case 0x6:                /* FBN+x */
922
                {
923
#if !defined(CONFIG_USER_ONLY)
924
                    gen_op_trap_ifnofpu();
925
#endif
926
                    target = GET_FIELD(insn, 10, 31);
927
                    target <<= 2;
928
                    target = sign_extend(target, 22);
929
                    do_fbranch(dc, target, insn, 0);
930
                    goto jmp_insn;
931
                }
932
            case 0x4:                /* SETHI */
933
#define OPTIM
934
#if defined(OPTIM)
935
                if (rd) { // nop
936
#endif
937
                    uint32_t value = GET_FIELD(insn, 10, 31);
938
                    gen_movl_imm_T0(value << 10);
939
                    gen_movl_T0_reg(rd);
940
#if defined(OPTIM)
941
                }
942
#endif
943
                break;
944
            case 0x0:                /* UNIMPL */
945
            default:
946
                goto illegal_insn;
947
            }
948
            break;
949
        }
950
        break;
951
    case 1:
952
        /*CALL*/ {
953
            target_long target = GET_FIELDs(insn, 2, 31) << 2;
954

    
955
            gen_op_movl_T0_im(dc->pc);
956
            gen_movl_T0_reg(15);
957
            target += dc->pc;
958
            gen_mov_pc_npc(dc);
959
            dc->npc = target;
960
        }
961
        goto jmp_insn;
962
    case 2:                        /* FPU & Logical Operations */
963
        {
964
            unsigned int xop = GET_FIELD(insn, 7, 12);
965
            if (xop == 0x3a) {        /* generate trap */
966
                int cond;
967

    
968
                rs1 = GET_FIELD(insn, 13, 17);
969
                gen_movl_reg_T0(rs1);
970
                if (IS_IMM) {
971
                    rs2 = GET_FIELD(insn, 25, 31);
972
#if defined(OPTIM)
973
                    if (rs2 != 0) {
974
#endif
975
                        gen_movl_simm_T1(rs2);
976
                        gen_op_add_T1_T0();
977
#if defined(OPTIM)
978
                    }
979
#endif
980
                } else {
981
                    rs2 = GET_FIELD(insn, 27, 31);
982
#if defined(OPTIM)
983
                    if (rs2 != 0) {
984
#endif
985
                        gen_movl_reg_T1(rs2);
986
                        gen_op_add_T1_T0();
987
#if defined(OPTIM)
988
                    }
989
#endif
990
                }
991
                save_state(dc);
992
                cond = GET_FIELD(insn, 3, 6);
993
                if (cond == 0x8) {
994
                    gen_op_trap_T0();
995
                    dc->is_br = 1;
996
                    goto jmp_insn;
997
                } else if (cond != 0) {
998
#ifdef TARGET_SPARC64
999
                    /* V9 icc/xcc */
1000
                    int cc = GET_FIELD_SP(insn, 11, 12);
1001
                    if (cc == 0)
1002
                        gen_cond[0][cond]();
1003
                    else if (cc == 2)
1004
                        gen_cond[1][cond]();
1005
                    else
1006
                        goto illegal_insn;
1007
#else
1008
                    gen_cond[0][cond]();
1009
#endif
1010
                    gen_op_trapcc_T0();
1011
                }
1012
            } else if (xop == 0x28) {
1013
                rs1 = GET_FIELD(insn, 13, 17);
1014
                switch(rs1) {
1015
                case 0: /* rdy */
1016
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, y));
1017
                    gen_movl_T0_reg(rd);
1018
                    break;
1019
                case 15: /* stbar / V9 membar */
1020
                    break; /* no effect? */
1021
#ifdef TARGET_SPARC64
1022
                case 0x2: /* V9 rdccr */
1023
                    gen_op_rdccr();
1024
                    gen_movl_T0_reg(rd);
1025
                    break;
1026
                case 0x3: /* V9 rdasi */
1027
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, asi));
1028
                    gen_movl_T0_reg(rd);
1029
                    break;
1030
                case 0x4: /* V9 rdtick */
1031
                    gen_op_rdtick();
1032
                    gen_movl_T0_reg(rd);
1033
                    break;
1034
                case 0x5: /* V9 rdpc */
1035
                    gen_op_movl_T0_im(dc->pc);
1036
                    gen_movl_T0_reg(rd);
1037
                    break;
1038
                case 0x6: /* V9 rdfprs */
1039
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, fprs));
1040
                    gen_movl_T0_reg(rd);
1041
                    break;
1042
#endif
1043
                default:
1044
                    goto illegal_insn;
1045
                }
1046
#if !defined(CONFIG_USER_ONLY)
1047
#ifndef TARGET_SPARC64
1048
            } else if (xop == 0x29) { /* rdpsr / V9 unimp */
1049
                if (!supervisor(dc))
1050
                    goto priv_insn;
1051
                gen_op_rdpsr();
1052
                gen_movl_T0_reg(rd);
1053
                break;
1054
#endif
1055
            } else if (xop == 0x2a) { /* rdwim / V9 rdpr */
1056
                if (!supervisor(dc))
1057
                    goto priv_insn;
1058
#ifdef TARGET_SPARC64
1059
                rs1 = GET_FIELD(insn, 13, 17);
1060
                switch (rs1) {
1061
                case 0: // tpc
1062
                    gen_op_rdtpc();
1063
                    break;
1064
                case 1: // tnpc
1065
                    gen_op_rdtnpc();
1066
                    break;
1067
                case 2: // tstate
1068
                    gen_op_rdtstate();
1069
                    break;
1070
                case 3: // tt
1071
                    gen_op_rdtt();
1072
                    break;
1073
                case 4: // tick
1074
                    gen_op_rdtick();
1075
                    break;
1076
                case 5: // tba
1077
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1078
                    break;
1079
                case 6: // pstate
1080
                    gen_op_rdpstate();
1081
                    break;
1082
                case 7: // tl
1083
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, tl));
1084
                    break;
1085
                case 8: // pil
1086
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, psrpil));
1087
                    break;
1088
                case 9: // cwp
1089
                    gen_op_rdcwp();
1090
                    break;
1091
                case 10: // cansave
1092
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cansave));
1093
                    break;
1094
                case 11: // canrestore
1095
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, canrestore));
1096
                    break;
1097
                case 12: // cleanwin
1098
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, cleanwin));
1099
                    break;
1100
                case 13: // otherwin
1101
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, otherwin));
1102
                    break;
1103
                case 14: // wstate
1104
                    gen_op_movl_T0_env(offsetof(CPUSPARCState, wstate));
1105
                    break;
1106
                case 31: // ver
1107
                    gen_op_movtl_T0_env(offsetof(CPUSPARCState, version));
1108
                    break;
1109
                case 15: // fq
1110
                default:
1111
                    goto illegal_insn;
1112
                }
1113
#else
1114
                gen_op_movl_T0_env(offsetof(CPUSPARCState, wim));
1115
#endif
1116
                gen_movl_T0_reg(rd);
1117
                break;
1118
            } else if (xop == 0x2b) { /* rdtbr / V9 flushw */
1119
#ifdef TARGET_SPARC64
1120
                gen_op_flushw();
1121
#else
1122
                if (!supervisor(dc))
1123
                    goto priv_insn;
1124
                gen_op_movtl_T0_env(offsetof(CPUSPARCState, tbr));
1125
                gen_movl_T0_reg(rd);
1126
#endif
1127
                break;
1128
#endif
1129
            } else if (xop == 0x34) {        /* FPU Operations */
1130
#if !defined(CONFIG_USER_ONLY)
1131
                gen_op_trap_ifnofpu();
1132
#endif
1133
                rs1 = GET_FIELD(insn, 13, 17);
1134
                rs2 = GET_FIELD(insn, 27, 31);
1135
                xop = GET_FIELD(insn, 18, 26);
1136
                switch (xop) {
1137
                    case 0x1: /* fmovs */
1138
                        gen_op_load_fpr_FT0(rs2);
1139
                        gen_op_store_FT0_fpr(rd);
1140
                        break;
1141
                    case 0x5: /* fnegs */
1142
                        gen_op_load_fpr_FT1(rs2);
1143
                        gen_op_fnegs();
1144
                        gen_op_store_FT0_fpr(rd);
1145
                        break;
1146
                    case 0x9: /* fabss */
1147
                        gen_op_load_fpr_FT1(rs2);
1148
                        gen_op_fabss();
1149
                        gen_op_store_FT0_fpr(rd);
1150
                        break;
1151
                    case 0x29: /* fsqrts */
1152
                        gen_op_load_fpr_FT1(rs2);
1153
                        gen_op_fsqrts();
1154
                        gen_op_store_FT0_fpr(rd);
1155
                        break;
1156
                    case 0x2a: /* fsqrtd */
1157
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1158
                        gen_op_fsqrtd();
1159
                        gen_op_store_DT0_fpr(DFPREG(rd));
1160
                        break;
1161
                    case 0x2b: /* fsqrtq */
1162
                        goto nfpu_insn;
1163
                    case 0x41:
1164
                        gen_op_load_fpr_FT0(rs1);
1165
                        gen_op_load_fpr_FT1(rs2);
1166
                        gen_op_fadds();
1167
                        gen_op_store_FT0_fpr(rd);
1168
                        break;
1169
                    case 0x42:
1170
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1171
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1172
                        gen_op_faddd();
1173
                        gen_op_store_DT0_fpr(DFPREG(rd));
1174
                        break;
1175
                    case 0x43: /* faddq */
1176
                        goto nfpu_insn;
1177
                    case 0x45:
1178
                        gen_op_load_fpr_FT0(rs1);
1179
                        gen_op_load_fpr_FT1(rs2);
1180
                        gen_op_fsubs();
1181
                        gen_op_store_FT0_fpr(rd);
1182
                        break;
1183
                    case 0x46:
1184
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1185
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1186
                        gen_op_fsubd();
1187
                        gen_op_store_DT0_fpr(DFPREG(rd));
1188
                        break;
1189
                    case 0x47: /* fsubq */
1190
                        goto nfpu_insn;
1191
                    case 0x49:
1192
                        gen_op_load_fpr_FT0(rs1);
1193
                        gen_op_load_fpr_FT1(rs2);
1194
                        gen_op_fmuls();
1195
                        gen_op_store_FT0_fpr(rd);
1196
                        break;
1197
                    case 0x4a:
1198
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1199
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1200
                        gen_op_fmuld();
1201
                        gen_op_store_DT0_fpr(rd);
1202
                        break;
1203
                    case 0x4b: /* fmulq */
1204
                        goto nfpu_insn;
1205
                    case 0x4d:
1206
                        gen_op_load_fpr_FT0(rs1);
1207
                        gen_op_load_fpr_FT1(rs2);
1208
                        gen_op_fdivs();
1209
                        gen_op_store_FT0_fpr(rd);
1210
                        break;
1211
                    case 0x4e:
1212
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1213
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1214
                        gen_op_fdivd();
1215
                        gen_op_store_DT0_fpr(DFPREG(rd));
1216
                        break;
1217
                    case 0x4f: /* fdivq */
1218
                        goto nfpu_insn;
1219
                    case 0x69:
1220
                        gen_op_load_fpr_FT0(rs1);
1221
                        gen_op_load_fpr_FT1(rs2);
1222
                        gen_op_fsmuld();
1223
                        gen_op_store_DT0_fpr(DFPREG(rd));
1224
                        break;
1225
                    case 0x6e: /* fdmulq */
1226
                        goto nfpu_insn;
1227
                    case 0xc4:
1228
                        gen_op_load_fpr_FT1(rs2);
1229
                        gen_op_fitos();
1230
                        gen_op_store_FT0_fpr(rd);
1231
                        break;
1232
                    case 0xc6:
1233
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1234
                        gen_op_fdtos();
1235
                        gen_op_store_FT0_fpr(rd);
1236
                        break;
1237
                    case 0xc7: /* fqtos */
1238
                        goto nfpu_insn;
1239
                    case 0xc8:
1240
                        gen_op_load_fpr_FT1(rs2);
1241
                        gen_op_fitod();
1242
                        gen_op_store_DT0_fpr(DFPREG(rd));
1243
                        break;
1244
                    case 0xc9:
1245
                        gen_op_load_fpr_FT1(rs2);
1246
                        gen_op_fstod();
1247
                        gen_op_store_DT0_fpr(DFPREG(rd));
1248
                        break;
1249
                    case 0xcb: /* fqtod */
1250
                        goto nfpu_insn;
1251
                    case 0xcc: /* fitoq */
1252
                        goto nfpu_insn;
1253
                    case 0xcd: /* fstoq */
1254
                        goto nfpu_insn;
1255
                    case 0xce: /* fdtoq */
1256
                        goto nfpu_insn;
1257
                    case 0xd1:
1258
                        gen_op_load_fpr_FT1(rs2);
1259
                        gen_op_fstoi();
1260
                        gen_op_store_FT0_fpr(rd);
1261
                        break;
1262
                    case 0xd2:
1263
                        gen_op_load_fpr_DT1(rs2);
1264
                        gen_op_fdtoi();
1265
                        gen_op_store_FT0_fpr(rd);
1266
                        break;
1267
                    case 0xd3: /* fqtoi */
1268
                        goto nfpu_insn;
1269
#ifdef TARGET_SPARC64
1270
                    case 0x2: /* V9 fmovd */
1271
                        gen_op_load_fpr_DT0(DFPREG(rs2));
1272
                        gen_op_store_DT0_fpr(DFPREG(rd));
1273
                        break;
1274
                    case 0x6: /* V9 fnegd */
1275
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1276
                        gen_op_fnegd();
1277
                        gen_op_store_DT0_fpr(DFPREG(rd));
1278
                        break;
1279
                    case 0xa: /* V9 fabsd */
1280
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1281
                        gen_op_fabsd();
1282
                        gen_op_store_DT0_fpr(DFPREG(rd));
1283
                        break;
1284
                    case 0x81: /* V9 fstox */
1285
                        gen_op_load_fpr_FT1(rs2);
1286
                        gen_op_fstox();
1287
                        gen_op_store_DT0_fpr(DFPREG(rd));
1288
                        break;
1289
                    case 0x82: /* V9 fdtox */
1290
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1291
                        gen_op_fdtox();
1292
                        gen_op_store_DT0_fpr(DFPREG(rd));
1293
                        break;
1294
                    case 0x84: /* V9 fxtos */
1295
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1296
                        gen_op_fxtos();
1297
                        gen_op_store_FT0_fpr(rd);
1298
                        break;
1299
                    case 0x88: /* V9 fxtod */
1300
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1301
                        gen_op_fxtod();
1302
                        gen_op_store_DT0_fpr(DFPREG(rd));
1303
                        break;
1304
                    case 0x3: /* V9 fmovq */
1305
                    case 0x7: /* V9 fnegq */
1306
                    case 0xb: /* V9 fabsq */
1307
                    case 0x83: /* V9 fqtox */
1308
                    case 0x8c: /* V9 fxtoq */
1309
                        goto nfpu_insn;
1310
#endif
1311
                    default:
1312
                        goto illegal_insn;
1313
                }
1314
            } else if (xop == 0x35) {        /* FPU Operations */
1315
#ifdef TARGET_SPARC64
1316
                int cond;
1317
#endif
1318
#if !defined(CONFIG_USER_ONLY)
1319
                gen_op_trap_ifnofpu();
1320
#endif
1321
                rs1 = GET_FIELD(insn, 13, 17);
1322
                rs2 = GET_FIELD(insn, 27, 31);
1323
                xop = GET_FIELD(insn, 18, 26);
1324
#ifdef TARGET_SPARC64
1325
                if ((xop & 0x11f) == 0x005) { // V9 fmovsr
1326
                    cond = GET_FIELD_SP(insn, 14, 17);
1327
                    gen_op_load_fpr_FT0(rd);
1328
                    gen_op_load_fpr_FT1(rs2);
1329
                    rs1 = GET_FIELD(insn, 13, 17);
1330
                    gen_movl_reg_T0(rs1);
1331
                    flush_T2(dc);
1332
                    gen_cond_reg(cond);
1333
                    gen_op_fmovs_cc();
1334
                    gen_op_store_FT0_fpr(rd);
1335
                    break;
1336
                } else if ((xop & 0x11f) == 0x006) { // V9 fmovdr
1337
                    cond = GET_FIELD_SP(insn, 14, 17);
1338
                    gen_op_load_fpr_DT0(rd);
1339
                    gen_op_load_fpr_DT1(rs2);
1340
                    flush_T2(dc);
1341
                    rs1 = GET_FIELD(insn, 13, 17);
1342
                    gen_movl_reg_T0(rs1);
1343
                    gen_cond_reg(cond);
1344
                    gen_op_fmovs_cc();
1345
                    gen_op_store_DT0_fpr(rd);
1346
                    break;
1347
                } else if ((xop & 0x11f) == 0x007) { // V9 fmovqr
1348
                    goto nfpu_insn;
1349
                }
1350
#endif
1351
                switch (xop) {
1352
#ifdef TARGET_SPARC64
1353
                    case 0x001: /* V9 fmovscc %fcc0 */
1354
                        cond = GET_FIELD_SP(insn, 14, 17);
1355
                        gen_op_load_fpr_FT0(rd);
1356
                        gen_op_load_fpr_FT1(rs2);
1357
                        flush_T2(dc);
1358
                        gen_fcond[0][cond]();
1359
                        gen_op_fmovs_cc();
1360
                        gen_op_store_FT0_fpr(rd);
1361
                        break;
1362
                    case 0x002: /* V9 fmovdcc %fcc0 */
1363
                        cond = GET_FIELD_SP(insn, 14, 17);
1364
                        gen_op_load_fpr_DT0(rd);
1365
                        gen_op_load_fpr_DT1(rs2);
1366
                        flush_T2(dc);
1367
                        gen_fcond[0][cond]();
1368
                        gen_op_fmovd_cc();
1369
                        gen_op_store_DT0_fpr(rd);
1370
                        break;
1371
                    case 0x003: /* V9 fmovqcc %fcc0 */
1372
                        goto nfpu_insn;
1373
                    case 0x041: /* V9 fmovscc %fcc1 */
1374
                        cond = GET_FIELD_SP(insn, 14, 17);
1375
                        gen_op_load_fpr_FT0(rd);
1376
                        gen_op_load_fpr_FT1(rs2);
1377
                        flush_T2(dc);
1378
                        gen_fcond[1][cond]();
1379
                        gen_op_fmovs_cc();
1380
                        gen_op_store_FT0_fpr(rd);
1381
                        break;
1382
                    case 0x042: /* V9 fmovdcc %fcc1 */
1383
                        cond = GET_FIELD_SP(insn, 14, 17);
1384
                        gen_op_load_fpr_DT0(rd);
1385
                        gen_op_load_fpr_DT1(rs2);
1386
                        flush_T2(dc);
1387
                        gen_fcond[1][cond]();
1388
                        gen_op_fmovd_cc();
1389
                        gen_op_store_DT0_fpr(rd);
1390
                        break;
1391
                    case 0x043: /* V9 fmovqcc %fcc1 */
1392
                        goto nfpu_insn;
1393
                    case 0x081: /* V9 fmovscc %fcc2 */
1394
                        cond = GET_FIELD_SP(insn, 14, 17);
1395
                        gen_op_load_fpr_FT0(rd);
1396
                        gen_op_load_fpr_FT1(rs2);
1397
                        flush_T2(dc);
1398
                        gen_fcond[2][cond]();
1399
                        gen_op_fmovs_cc();
1400
                        gen_op_store_FT0_fpr(rd);
1401
                        break;
1402
                    case 0x082: /* V9 fmovdcc %fcc2 */
1403
                        cond = GET_FIELD_SP(insn, 14, 17);
1404
                        gen_op_load_fpr_DT0(rd);
1405
                        gen_op_load_fpr_DT1(rs2);
1406
                        flush_T2(dc);
1407
                        gen_fcond[2][cond]();
1408
                        gen_op_fmovd_cc();
1409
                        gen_op_store_DT0_fpr(rd);
1410
                        break;
1411
                    case 0x083: /* V9 fmovqcc %fcc2 */
1412
                        goto nfpu_insn;
1413
                    case 0x0c1: /* V9 fmovscc %fcc3 */
1414
                        cond = GET_FIELD_SP(insn, 14, 17);
1415
                        gen_op_load_fpr_FT0(rd);
1416
                        gen_op_load_fpr_FT1(rs2);
1417
                        flush_T2(dc);
1418
                        gen_fcond[3][cond]();
1419
                        gen_op_fmovs_cc();
1420
                        gen_op_store_FT0_fpr(rd);
1421
                        break;
1422
                    case 0x0c2: /* V9 fmovdcc %fcc3 */
1423
                        cond = GET_FIELD_SP(insn, 14, 17);
1424
                        gen_op_load_fpr_DT0(rd);
1425
                        gen_op_load_fpr_DT1(rs2);
1426
                        flush_T2(dc);
1427
                        gen_fcond[3][cond]();
1428
                        gen_op_fmovd_cc();
1429
                        gen_op_store_DT0_fpr(rd);
1430
                        break;
1431
                    case 0x0c3: /* V9 fmovqcc %fcc3 */
1432
                        goto nfpu_insn;
1433
                    case 0x101: /* V9 fmovscc %icc */
1434
                        cond = GET_FIELD_SP(insn, 14, 17);
1435
                        gen_op_load_fpr_FT0(rd);
1436
                        gen_op_load_fpr_FT1(rs2);
1437
                        flush_T2(dc);
1438
                        gen_cond[0][cond]();
1439
                        gen_op_fmovs_cc();
1440
                        gen_op_store_FT0_fpr(rd);
1441
                        break;
1442
                    case 0x102: /* V9 fmovdcc %icc */
1443
                        cond = GET_FIELD_SP(insn, 14, 17);
1444
                        gen_op_load_fpr_DT0(rd);
1445
                        gen_op_load_fpr_DT1(rs2);
1446
                        flush_T2(dc);
1447
                        gen_cond[0][cond]();
1448
                        gen_op_fmovd_cc();
1449
                        gen_op_store_DT0_fpr(rd);
1450
                        break;
1451
                    case 0x103: /* V9 fmovqcc %icc */
1452
                        goto nfpu_insn;
1453
                    case 0x181: /* V9 fmovscc %xcc */
1454
                        cond = GET_FIELD_SP(insn, 14, 17);
1455
                        gen_op_load_fpr_FT0(rd);
1456
                        gen_op_load_fpr_FT1(rs2);
1457
                        flush_T2(dc);
1458
                        gen_cond[1][cond]();
1459
                        gen_op_fmovs_cc();
1460
                        gen_op_store_FT0_fpr(rd);
1461
                        break;
1462
                    case 0x182: /* V9 fmovdcc %xcc */
1463
                        cond = GET_FIELD_SP(insn, 14, 17);
1464
                        gen_op_load_fpr_DT0(rd);
1465
                        gen_op_load_fpr_DT1(rs2);
1466
                        flush_T2(dc);
1467
                        gen_cond[1][cond]();
1468
                        gen_op_fmovd_cc();
1469
                        gen_op_store_DT0_fpr(rd);
1470
                        break;
1471
                    case 0x183: /* V9 fmovqcc %xcc */
1472
                        goto nfpu_insn;
1473
#endif
1474
                    case 0x51: /* V9 %fcc */
1475
                        gen_op_load_fpr_FT0(rs1);
1476
                        gen_op_load_fpr_FT1(rs2);
1477
#ifdef TARGET_SPARC64
1478
                        gen_fcmps[rd & 3]();
1479
#else
1480
                        gen_op_fcmps();
1481
#endif
1482
                        break;
1483
                    case 0x52: /* V9 %fcc */
1484
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1485
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1486
#ifdef TARGET_SPARC64
1487
                        gen_fcmpd[rd & 3]();
1488
#else
1489
                        gen_op_fcmpd();
1490
#endif
1491
                        break;
1492
                    case 0x53: /* fcmpq */
1493
                        goto nfpu_insn;
1494
                    case 0x55: /* fcmpes, V9 %fcc */
1495
                        gen_op_load_fpr_FT0(rs1);
1496
                        gen_op_load_fpr_FT1(rs2);
1497
#ifdef TARGET_SPARC64
1498
                        gen_fcmps[rd & 3]();
1499
#else
1500
                        gen_op_fcmps(); /* XXX should trap if qNaN or sNaN  */
1501
#endif
1502
                        break;
1503
                    case 0x56: /* fcmped, V9 %fcc */
1504
                        gen_op_load_fpr_DT0(DFPREG(rs1));
1505
                        gen_op_load_fpr_DT1(DFPREG(rs2));
1506
#ifdef TARGET_SPARC64
1507
                        gen_fcmpd[rd & 3]();
1508
#else
1509
                        gen_op_fcmpd(); /* XXX should trap if qNaN or sNaN  */
1510
#endif
1511
                        break;
1512
                    case 0x57: /* fcmpeq */
1513
                        goto nfpu_insn;
1514
                    default:
1515
                        goto illegal_insn;
1516
                }
1517
#if defined(OPTIM)
1518
            } else if (xop == 0x2) {
1519
                // clr/mov shortcut
1520

    
1521
                rs1 = GET_FIELD(insn, 13, 17);
1522
                if (rs1 == 0) {
1523
                    // or %g0, x, y -> mov T1, x; mov y, T1
1524
                    if (IS_IMM) {        /* immediate */
1525
                        rs2 = GET_FIELDs(insn, 19, 31);
1526
                        gen_movl_simm_T1(rs2);
1527
                    } else {                /* register */
1528
                        rs2 = GET_FIELD(insn, 27, 31);
1529
                        gen_movl_reg_T1(rs2);
1530
                    }
1531
                    gen_movl_T1_reg(rd);
1532
                } else {
1533
                    gen_movl_reg_T0(rs1);
1534
                    if (IS_IMM) {        /* immediate */
1535
                        // or x, #0, y -> mov T1, x; mov y, T1
1536
                        rs2 = GET_FIELDs(insn, 19, 31);
1537
                        if (rs2 != 0) {
1538
                            gen_movl_simm_T1(rs2);
1539
                            gen_op_or_T1_T0();
1540
                        }
1541
                    } else {                /* register */
1542
                        // or x, %g0, y -> mov T1, x; mov y, T1
1543
                        rs2 = GET_FIELD(insn, 27, 31);
1544
                        if (rs2 != 0) {
1545
                            gen_movl_reg_T1(rs2);
1546
                            gen_op_or_T1_T0();
1547
                        }
1548
                    }
1549
                    gen_movl_T0_reg(rd);
1550
                }
1551
#endif
1552
            } else if (xop < 0x38) {
1553
                rs1 = GET_FIELD(insn, 13, 17);
1554
                gen_movl_reg_T0(rs1);
1555
                if (IS_IMM) {        /* immediate */
1556
                    rs2 = GET_FIELDs(insn, 19, 31);
1557
                    gen_movl_simm_T1(rs2);
1558
                } else {                /* register */
1559
                    rs2 = GET_FIELD(insn, 27, 31);
1560
                    gen_movl_reg_T1(rs2);
1561
                }
1562
                if (xop < 0x20) {
1563
                    switch (xop & ~0x10) {
1564
                    case 0x0:
1565
                        if (xop & 0x10)
1566
                            gen_op_add_T1_T0_cc();
1567
                        else
1568
                            gen_op_add_T1_T0();
1569
                        break;
1570
                    case 0x1:
1571
                        gen_op_and_T1_T0();
1572
                        if (xop & 0x10)
1573
                            gen_op_logic_T0_cc();
1574
                        break;
1575
                    case 0x2:
1576
                        gen_op_or_T1_T0();
1577
                        if (xop & 0x10)
1578
                            gen_op_logic_T0_cc();
1579
                        break;
1580
                    case 0x3:
1581
                        gen_op_xor_T1_T0();
1582
                        if (xop & 0x10)
1583
                            gen_op_logic_T0_cc();
1584
                        break;
1585
                    case 0x4:
1586
                        if (xop & 0x10)
1587
                            gen_op_sub_T1_T0_cc();
1588
                        else
1589
                            gen_op_sub_T1_T0();
1590
                        break;
1591
                    case 0x5:
1592
                        gen_op_andn_T1_T0();
1593
                        if (xop & 0x10)
1594
                            gen_op_logic_T0_cc();
1595
                        break;
1596
                    case 0x6:
1597
                        gen_op_orn_T1_T0();
1598
                        if (xop & 0x10)
1599
                            gen_op_logic_T0_cc();
1600
                        break;
1601
                    case 0x7:
1602
                        gen_op_xnor_T1_T0();
1603
                        if (xop & 0x10)
1604
                            gen_op_logic_T0_cc();
1605
                        break;
1606
                    case 0x8:
1607
                        if (xop & 0x10)
1608
                            gen_op_addx_T1_T0_cc();
1609
                        else
1610
                            gen_op_addx_T1_T0();
1611
                        break;
1612
                    case 0xa:
1613
                        gen_op_umul_T1_T0();
1614
                        if (xop & 0x10)
1615
                            gen_op_logic_T0_cc();
1616
                        break;
1617
                    case 0xb:
1618
                        gen_op_smul_T1_T0();
1619
                        if (xop & 0x10)
1620
                            gen_op_logic_T0_cc();
1621
                        break;
1622
                    case 0xc:
1623
                        if (xop & 0x10)
1624
                            gen_op_subx_T1_T0_cc();
1625
                        else
1626
                            gen_op_subx_T1_T0();
1627
                        break;
1628
                    case 0xe:
1629
                        gen_op_udiv_T1_T0();
1630
                        if (xop & 0x10)
1631
                            gen_op_div_cc();
1632
                        break;
1633
                    case 0xf:
1634
                        gen_op_sdiv_T1_T0();
1635
                        if (xop & 0x10)
1636
                            gen_op_div_cc();
1637
                        break;
1638
                    default:
1639
                        goto illegal_insn;
1640
                    }
1641
                    gen_movl_T0_reg(rd);
1642
                } else {
1643
                    switch (xop) {
1644
#ifdef TARGET_SPARC64
1645
                    case 0x9: /* V9 mulx */
1646
                        gen_op_mulx_T1_T0();
1647
                        gen_movl_T0_reg(rd);
1648
                        break;
1649
                    case 0xd: /* V9 udivx */
1650
                        gen_op_udivx_T1_T0();
1651
                        gen_movl_T0_reg(rd);
1652
                        break;
1653
#endif
1654
                    case 0x20: /* taddcc */
1655
                    case 0x21: /* tsubcc */
1656
                    case 0x22: /* taddcctv */
1657
                    case 0x23: /* tsubcctv */
1658
                        goto illegal_insn;
1659
                    case 0x24: /* mulscc */
1660
                        gen_op_mulscc_T1_T0();
1661
                        gen_movl_T0_reg(rd);
1662
                        break;
1663
                    case 0x25:        /* sll, V9 sllx ( == sll) */
1664
                        gen_op_sll();
1665
                        gen_movl_T0_reg(rd);
1666
                        break;
1667
                    case 0x26:  /* srl, V9 srlx */
1668
#ifdef TARGET_SPARC64
1669
                        if (insn & (1 << 12))
1670
                            gen_op_srlx();
1671
                        else
1672
                            gen_op_srl();
1673
#else
1674
                        gen_op_srl();
1675
#endif
1676
                        gen_movl_T0_reg(rd);
1677
                        break;
1678
                    case 0x27:  /* sra, V9 srax */
1679
#ifdef TARGET_SPARC64
1680
                        if (insn & (1 << 12))
1681
                            gen_op_srax();
1682
                        else
1683
                            gen_op_sra();
1684
#else
1685
                        gen_op_sra();
1686
#endif
1687
                        gen_movl_T0_reg(rd);
1688
                        break;
1689
                    case 0x30:
1690
                        {
1691
                            switch(rd) {
1692
                            case 0: /* wry */
1693
                                gen_op_xor_T1_T0();
1694
                                gen_op_movtl_env_T0(offsetof(CPUSPARCState, y));
1695
                                break;
1696
#ifdef TARGET_SPARC64
1697
                            case 0x2: /* V9 wrccr */
1698
                                gen_op_wrccr();
1699
                                break;
1700
                            case 0x3: /* V9 wrasi */
1701
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, asi));
1702
                                break;
1703
                            case 0x6: /* V9 wrfprs */
1704
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, fprs));
1705
                                break;
1706
                            case 0xf: /* V9 sir, nop if user */
1707
#if !defined(CONFIG_USER_ONLY)
1708
                                if (supervisor(dc))
1709
                                    gen_op_sir();
1710
#endif
1711
                                break;
1712
#endif
1713
                            case 0x10: /* Performance Control */
1714
                            case 0x11: /* Performance Instrumentation Counter */
1715
                            case 0x12: /* Dispatch Control */
1716
                            case 0x13: /* Graphics Status */
1717
                            case 0x14: /* Softint set */
1718
                            case 0x15: /* Softint clear */
1719
                            case 0x16: /* Softint write */
1720
                            case 0x17: /* Tick compare */
1721
                            case 0x18: /* System tick */
1722
                            case 0x19: /* System tick compare */
1723
                            default:
1724
                                goto illegal_insn;
1725
                            }
1726
                        }
1727
                        break;
1728
#if !defined(CONFIG_USER_ONLY)
1729
                    case 0x31: /* wrpsr, V9 saved, restored */
1730
                        {
1731
                            if (!supervisor(dc))
1732
                                goto priv_insn;
1733
#ifdef TARGET_SPARC64
1734
                            switch (rd) {
1735
                            case 0:
1736
                                gen_op_saved();
1737
                                break;
1738
                            case 1:
1739
                                gen_op_restored();
1740
                                break;
1741
                            default:
1742
                                goto illegal_insn;
1743
                            }
1744
#else
1745
                            gen_op_xor_T1_T0();
1746
                            gen_op_wrpsr();
1747
#endif
1748
                        }
1749
                        break;
1750
                    case 0x32: /* wrwim, V9 wrpr */
1751
                        {
1752
                            if (!supervisor(dc))
1753
                                goto priv_insn;
1754
                            gen_op_xor_T1_T0();
1755
#ifdef TARGET_SPARC64
1756
                            switch (rd) {
1757
                            case 0: // tpc
1758
                                gen_op_wrtpc();
1759
                                break;
1760
                            case 1: // tnpc
1761
                                gen_op_wrtnpc();
1762
                                break;
1763
                            case 2: // tstate
1764
                                gen_op_wrtstate();
1765
                                break;
1766
                            case 3: // tt
1767
                                gen_op_wrtt();
1768
                                break;
1769
                            case 4: // tick
1770
                                gen_op_wrtick();
1771
                                break;
1772
                            case 5: // tba
1773
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, tbr));
1774
                                break;
1775
                            case 6: // pstate
1776
                                gen_op_wrpstate();
1777
                                break;
1778
                            case 7: // tl
1779
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, tl));
1780
                                break;
1781
                            case 8: // pil
1782
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, psrpil));
1783
                                break;
1784
                            case 9: // cwp
1785
                                gen_op_wrcwp();
1786
                                break;
1787
                            case 10: // cansave
1788
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, cansave));
1789
                                break;
1790
                            case 11: // canrestore
1791
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, canrestore));
1792
                                break;
1793
                            case 12: // cleanwin
1794
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, cleanwin));
1795
                                break;
1796
                            case 13: // otherwin
1797
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, otherwin));
1798
                                break;
1799
                            case 14: // wstate
1800
                                gen_op_movl_env_T0(offsetof(CPUSPARCState, wstate));
1801
                                break;
1802
                            default:
1803
                                goto illegal_insn;
1804
                            }
1805
#else
1806
                            gen_op_movl_env_T0(offsetof(CPUSPARCState, wim));
1807
#endif
1808
                        }
1809
                        break;
1810
#ifndef TARGET_SPARC64
1811
                    case 0x33: /* wrtbr, V9 unimp */
1812
                        {
1813
                            if (!supervisor(dc))
1814
                                goto priv_insn;
1815
                            gen_op_xor_T1_T0();
1816
                            gen_op_movtl_env_T0(offsetof(CPUSPARCState, tbr));
1817
                        }
1818
                        break;
1819
#endif
1820
#endif
1821
#ifdef TARGET_SPARC64
1822
                    case 0x2c: /* V9 movcc */
1823
                        {
1824
                            int cc = GET_FIELD_SP(insn, 11, 12);
1825
                            int cond = GET_FIELD_SP(insn, 14, 17);
1826
                            if (IS_IMM) {        /* immediate */
1827
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
1828
                                gen_movl_simm_T1(rs2);
1829
                            }
1830
                            else {
1831
                                rs2 = GET_FIELD_SP(insn, 0, 4);
1832
                                gen_movl_reg_T1(rs2);
1833
                            }
1834
                            gen_movl_reg_T0(rd);
1835
                            flush_T2(dc);
1836
                            if (insn & (1 << 18)) {
1837
                                if (cc == 0)
1838
                                    gen_cond[0][cond]();
1839
                                else if (cc == 2)
1840
                                    gen_cond[1][cond]();
1841
                                else
1842
                                    goto illegal_insn;
1843
                            } else {
1844
                                gen_fcond[cc][cond]();
1845
                            }
1846
                            gen_op_mov_cc();
1847
                            gen_movl_T0_reg(rd);
1848
                            break;
1849
                        }
1850
                    case 0x2d: /* V9 sdivx */
1851
                        gen_op_sdivx_T1_T0();
1852
                        gen_movl_T0_reg(rd);
1853
                        break;
1854
                    case 0x2e: /* V9 popc */
1855
                        {
1856
                            if (IS_IMM) {        /* immediate */
1857
                                rs2 = GET_FIELD_SPs(insn, 0, 12);
1858
                                gen_movl_simm_T1(rs2);
1859
                                // XXX optimize: popc(constant)
1860
                            }
1861
                            else {
1862
                                rs2 = GET_FIELD_SP(insn, 0, 4);
1863
                                gen_movl_reg_T1(rs2);
1864
                            }
1865
                            gen_op_popc();
1866
                            gen_movl_T0_reg(rd);
1867
                        }
1868
                    case 0x2f: /* V9 movr */
1869
                        {
1870
                            int cond = GET_FIELD_SP(insn, 10, 12);
1871
                            rs1 = GET_FIELD(insn, 13, 17);
1872
                            flush_T2(dc);
1873
                            gen_movl_reg_T0(rs1);
1874
                            gen_cond_reg(cond);
1875
                            if (IS_IMM) {        /* immediate */
1876
                                rs2 = GET_FIELD_SPs(insn, 0, 10);
1877
                                gen_movl_simm_T1(rs2);
1878
                            }
1879
                            else {
1880
                                rs2 = GET_FIELD_SP(insn, 0, 4);
1881
                                gen_movl_reg_T1(rs2);
1882
                            }
1883
                            gen_movl_reg_T0(rd);
1884
                            gen_op_mov_cc();
1885
                            gen_movl_T0_reg(rd);
1886
                            break;
1887
                        }
1888
                    case 0x36: /* UltraSparc shutdown, VIS */
1889
                        {
1890
                            // XXX
1891
                        }
1892
#endif
1893
                    default:
1894
                        goto illegal_insn;
1895
                    }
1896
                }
1897
#ifdef TARGET_SPARC64
1898
            } else if (xop == 0x39) { /* V9 return */
1899
                gen_op_restore();
1900
                rs1 = GET_FIELD(insn, 13, 17);
1901
                gen_movl_reg_T0(rs1);
1902
                if (IS_IMM) {        /* immediate */
1903
                    rs2 = GET_FIELDs(insn, 19, 31);
1904
#if defined(OPTIM)
1905
                    if (rs2) {
1906
#endif
1907
                        gen_movl_simm_T1(rs2);
1908
                        gen_op_add_T1_T0();
1909
#if defined(OPTIM)
1910
                    }
1911
#endif
1912
                } else {                /* register */
1913
                    rs2 = GET_FIELD(insn, 27, 31);
1914
#if defined(OPTIM)
1915
                    if (rs2) {
1916
#endif
1917
                        gen_movl_reg_T1(rs2);
1918
                        gen_op_add_T1_T0();
1919
#if defined(OPTIM)
1920
                    }
1921
#endif
1922
                }
1923
                gen_mov_pc_npc(dc);
1924
                gen_op_movl_npc_T0();
1925
                dc->npc = DYNAMIC_PC;
1926
                goto jmp_insn;
1927
#endif
1928
            } else {
1929
                rs1 = GET_FIELD(insn, 13, 17);
1930
                gen_movl_reg_T0(rs1);
1931
                if (IS_IMM) {        /* immediate */
1932
                    rs2 = GET_FIELDs(insn, 19, 31);
1933
#if defined(OPTIM)
1934
                    if (rs2) {
1935
#endif
1936
                        gen_movl_simm_T1(rs2);
1937
                        gen_op_add_T1_T0();
1938
#if defined(OPTIM)
1939
                    }
1940
#endif
1941
                } else {                /* register */
1942
                    rs2 = GET_FIELD(insn, 27, 31);
1943
#if defined(OPTIM)
1944
                    if (rs2) {
1945
#endif
1946
                        gen_movl_reg_T1(rs2);
1947
                        gen_op_add_T1_T0();
1948
#if defined(OPTIM)
1949
                    }
1950
#endif
1951
                }
1952
                switch (xop) {
1953
                case 0x38:        /* jmpl */
1954
                    {
1955
                        if (rd != 0) {
1956
                            gen_op_movl_T1_im(dc->pc);
1957
                            gen_movl_T1_reg(rd);
1958
                        }
1959
                        gen_mov_pc_npc(dc);
1960
                        gen_op_movl_npc_T0();
1961
                        dc->npc = DYNAMIC_PC;
1962
                    }
1963
                    goto jmp_insn;
1964
#if !defined(CONFIG_USER_ONLY) && !defined(TARGET_SPARC64)
1965
                case 0x39:        /* rett, V9 return */
1966
                    {
1967
                        if (!supervisor(dc))
1968
                            goto priv_insn;
1969
                        gen_mov_pc_npc(dc);
1970
                        gen_op_movl_npc_T0();
1971
                        dc->npc = DYNAMIC_PC;
1972
                        gen_op_rett();
1973
                    }
1974
                    goto jmp_insn;
1975
#endif
1976
                case 0x3b: /* flush */
1977
                    gen_op_flush_T0();
1978
                    break;
1979
                case 0x3c:        /* save */
1980
                    save_state(dc);
1981
                    gen_op_save();
1982
                    gen_movl_T0_reg(rd);
1983
                    break;
1984
                case 0x3d:        /* restore */
1985
                    save_state(dc);
1986
                    gen_op_restore();
1987
                    gen_movl_T0_reg(rd);
1988
                    break;
1989
#if !defined(CONFIG_USER_ONLY) && defined(TARGET_SPARC64)
1990
                case 0x3e:      /* V9 done/retry */
1991
                    {
1992
                        switch (rd) {
1993
                        case 0:
1994
                            if (!supervisor(dc))
1995
                                goto priv_insn;
1996
                            gen_op_done();
1997
                            break;
1998
                        case 1:
1999
                            if (!supervisor(dc))
2000
                                goto priv_insn;
2001
                            gen_op_retry();
2002
                            break;
2003
                        default:
2004
                            goto illegal_insn;
2005
                        }
2006
                    }
2007
                    break;
2008
#endif
2009
                default:
2010
                    goto illegal_insn;
2011
                }
2012
            }
2013
            break;
2014
        }
2015
        break;
2016
    case 3:                        /* load/store instructions */
2017
        {
2018
            unsigned int xop = GET_FIELD(insn, 7, 12);
2019
            rs1 = GET_FIELD(insn, 13, 17);
2020
            gen_movl_reg_T0(rs1);
2021
            if (IS_IMM) {        /* immediate */
2022
                rs2 = GET_FIELDs(insn, 19, 31);
2023
#if defined(OPTIM)
2024
                if (rs2 != 0) {
2025
#endif
2026
                    gen_movl_simm_T1(rs2);
2027
                    gen_op_add_T1_T0();
2028
#if defined(OPTIM)
2029
                }
2030
#endif
2031
            } else {                /* register */
2032
                rs2 = GET_FIELD(insn, 27, 31);
2033
#if defined(OPTIM)
2034
                if (rs2 != 0) {
2035
#endif
2036
                    gen_movl_reg_T1(rs2);
2037
                    gen_op_add_T1_T0();
2038
#if defined(OPTIM)
2039
                }
2040
#endif
2041
            }
2042
            if (xop < 4 || (xop > 7 && xop < 0x14 && xop != 0x0e) || \
2043
                    (xop > 0x17 && xop < 0x1d ) || \
2044
                    (xop > 0x2c && xop < 0x33) || xop == 0x1f) {
2045
                switch (xop) {
2046
                case 0x0:        /* load word */
2047
                    gen_op_ldst(ld);
2048
                    break;
2049
                case 0x1:        /* load unsigned byte */
2050
                    gen_op_ldst(ldub);
2051
                    break;
2052
                case 0x2:        /* load unsigned halfword */
2053
                    gen_op_ldst(lduh);
2054
                    break;
2055
                case 0x3:        /* load double word */
2056
                    gen_op_ldst(ldd);
2057
                    gen_movl_T0_reg(rd + 1);
2058
                    break;
2059
                case 0x9:        /* load signed byte */
2060
                    gen_op_ldst(ldsb);
2061
                    break;
2062
                case 0xa:        /* load signed halfword */
2063
                    gen_op_ldst(ldsh);
2064
                    break;
2065
                case 0xd:        /* ldstub -- XXX: should be atomically */
2066
                    gen_op_ldst(ldstub);
2067
                    break;
2068
                case 0x0f:        /* swap register with memory. Also atomically */
2069
                    gen_movl_reg_T1(rd);
2070
                    gen_op_ldst(swap);
2071
                    break;
2072
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2073
                case 0x10:        /* load word alternate */
2074
#ifndef TARGET_SPARC64
2075
                    if (!supervisor(dc))
2076
                        goto priv_insn;
2077
#endif
2078
                    gen_op_lda(insn, 1, 4, 0);
2079
                    break;
2080
                case 0x11:        /* load unsigned byte alternate */
2081
#ifndef TARGET_SPARC64
2082
                    if (!supervisor(dc))
2083
                        goto priv_insn;
2084
#endif
2085
                    gen_op_lduba(insn, 1, 1, 0);
2086
                    break;
2087
                case 0x12:        /* load unsigned halfword alternate */
2088
#ifndef TARGET_SPARC64
2089
                    if (!supervisor(dc))
2090
                        goto priv_insn;
2091
#endif
2092
                    gen_op_lduha(insn, 1, 2, 0);
2093
                    break;
2094
                case 0x13:        /* load double word alternate */
2095
#ifndef TARGET_SPARC64
2096
                    if (!supervisor(dc))
2097
                        goto priv_insn;
2098
#endif
2099
                    gen_op_ldda(insn, 1, 8, 0);
2100
                    gen_movl_T0_reg(rd + 1);
2101
                    break;
2102
                case 0x19:        /* load signed byte alternate */
2103
#ifndef TARGET_SPARC64
2104
                    if (!supervisor(dc))
2105
                        goto priv_insn;
2106
#endif
2107
                    gen_op_ldsba(insn, 1, 1, 1);
2108
                    break;
2109
                case 0x1a:        /* load signed halfword alternate */
2110
#ifndef TARGET_SPARC64
2111
                    if (!supervisor(dc))
2112
                        goto priv_insn;
2113
#endif
2114
                    gen_op_ldsha(insn, 1, 2 ,1);
2115
                    break;
2116
                case 0x1d:        /* ldstuba -- XXX: should be atomically */
2117
#ifndef TARGET_SPARC64
2118
                    if (!supervisor(dc))
2119
                        goto priv_insn;
2120
#endif
2121
                    gen_op_ldstuba(insn, 1, 1, 0);
2122
                    break;
2123
                case 0x1f:        /* swap reg with alt. memory. Also atomically */
2124
#ifndef TARGET_SPARC64
2125
                    if (!supervisor(dc))
2126
                        goto priv_insn;
2127
#endif
2128
                    gen_movl_reg_T1(rd);
2129
                    gen_op_swapa(insn, 1, 4, 0);
2130
                    break;
2131

    
2132
#ifndef TARGET_SPARC64
2133
                    /* avoid warnings */
2134
                    (void) &gen_op_stfa;
2135
                    (void) &gen_op_stdfa;
2136
                    (void) &gen_op_ldfa;
2137
                    (void) &gen_op_lddfa;
2138
#else
2139
#if !defined(CONFIG_USER_ONLY)
2140
                    (void) &gen_op_cas;
2141
                    (void) &gen_op_casx;
2142
#endif
2143
#endif
2144
#endif
2145
#ifdef TARGET_SPARC64
2146
                case 0x08: /* V9 ldsw */
2147
                    gen_op_ldst(ldsw);
2148
                    break;
2149
                case 0x0b: /* V9 ldx */
2150
                    gen_op_ldst(ldx);
2151
                    break;
2152
                case 0x18: /* V9 ldswa */
2153
                    gen_op_ldswa(insn, 1, 4, 1);
2154
                    break;
2155
                case 0x1b: /* V9 ldxa */
2156
                    gen_op_ldxa(insn, 1, 8, 0);
2157
                    break;
2158
                case 0x2d: /* V9 prefetch, no effect */
2159
                    goto skip_move;
2160
                case 0x30: /* V9 ldfa */
2161
                    gen_op_ldfa(insn, 1, 8, 0); // XXX
2162
                    break;
2163
                case 0x33: /* V9 lddfa */
2164
                    gen_op_lddfa(insn, 1, 8, 0); // XXX
2165

    
2166
                    break;
2167
                case 0x3d: /* V9 prefetcha, no effect */
2168
                    goto skip_move;
2169
                case 0x32: /* V9 ldqfa */
2170
                    goto nfpu_insn;
2171
#endif
2172
                default:
2173
                    goto illegal_insn;
2174
                }
2175
                gen_movl_T1_reg(rd);
2176
#ifdef TARGET_SPARC64
2177
            skip_move: ;
2178
#endif
2179
            } else if (xop >= 0x20 && xop < 0x24) {
2180
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2181
                gen_op_trap_ifnofpu();
2182
#endif
2183
                switch (xop) {
2184
                case 0x20:        /* load fpreg */
2185
                    gen_op_ldst(ldf);
2186
                    gen_op_store_FT0_fpr(rd);
2187
                    break;
2188
                case 0x21:        /* load fsr */
2189
                    gen_op_ldfsr();
2190
                    gen_op_store_FT0_fpr(rd);
2191
                    break;
2192
                case 0x22:      /* load quad fpreg */
2193
                    goto nfpu_insn;
2194
                case 0x23:        /* load double fpreg */
2195
                    gen_op_ldst(lddf);
2196
                    gen_op_store_DT0_fpr(DFPREG(rd));
2197
                    break;
2198
                default:
2199
                    goto illegal_insn;
2200
                }
2201
            } else if (xop < 8 || (xop >= 0x14 && xop < 0x18) || \
2202
                       xop == 0xe || xop == 0x1e) {
2203
                gen_movl_reg_T1(rd);
2204
                switch (xop) {
2205
                case 0x4:
2206
                    gen_op_ldst(st);
2207
                    break;
2208
                case 0x5:
2209
                    gen_op_ldst(stb);
2210
                    break;
2211
                case 0x6:
2212
                    gen_op_ldst(sth);
2213
                    break;
2214
                case 0x7:
2215
                    flush_T2(dc);
2216
                    gen_movl_reg_T2(rd + 1);
2217
                    gen_op_ldst(std);
2218
                    break;
2219
#if !defined(CONFIG_USER_ONLY) || defined(TARGET_SPARC64)
2220
                case 0x14:
2221
#ifndef TARGET_SPARC64
2222
                    if (!supervisor(dc))
2223
                        goto priv_insn;
2224
#endif
2225
                    gen_op_sta(insn, 0, 4, 0);
2226
                    break;
2227
                case 0x15:
2228
#ifndef TARGET_SPARC64
2229
                    if (!supervisor(dc))
2230
                        goto priv_insn;
2231
#endif
2232
                    gen_op_stba(insn, 0, 1, 0);
2233
                    break;
2234
                case 0x16:
2235
#ifndef TARGET_SPARC64
2236
                    if (!supervisor(dc))
2237
                        goto priv_insn;
2238
#endif
2239
                    gen_op_stha(insn, 0, 2, 0);
2240
                    break;
2241
                case 0x17:
2242
#ifndef TARGET_SPARC64
2243
                    if (!supervisor(dc))
2244
                        goto priv_insn;
2245
#endif
2246
                    flush_T2(dc);
2247
                    gen_movl_reg_T2(rd + 1);
2248
                    gen_op_stda(insn, 0, 8, 0);
2249
                    break;
2250
#endif
2251
#ifdef TARGET_SPARC64
2252
                case 0x0e: /* V9 stx */
2253
                    gen_op_ldst(stx);
2254
                    break;
2255
                case 0x1e: /* V9 stxa */
2256
                    gen_op_stxa(insn, 0, 8, 0); // XXX
2257
                    break;
2258
#endif
2259
                default:
2260
                    goto illegal_insn;
2261
                }
2262
            } else if (xop > 0x23 && xop < 0x28) {
2263
#if !defined(CONFIG_USER_ONLY)
2264
                gen_op_trap_ifnofpu();
2265
#endif
2266
                switch (xop) {
2267
                case 0x24:
2268
                    gen_op_load_fpr_FT0(rd);
2269
                    gen_op_ldst(stf);
2270
                    break;
2271
                case 0x25: /* stfsr, V9 stxfsr */
2272
                    gen_op_load_fpr_FT0(rd);
2273
                    // XXX
2274
                    gen_op_stfsr();
2275
                    break;
2276
                case 0x26: /* stdfq */
2277
                    goto nfpu_insn;
2278
                case 0x27:
2279
                    gen_op_load_fpr_DT0(DFPREG(rd));
2280
                    gen_op_ldst(stdf);
2281
                    break;
2282
                default:
2283
                    goto illegal_insn;
2284
                }
2285
            } else if (xop > 0x33 && xop < 0x3f) {
2286
#ifdef TARGET_SPARC64
2287
                switch (xop) {
2288
                case 0x34: /* V9 stfa */
2289
                    gen_op_stfa(insn, 0, 0, 0); // XXX
2290
                    break;
2291
                case 0x37: /* V9 stdfa */
2292
                    gen_op_stdfa(insn, 0, 0, 0); // XXX
2293
                    break;
2294
                case 0x3c: /* V9 casa */
2295
                    gen_op_casa(insn, 0, 4, 0); // XXX
2296
                    break;
2297
                case 0x3e: /* V9 casxa */
2298
                    gen_op_casxa(insn, 0, 8, 0); // XXX
2299
                    break;
2300
                case 0x36: /* V9 stqfa */
2301
                    goto nfpu_insn;
2302
                default:
2303
                    goto illegal_insn;
2304
                }
2305
#else
2306
                goto illegal_insn;
2307
#endif
2308
            }
2309
            else
2310
                goto illegal_insn;
2311
        }
2312
        break;
2313
    }
2314
    /* default case for non jump instructions */
2315
    if (dc->npc == DYNAMIC_PC) {
2316
        dc->pc = DYNAMIC_PC;
2317
        gen_op_next_insn();
2318
    } else if (dc->npc == JUMP_PC) {
2319
        /* we can do a static jump */
2320
        gen_op_branch2((long)dc->tb, dc->jump_pc[0], dc->jump_pc[1]);
2321
        dc->is_br = 1;
2322
    } else {
2323
        dc->pc = dc->npc;
2324
        dc->npc = dc->npc + 4;
2325
    }
2326
 jmp_insn:
2327
    return;
2328
 illegal_insn:
2329
    save_state(dc);
2330
    gen_op_exception(TT_ILL_INSN);
2331
    dc->is_br = 1;
2332
    return;
2333
#if !defined(CONFIG_USER_ONLY)
2334
 priv_insn:
2335
    save_state(dc);
2336
    gen_op_exception(TT_PRIV_INSN);
2337
    dc->is_br = 1;
2338
    return;
2339
#endif
2340
 nfpu_insn:
2341
    save_state(dc);
2342
    gen_op_fpexception_im(FSR_FTT_UNIMPFPOP);
2343
    dc->is_br = 1;
2344
}
2345

    
2346
static inline int gen_intermediate_code_internal(TranslationBlock * tb,
2347
                                                 int spc, CPUSPARCState *env)
2348
{
2349
    target_ulong pc_start, last_pc;
2350
    uint16_t *gen_opc_end;
2351
    DisasContext dc1, *dc = &dc1;
2352
    int j, lj = -1;
2353

    
2354
    memset(dc, 0, sizeof(DisasContext));
2355
    dc->tb = tb;
2356
    pc_start = tb->pc;
2357
    dc->pc = pc_start;
2358
    last_pc = dc->pc;
2359
    dc->npc = (target_ulong) tb->cs_base;
2360
#if defined(CONFIG_USER_ONLY)
2361
    dc->mem_idx = 0;
2362
#else
2363
    dc->mem_idx = ((env->psrs) != 0);
2364
#endif
2365
    gen_opc_ptr = gen_opc_buf;
2366
    gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
2367
    gen_opparam_ptr = gen_opparam_buf;
2368

    
2369
    do {
2370
        if (env->nb_breakpoints > 0) {
2371
            for(j = 0; j < env->nb_breakpoints; j++) {
2372
                if (env->breakpoints[j] == dc->pc) {
2373
                    if (dc->pc != pc_start)
2374
                        save_state(dc);
2375
                    gen_op_debug();
2376
                    gen_op_movl_T0_0();
2377
                    gen_op_exit_tb();
2378
                    dc->is_br = 1;
2379
                    goto exit_gen_loop;
2380
                }
2381
            }
2382
        }
2383
        if (spc) {
2384
            if (loglevel > 0)
2385
                fprintf(logfile, "Search PC...\n");
2386
            j = gen_opc_ptr - gen_opc_buf;
2387
            if (lj < j) {
2388
                lj++;
2389
                while (lj < j)
2390
                    gen_opc_instr_start[lj++] = 0;
2391
                gen_opc_pc[lj] = dc->pc;
2392
                gen_opc_npc[lj] = dc->npc;
2393
                gen_opc_instr_start[lj] = 1;
2394
            }
2395
        }
2396
        last_pc = dc->pc;
2397
        disas_sparc_insn(dc);
2398

    
2399
        if (dc->is_br)
2400
            break;
2401
        /* if the next PC is different, we abort now */
2402
        if (dc->pc != (last_pc + 4))
2403
            break;
2404
        /* if we reach a page boundary, we stop generation so that the
2405
           PC of a TT_TFAULT exception is always in the right page */
2406
        if ((dc->pc & (TARGET_PAGE_SIZE - 1)) == 0)
2407
            break;
2408
        /* if single step mode, we generate only one instruction and
2409
           generate an exception */
2410
        if (env->singlestep_enabled) {
2411
            gen_jmp_im(dc->pc);
2412
            gen_op_movl_T0_0();
2413
            gen_op_exit_tb();
2414
            break;
2415
        }
2416
    } while ((gen_opc_ptr < gen_opc_end) &&
2417
             (dc->pc - pc_start) < (TARGET_PAGE_SIZE - 32));
2418

    
2419
 exit_gen_loop:
2420
    if (!dc->is_br) {
2421
        if (dc->pc != DYNAMIC_PC && 
2422
            (dc->npc != DYNAMIC_PC && dc->npc != JUMP_PC)) {
2423
            /* static PC and NPC: we can use direct chaining */
2424
            gen_op_branch((long)tb, dc->pc, dc->npc);
2425
        } else {
2426
            if (dc->pc != DYNAMIC_PC)
2427
                gen_jmp_im(dc->pc);
2428
            save_npc(dc);
2429
            gen_op_movl_T0_0();
2430
            gen_op_exit_tb();
2431
        }
2432
    }
2433
    *gen_opc_ptr = INDEX_op_end;
2434
    if (spc) {
2435
        j = gen_opc_ptr - gen_opc_buf;
2436
        lj++;
2437
        while (lj <= j)
2438
            gen_opc_instr_start[lj++] = 0;
2439
        tb->size = 0;
2440
#if 0
2441
        if (loglevel > 0) {
2442
            page_dump(logfile);
2443
        }
2444
#endif
2445
        gen_opc_jump_pc[0] = dc->jump_pc[0];
2446
        gen_opc_jump_pc[1] = dc->jump_pc[1];
2447
    } else {
2448
        tb->size = last_pc + 4 - pc_start;
2449
    }
2450
#ifdef DEBUG_DISAS
2451
    if (loglevel & CPU_LOG_TB_IN_ASM) {
2452
        fprintf(logfile, "--------------\n");
2453
        fprintf(logfile, "IN: %s\n", lookup_symbol(pc_start));
2454
        target_disas(logfile, pc_start, last_pc + 4 - pc_start, 0);
2455
        fprintf(logfile, "\n");
2456
        if (loglevel & CPU_LOG_TB_OP) {
2457
            fprintf(logfile, "OP:\n");
2458
            dump_ops(gen_opc_buf, gen_opparam_buf);
2459
            fprintf(logfile, "\n");
2460
        }
2461
    }
2462
#endif
2463
    return 0;
2464
}
2465

    
2466
int gen_intermediate_code(CPUSPARCState * env, TranslationBlock * tb)
2467
{
2468
    return gen_intermediate_code_internal(tb, 0, env);
2469
}
2470

    
2471
int gen_intermediate_code_pc(CPUSPARCState * env, TranslationBlock * tb)
2472
{
2473
    return gen_intermediate_code_internal(tb, 1, env);
2474
}
2475

    
2476
extern int ram_size;
2477

    
2478
void cpu_reset(CPUSPARCState *env)
2479
{
2480
    memset(env, 0, sizeof(*env));
2481
    tlb_flush(env, 1);
2482
    env->cwp = 0;
2483
    env->wim = 1;
2484
    env->regwptr = env->regbase + (env->cwp * 16);
2485
#if defined(CONFIG_USER_ONLY)
2486
    env->user_mode_only = 1;
2487
#else
2488
    env->psrs = 1;
2489
    env->psrps = 1;
2490
    env->pc = 0xffd00000;
2491
    env->gregs[1] = ram_size;
2492
    env->npc = env->pc + 4;
2493
#ifdef TARGET_SPARC64
2494
    env->pstate = PS_AM | PS_PRIV; // XXX: Force AM
2495
    env->version = GET_VER(env);
2496
#else
2497
    env->mmuregs[0] = (0x04 << 24); /* Impl 0, ver 4, MMU disabled */
2498
#endif
2499
#endif
2500
}
2501

    
2502
CPUSPARCState *cpu_sparc_init(void)
2503
{
2504
    CPUSPARCState *env;
2505

    
2506
    cpu_exec_init();
2507

    
2508
    if (!(env = malloc(sizeof(CPUSPARCState))))
2509
        return (NULL);
2510
    cpu_single_env = env;
2511
    cpu_reset(env);
2512
    return (env);
2513
}
2514

    
2515
#define GET_FLAG(a,b) ((env->psr & a)?b:'-')
2516

    
2517
void cpu_dump_state(CPUState *env, FILE *f, 
2518
                    int (*cpu_fprintf)(FILE *f, const char *fmt, ...),
2519
                    int flags)
2520
{
2521
    int i, x;
2522

    
2523
    cpu_fprintf(f, "pc: " TARGET_FMT_lx "  npc: " TARGET_FMT_lx "\n", env->pc, env->npc);
2524
    cpu_fprintf(f, "General Registers:\n");
2525
    for (i = 0; i < 4; i++)
2526
        cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
2527
    cpu_fprintf(f, "\n");
2528
    for (; i < 8; i++)
2529
        cpu_fprintf(f, "%%g%c: " TARGET_FMT_lx "\t", i + '0', env->gregs[i]);
2530
    cpu_fprintf(f, "\nCurrent Register Window:\n");
2531
    for (x = 0; x < 3; x++) {
2532
        for (i = 0; i < 4; i++)
2533
            cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
2534
                    (x == 0 ? 'o' : (x == 1 ? 'l' : 'i')), i,
2535
                    env->regwptr[i + x * 8]);
2536
        cpu_fprintf(f, "\n");
2537
        for (; i < 8; i++)
2538
            cpu_fprintf(f, "%%%c%d: " TARGET_FMT_lx "\t",
2539
                    (x == 0 ? 'o' : x == 1 ? 'l' : 'i'), i,
2540
                    env->regwptr[i + x * 8]);
2541
        cpu_fprintf(f, "\n");
2542
    }
2543
    cpu_fprintf(f, "\nFloating Point Registers:\n");
2544
    for (i = 0; i < 32; i++) {
2545
        if ((i & 3) == 0)
2546
            cpu_fprintf(f, "%%f%02d:", i);
2547
        cpu_fprintf(f, " %016lf", env->fpr[i]);
2548
        if ((i & 3) == 3)
2549
            cpu_fprintf(f, "\n");
2550
    }
2551
    cpu_fprintf(f, "psr: 0x%08x -> %c%c%c%c %c%c%c wim: 0x%08x\n", GET_PSR(env),
2552
            GET_FLAG(PSR_ZERO, 'Z'), GET_FLAG(PSR_OVF, 'V'),
2553
            GET_FLAG(PSR_NEG, 'N'), GET_FLAG(PSR_CARRY, 'C'),
2554
            env->psrs?'S':'-', env->psrps?'P':'-', 
2555
            env->psret?'E':'-', env->wim);
2556
    cpu_fprintf(f, "fsr: 0x%08x\n", GET_FSR32(env));
2557
}
2558

    
2559
#if defined(CONFIG_USER_ONLY)
2560
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
2561
{
2562
    return addr;
2563
}
2564

    
2565
#else
2566
extern int get_physical_address (CPUState *env, target_phys_addr_t *physical, int *prot,
2567
                                 int *access_index, target_ulong address, int rw,
2568
                                 int is_user);
2569

    
2570
target_ulong cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
2571
{
2572
    target_phys_addr_t phys_addr;
2573
    int prot, access_index;
2574

    
2575
    if (get_physical_address(env, &phys_addr, &prot, &access_index, addr, 2, 0) != 0)
2576
        return -1;
2577
    return phys_addr;
2578
}
2579
#endif
2580

    
2581
void helper_flush(target_ulong addr)
2582
{
2583
    addr &= ~7;
2584
    tb_invalidate_page_range(addr, addr + 8);
2585
}