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/*
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* pcie_aer.c
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*
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* Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
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* VA Linux Systems Japan K.K.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, see <http://www.gnu.org/licenses/>.
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*/
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#include "sysemu.h"
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#include "pci_bridge.h"
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#include "pcie.h"
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#include "msix.h"
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#include "msi.h"
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#include "pci_internals.h"
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#include "pcie_regs.h"
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//#define DEBUG_PCIE
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#ifdef DEBUG_PCIE
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# define PCIE_DPRINTF(fmt, ...) \
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fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
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#else
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# define PCIE_DPRINTF(fmt, ...) do {} while (0)
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#endif
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#define PCIE_DEV_PRINTF(dev, fmt, ...) \
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PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
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/* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
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static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
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{
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switch (status) {
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case PCI_ERR_UNC_INTN:
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case PCI_ERR_UNC_DLP:
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case PCI_ERR_UNC_SDN:
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case PCI_ERR_UNC_RX_OVER:
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case PCI_ERR_UNC_FCP:
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case PCI_ERR_UNC_MALF_TLP:
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return PCI_ERR_ROOT_CMD_FATAL_EN;
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case PCI_ERR_UNC_POISON_TLP:
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case PCI_ERR_UNC_ECRC:
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case PCI_ERR_UNC_UNSUP:
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case PCI_ERR_UNC_COMP_TIME:
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case PCI_ERR_UNC_COMP_ABORT:
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case PCI_ERR_UNC_UNX_COMP:
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case PCI_ERR_UNC_ACSV:
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case PCI_ERR_UNC_MCBTLP:
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case PCI_ERR_UNC_ATOP_EBLOCKED:
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case PCI_ERR_UNC_TLP_PRF_BLOCKED:
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return PCI_ERR_ROOT_CMD_NONFATAL_EN;
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default:
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abort();
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break;
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}
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return PCI_ERR_ROOT_CMD_FATAL_EN;
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}
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static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err)
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{
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if (aer_log->log_num == aer_log->log_max) {
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return -1;
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}
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memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err);
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aer_log->log_num++;
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return 0;
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}
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static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err)
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{
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assert(aer_log->log_num);
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*err = aer_log->log[0];
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aer_log->log_num--;
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memmove(&aer_log->log[0], &aer_log->log[1],
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aer_log->log_num * sizeof *err);
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}
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static void aer_log_clear_all_err(PCIEAERLog *aer_log)
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{
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aer_log->log_num = 0;
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}
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int pcie_aer_init(PCIDevice *dev, uint16_t offset)
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{
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PCIExpressDevice *exp;
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pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
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offset, PCI_ERR_SIZEOF);
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exp = &dev->exp;
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exp->aer_cap = offset;
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/* log_max is property */
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if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
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dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT;
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}
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/* clip down the value to avoid unreasobale memory usage */
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if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
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return -EINVAL;
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}
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dev->exp.aer_log.log = qemu_mallocz(sizeof dev->exp.aer_log.log[0] *
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dev->exp.aer_log.log_max);
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pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
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PCI_ERR_UNC_SUPPORTED);
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pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
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PCI_ERR_UNC_SEVERITY_DEFAULT);
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pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER,
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PCI_ERR_UNC_SUPPORTED);
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pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS,
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PCI_ERR_COR_STATUS);
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pci_set_long(dev->config + offset + PCI_ERR_COR_MASK,
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PCI_ERR_COR_MASK_DEFAULT);
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pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK,
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PCI_ERR_COR_SUPPORTED);
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/* capabilities and control. multiple header logging is supported */
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if (dev->exp.aer_log.log_max > 0) {
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pci_set_long(dev->config + offset + PCI_ERR_CAP,
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PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC |
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PCI_ERR_CAP_MHRC);
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pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
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PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE |
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PCI_ERR_CAP_MHRE);
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} else {
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pci_set_long(dev->config + offset + PCI_ERR_CAP,
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PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC);
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pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
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PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
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}
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switch (pcie_cap_get_type(dev)) {
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case PCI_EXP_TYPE_ROOT_PORT:
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/* this case will be set by pcie_aer_root_init() */
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/* fallthrough */
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case PCI_EXP_TYPE_DOWNSTREAM:
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case PCI_EXP_TYPE_UPSTREAM:
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pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL,
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PCI_BRIDGE_CTL_SERR);
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pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS,
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PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
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break;
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default:
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/* nothing */
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break;
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}
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return 0;
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}
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void pcie_aer_exit(PCIDevice *dev)
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{
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qemu_free(dev->exp.aer_log.log);
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}
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static void pcie_aer_update_uncor_status(PCIDevice *dev)
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{
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uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
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PCIEAERLog *aer_log = &dev->exp.aer_log;
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uint16_t i;
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for (i = 0; i < aer_log->log_num; i++) {
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pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS,
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dev->exp.aer_log.log[i].status);
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}
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}
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/*
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* pcie_aer_msg() is called recursively by
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* pcie_aer_msg_alldev(), pci_aer_msg_vbridge() and pcie_aer_msg_root_port()
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*/
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static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg);
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/*
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* return value:
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* true: error message is sent up
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* false: error message is masked
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*
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* 6.2.6 Error Message Control
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* Figure 6-3
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* all pci express devices part
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*/
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static bool
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pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
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{
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PCIDevice *parent_port;
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if (!(pcie_aer_msg_is_uncor(msg) &&
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(pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
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return false;
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}
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/* Signaled System Error
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*
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* 7.5.1.1 Command register
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* Bit 8 SERR# Enable
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*
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* When Set, this bit enables reporting of Non-fatal and Fatal
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* errors detected by the Function to the Root Complex. Note that
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* errors are reported if enabled either through this bit or through
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* the PCI Express specific bits in the Device Control register (see
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* Section 7.8.4).
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*/
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pci_word_test_and_set_mask(dev->config + PCI_STATUS,
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PCI_STATUS_SIG_SYSTEM_ERROR);
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if (!(msg->severity &
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pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) {
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return false;
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}
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/* send up error message */
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if (pci_is_express(dev) &&
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pcie_cap_get_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
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/* Root port notify system itself,
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or send the error message to root complex event collector. */
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/*
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* if root port is associated to event collector, set
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* parent_port = root complex event collector
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* For now root complex event collector isn't supported.
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*/
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parent_port = NULL;
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} else {
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parent_port = pci_bridge_get_device(dev->bus);
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}
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if (parent_port) {
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if (!pci_is_express(parent_port)) {
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/* just ignore it */
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return false;
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}
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pcie_aer_msg(parent_port, msg);
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}
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return true;
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}
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/*
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* return value:
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* true: error message is sent up
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* false: error message is masked
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*
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* 6.2.6 Error Message Control
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* Figure 6-3
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* virtual pci bridge part
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*/
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static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg)
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{
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uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL);
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if (pcie_aer_msg_is_uncor(msg)) {
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/* Received System Error */
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pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS,
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PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
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}
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if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) {
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return false;
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}
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return true;
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}
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void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector)
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{
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uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
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assert(vector < PCI_ERR_ROOT_IRQ_MAX);
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pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS,
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PCI_ERR_ROOT_IRQ);
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pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS,
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vector << PCI_ERR_ROOT_IRQ_SHIFT);
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}
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static unsigned int pcie_aer_root_get_vector(PCIDevice *dev)
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{
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uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
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uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
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return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT;
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}
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/*
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* return value:
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* true: error message is sent up
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* false: error message is masked
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*
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* 6.2.6 Error Message Control
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* Figure 6-3
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* root port part
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*/
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static bool pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
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{
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bool msg_sent;
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uint16_t cmd;
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uint8_t *aer_cap;
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uint32_t root_cmd;
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uint32_t root_status;
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bool msi_trigger;
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msg_sent = false;
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cmd = pci_get_word(dev->config + PCI_COMMAND);
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aer_cap = dev->config + dev->exp.aer_cap;
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root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
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root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
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msi_trigger = false;
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312 |
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if (cmd & PCI_COMMAND_SERR) {
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/* System Error.
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*
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* The way to report System Error is platform specific and
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* it isn't implemented in qemu right now.
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* So just discard the error for now.
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* OS which cares of aer would receive errors via
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* native aer mechanims, so this wouldn't matter.
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*/
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}
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323 |
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/* Errro Message Received: Root Error Status register */
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switch (msg->severity) {
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case PCI_ERR_ROOT_CMD_COR_EN:
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if (root_status & PCI_ERR_ROOT_COR_RCV) {
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root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
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} else {
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if (root_cmd & PCI_ERR_ROOT_CMD_COR_EN) {
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msi_trigger = true;
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}
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pci_set_word(aer_cap + PCI_ERR_ROOT_COR_SRC, msg->source_id);
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}
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root_status |= PCI_ERR_ROOT_COR_RCV;
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break;
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case PCI_ERR_ROOT_CMD_NONFATAL_EN:
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if (!(root_status & PCI_ERR_ROOT_NONFATAL_RCV) &&
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root_cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) {
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msi_trigger = true;
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341 |
}
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342 |
root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
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343 |
break;
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344 |
case PCI_ERR_ROOT_CMD_FATAL_EN:
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345 |
if (!(root_status & PCI_ERR_ROOT_FATAL_RCV) &&
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root_cmd & PCI_ERR_ROOT_CMD_FATAL_EN) {
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347 |
msi_trigger = true;
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348 |
}
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349 |
if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) {
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root_status |= PCI_ERR_ROOT_FIRST_FATAL;
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}
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root_status |= PCI_ERR_ROOT_FATAL_RCV;
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break;
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default:
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abort();
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356 |
break;
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357 |
}
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if (pcie_aer_msg_is_uncor(msg)) {
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if (root_status & PCI_ERR_ROOT_UNCOR_RCV) {
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root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
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} else {
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pci_set_word(aer_cap + PCI_ERR_ROOT_SRC, msg->source_id);
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363 |
}
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root_status |= PCI_ERR_ROOT_UNCOR_RCV;
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}
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pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status);
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367 |
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368 |
if (root_cmd & msg->severity) {
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369 |
/* 6.2.4.1.2 Interrupt Generation */
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370 |
if (pci_msi_enabled(dev)) {
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371 |
if (msi_trigger) {
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372 |
pci_msi_notify(dev, pcie_aer_root_get_vector(dev));
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373 |
}
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374 |
} else {
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375 |
qemu_set_irq(dev->irq[dev->exp.aer_intx], 1);
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376 |
}
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377 |
msg_sent = true;
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378 |
}
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379 |
return msg_sent;
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|
380 |
}
|
|
381 |
|
|
382 |
/*
|
|
383 |
* 6.2.6 Error Message Control Figure 6-3
|
|
384 |
*/
|
|
385 |
static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg)
|
|
386 |
{
|
|
387 |
uint8_t type;
|
|
388 |
bool msg_sent;
|
|
389 |
|
|
390 |
assert(pci_is_express(dev));
|
|
391 |
|
|
392 |
type = pcie_cap_get_type(dev);
|
|
393 |
if (type == PCI_EXP_TYPE_ROOT_PORT ||
|
|
394 |
type == PCI_EXP_TYPE_UPSTREAM ||
|
|
395 |
type == PCI_EXP_TYPE_DOWNSTREAM) {
|
|
396 |
msg_sent = pcie_aer_msg_vbridge(dev, msg);
|
|
397 |
if (!msg_sent) {
|
|
398 |
return;
|
|
399 |
}
|
|
400 |
}
|
|
401 |
msg_sent = pcie_aer_msg_alldev(dev, msg);
|
|
402 |
if (type == PCI_EXP_TYPE_ROOT_PORT && msg_sent) {
|
|
403 |
pcie_aer_msg_root_port(dev, msg);
|
|
404 |
}
|
|
405 |
}
|
|
406 |
|
|
407 |
static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err)
|
|
408 |
{
|
|
409 |
uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
|
|
410 |
uint8_t first_bit = ffsl(err->status) - 1;
|
|
411 |
uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
|
|
412 |
int i;
|
|
413 |
|
|
414 |
assert(err->status);
|
|
415 |
assert(err->status & (err->status - 1));
|
|
416 |
|
|
417 |
errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
|
|
418 |
errcap |= PCI_ERR_CAP_FEP(first_bit);
|
|
419 |
|
|
420 |
if (err->flags & PCIE_AER_ERR_HEADER_VALID) {
|
|
421 |
for (i = 0; i < ARRAY_SIZE(err->header); ++i) {
|
|
422 |
/* 7.10.8 Header Log Register */
|
|
423 |
uint8_t *header_log =
|
|
424 |
aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0];
|
|
425 |
cpu_to_be32wu((uint32_t*)header_log, err->header[i]);
|
|
426 |
}
|
|
427 |
} else {
|
|
428 |
assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT));
|
|
429 |
memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
|
|
430 |
}
|
|
431 |
|
|
432 |
if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) &&
|
|
433 |
(pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
|
|
434 |
PCI_EXP_DEVCAP2_EETLPP)) {
|
|
435 |
for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) {
|
|
436 |
/* 7.10.12 tlp prefix log register */
|
|
437 |
uint8_t *prefix_log =
|
|
438 |
aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0];
|
|
439 |
cpu_to_be32wu((uint32_t*)prefix_log, err->prefix[i]);
|
|
440 |
}
|
|
441 |
errcap |= PCI_ERR_CAP_TLP;
|
|
442 |
} else {
|
|
443 |
memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0,
|
|
444 |
PCI_ERR_TLP_PREFIX_LOG_SIZE);
|
|
445 |
}
|
|
446 |
pci_set_long(aer_cap + PCI_ERR_CAP, errcap);
|
|
447 |
}
|
|
448 |
|
|
449 |
static void pcie_aer_clear_log(PCIDevice *dev)
|
|
450 |
{
|
|
451 |
uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
|
|
452 |
|
|
453 |
pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP,
|
|
454 |
PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
|
|
455 |
|
|
456 |
memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
|
|
457 |
memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE);
|
|
458 |
}
|
|
459 |
|
|
460 |
static void pcie_aer_clear_error(PCIDevice *dev)
|
|
461 |
{
|
|
462 |
uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
|
|
463 |
uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
|
|
464 |
PCIEAERLog *aer_log = &dev->exp.aer_log;
|
|
465 |
PCIEAERErr err;
|
|
466 |
|
|
467 |
if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) {
|
|
468 |
pcie_aer_clear_log(dev);
|
|
469 |
return;
|
|
470 |
}
|
|
471 |
|
|
472 |
/*
|
|
473 |
* If more errors are queued, set corresponding bits in uncorrectable
|
|
474 |
* error status.
|
|
475 |
* We emulate uncorrectable error status register as W1CS.
|
|
476 |
* So set bit in uncorrectable error status here again for multiple
|
|
477 |
* error recording support.
|
|
478 |
*
|
|
479 |
* 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability)
|
|
480 |
*/
|
|
481 |
pcie_aer_update_uncor_status(dev);
|
|
482 |
|
|
483 |
aer_log_del_err(aer_log, &err);
|
|
484 |
pcie_aer_update_log(dev, &err);
|
|
485 |
}
|
|
486 |
|
|
487 |
static int pcie_aer_record_error(PCIDevice *dev,
|
|
488 |
const PCIEAERErr *err)
|
|
489 |
{
|
|
490 |
uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
|
|
491 |
uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
|
|
492 |
int fep = PCI_ERR_CAP_FEP(errcap);
|
|
493 |
|
|
494 |
assert(err->status);
|
|
495 |
assert(err->status & (err->status - 1));
|
|
496 |
|
|
497 |
if (errcap & PCI_ERR_CAP_MHRE &&
|
|
498 |
(pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) {
|
|
499 |
/* Not first error. queue error */
|
|
500 |
if (aer_log_add_err(&dev->exp.aer_log, err) < 0) {
|
|
501 |
/* overflow */
|
|
502 |
return -1;
|
|
503 |
}
|
|
504 |
return 0;
|
|
505 |
}
|
|
506 |
|
|
507 |
pcie_aer_update_log(dev, err);
|
|
508 |
return 0;
|
|
509 |
}
|
|
510 |
|
|
511 |
typedef struct PCIEAERInject {
|
|
512 |
PCIDevice *dev;
|
|
513 |
uint8_t *aer_cap;
|
|
514 |
const PCIEAERErr *err;
|
|
515 |
uint16_t devctl;
|
|
516 |
uint16_t devsta;
|
|
517 |
uint32_t error_status;
|
|
518 |
bool unsupported_request;
|
|
519 |
bool log_overflow;
|
|
520 |
PCIEAERMsg msg;
|
|
521 |
} PCIEAERInject;
|
|
522 |
|
|
523 |
static bool pcie_aer_inject_cor_error(PCIEAERInject *inj,
|
|
524 |
uint32_t uncor_status,
|
|
525 |
bool is_advisory_nonfatal)
|
|
526 |
{
|
|
527 |
PCIDevice *dev = inj->dev;
|
|
528 |
|
|
529 |
inj->devsta |= PCI_EXP_DEVSTA_CED;
|
|
530 |
if (inj->unsupported_request) {
|
|
531 |
inj->devsta |= PCI_EXP_DEVSTA_URD;
|
|
532 |
}
|
|
533 |
pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
|
|
534 |
|
|
535 |
if (inj->aer_cap) {
|
|
536 |
uint32_t mask;
|
|
537 |
pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS,
|
|
538 |
inj->error_status);
|
|
539 |
mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK);
|
|
540 |
if (mask & inj->error_status) {
|
|
541 |
return false;
|
|
542 |
}
|
|
543 |
if (is_advisory_nonfatal) {
|
|
544 |
uint32_t uncor_mask =
|
|
545 |
pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
|
|
546 |
if (!(uncor_mask & uncor_status)) {
|
|
547 |
inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
|
|
548 |
}
|
|
549 |
pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
|
|
550 |
uncor_status);
|
|
551 |
}
|
|
552 |
}
|
|
553 |
|
|
554 |
if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) {
|
|
555 |
return false;
|
|
556 |
}
|
|
557 |
if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) {
|
|
558 |
return false;
|
|
559 |
}
|
|
560 |
|
|
561 |
inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN;
|
|
562 |
return true;
|
|
563 |
}
|
|
564 |
|
|
565 |
static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal)
|
|
566 |
{
|
|
567 |
PCIDevice *dev = inj->dev;
|
|
568 |
uint16_t cmd;
|
|
569 |
|
|
570 |
if (is_fatal) {
|
|
571 |
inj->devsta |= PCI_EXP_DEVSTA_FED;
|
|
572 |
} else {
|
|
573 |
inj->devsta |= PCI_EXP_DEVSTA_NFED;
|
|
574 |
}
|
|
575 |
if (inj->unsupported_request) {
|
|
576 |
inj->devsta |= PCI_EXP_DEVSTA_URD;
|
|
577 |
}
|
|
578 |
pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
|
|
579 |
|
|
580 |
if (inj->aer_cap) {
|
|
581 |
uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
|
|
582 |
if (mask & inj->error_status) {
|
|
583 |
pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
|
|
584 |
inj->error_status);
|
|
585 |
return false;
|
|
586 |
}
|
|
587 |
|
|
588 |
inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
|
|
589 |
pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
|
|
590 |
inj->error_status);
|
|
591 |
}
|
|
592 |
|
|
593 |
cmd = pci_get_word(dev->config + PCI_COMMAND);
|
|
594 |
if (inj->unsupported_request &&
|
|
595 |
!(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) {
|
|
596 |
return false;
|
|
597 |
}
|
|
598 |
if (is_fatal) {
|
|
599 |
if (!((cmd & PCI_COMMAND_SERR) ||
|
|
600 |
(inj->devctl & PCI_EXP_DEVCTL_FERE))) {
|
|
601 |
return false;
|
|
602 |
}
|
|
603 |
inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN;
|
|
604 |
} else {
|
|
605 |
if (!((cmd & PCI_COMMAND_SERR) ||
|
|
606 |
(inj->devctl & PCI_EXP_DEVCTL_NFERE))) {
|
|
607 |
return false;
|
|
608 |
}
|
|
609 |
inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN;
|
|
610 |
}
|
|
611 |
return true;
|
|
612 |
}
|
|
613 |
|
|
614 |
/*
|
|
615 |
* non-Function specific error must be recorded in all functions.
|
|
616 |
* It is the responsibility of the caller of this function.
|
|
617 |
* It is also caller's responsiblity to determine which function should
|
|
618 |
* report the rerror.
|
|
619 |
*
|
|
620 |
* 6.2.4 Error Logging
|
|
621 |
* 6.2.5 Sqeunce of Device Error Signaling and Logging Operations
|
|
622 |
* table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging
|
|
623 |
* Operations
|
|
624 |
*/
|
|
625 |
int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err)
|
|
626 |
{
|
|
627 |
uint8_t *aer_cap = NULL;
|
|
628 |
uint16_t devctl = 0;
|
|
629 |
uint16_t devsta = 0;
|
|
630 |
uint32_t error_status = err->status;
|
|
631 |
PCIEAERInject inj;
|
|
632 |
|
|
633 |
if (!pci_is_express(dev)) {
|
|
634 |
return -ENOSYS;
|
|
635 |
}
|
|
636 |
|
|
637 |
if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
|
|
638 |
error_status &= PCI_ERR_COR_SUPPORTED;
|
|
639 |
} else {
|
|
640 |
error_status &= PCI_ERR_UNC_SUPPORTED;
|
|
641 |
}
|
|
642 |
|
|
643 |
/* invalid status bit. one and only one bit must be set */
|
|
644 |
if (!error_status || (error_status & (error_status - 1))) {
|
|
645 |
return -EINVAL;
|
|
646 |
}
|
|
647 |
|
|
648 |
if (dev->exp.aer_cap) {
|
|
649 |
uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
|
|
650 |
aer_cap = dev->config + dev->exp.aer_cap;
|
|
651 |
devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL);
|
|
652 |
devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA);
|
|
653 |
}
|
|
654 |
|
|
655 |
inj.dev = dev;
|
|
656 |
inj.aer_cap = aer_cap;
|
|
657 |
inj.err = err;
|
|
658 |
inj.devctl = devctl;
|
|
659 |
inj.devsta = devsta;
|
|
660 |
inj.error_status = error_status;
|
|
661 |
inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) &&
|
|
662 |
err->status == PCI_ERR_UNC_UNSUP;
|
|
663 |
inj.log_overflow = false;
|
|
664 |
|
|
665 |
if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
|
|
666 |
if (!pcie_aer_inject_cor_error(&inj, 0, false)) {
|
|
667 |
return 0;
|
|
668 |
}
|
|
669 |
} else {
|
|
670 |
bool is_fatal =
|
|
671 |
pcie_aer_uncor_default_severity(error_status) ==
|
|
672 |
PCI_ERR_ROOT_CMD_FATAL_EN;
|
|
673 |
if (aer_cap) {
|
|
674 |
is_fatal =
|
|
675 |
error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER);
|
|
676 |
}
|
|
677 |
if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) {
|
|
678 |
inj.error_status = PCI_ERR_COR_ADV_NONFATAL;
|
|
679 |
if (!pcie_aer_inject_cor_error(&inj, error_status, true)) {
|
|
680 |
return 0;
|
|
681 |
}
|
|
682 |
} else {
|
|
683 |
if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) {
|
|
684 |
return 0;
|
|
685 |
}
|
|
686 |
}
|
|
687 |
}
|
|
688 |
|
|
689 |
/* send up error message */
|
|
690 |
inj.msg.source_id = err->source_id;
|
|
691 |
pcie_aer_msg(dev, &inj.msg);
|
|
692 |
|
|
693 |
if (inj.log_overflow) {
|
|
694 |
PCIEAERErr header_log_overflow = {
|
|
695 |
.status = PCI_ERR_COR_HL_OVERFLOW,
|
|
696 |
.flags = PCIE_AER_ERR_IS_CORRECTABLE,
|
|
697 |
};
|
|
698 |
int ret = pcie_aer_inject_error(dev, &header_log_overflow);
|
|
699 |
assert(!ret);
|
|
700 |
}
|
|
701 |
return 0;
|
|
702 |
}
|
|
703 |
|
|
704 |
void pcie_aer_write_config(PCIDevice *dev,
|
|
705 |
uint32_t addr, uint32_t val, int len)
|
|
706 |
{
|
|
707 |
uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
|
|
708 |
uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
|
|
709 |
uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap);
|
|
710 |
uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS);
|
|
711 |
|
|
712 |
/* uncorrectable error */
|
|
713 |
if (!(uncorsta & first_error)) {
|
|
714 |
/* the bit that corresponds to the first error is cleared */
|
|
715 |
pcie_aer_clear_error(dev);
|
|
716 |
} else if (errcap & PCI_ERR_CAP_MHRE) {
|
|
717 |
/* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared
|
|
718 |
* nothing should happen. So we have to revert the modification to
|
|
719 |
* the register.
|
|
720 |
*/
|
|
721 |
pcie_aer_update_uncor_status(dev);
|
|
722 |
} else {
|
|
723 |
/* capability & control
|
|
724 |
* PCI_ERR_CAP_MHRE might be cleared, so clear of header log.
|
|
725 |
*/
|
|
726 |
aer_log_clear_all_err(&dev->exp.aer_log);
|
|
727 |
}
|
|
728 |
}
|
|
729 |
|
|
730 |
void pcie_aer_root_init(PCIDevice *dev)
|
|
731 |
{
|
|
732 |
uint16_t pos = dev->exp.aer_cap;
|
|
733 |
|
|
734 |
pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND,
|
|
735 |
PCI_ERR_ROOT_CMD_EN_MASK);
|
|
736 |
pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS,
|
|
737 |
PCI_ERR_ROOT_STATUS_REPORT_MASK);
|
|
738 |
}
|
|
739 |
|
|
740 |
void pcie_aer_root_reset(PCIDevice *dev)
|
|
741 |
{
|
|
742 |
uint8_t* aer_cap = dev->config + dev->exp.aer_cap;
|
|
743 |
|
|
744 |
pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0);
|
|
745 |
|
|
746 |
/*
|
|
747 |
* Advanced Error Interrupt Message Number in Root Error Status Register
|
|
748 |
* must be updated by chip dependent code because it's chip dependent
|
|
749 |
* which number is used.
|
|
750 |
*/
|
|
751 |
}
|
|
752 |
|
|
753 |
static bool pcie_aer_root_does_trigger(uint32_t cmd, uint32_t status)
|
|
754 |
{
|
|
755 |
return
|
|
756 |
((cmd & PCI_ERR_ROOT_CMD_COR_EN) && (status & PCI_ERR_ROOT_COR_RCV)) ||
|
|
757 |
((cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
|
|
758 |
(status & PCI_ERR_ROOT_NONFATAL_RCV)) ||
|
|
759 |
((cmd & PCI_ERR_ROOT_CMD_FATAL_EN) &&
|
|
760 |
(status & PCI_ERR_ROOT_FATAL_RCV));
|
|
761 |
}
|
|
762 |
|
|
763 |
void pcie_aer_root_write_config(PCIDevice *dev,
|
|
764 |
uint32_t addr, uint32_t val, int len,
|
|
765 |
uint32_t root_cmd_prev)
|
|
766 |
{
|
|
767 |
uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
|
|
768 |
|
|
769 |
/* root command register */
|
|
770 |
uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
|
|
771 |
if (root_cmd & PCI_ERR_ROOT_CMD_EN_MASK) {
|
|
772 |
/* 6.2.4.1.2 Interrupt Generation */
|
|
773 |
|
|
774 |
/* 0 -> 1 */
|
|
775 |
uint32_t root_cmd_set = (root_cmd_prev ^ root_cmd) & root_cmd;
|
|
776 |
uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
|
|
777 |
|
|
778 |
if (pci_msi_enabled(dev)) {
|
|
779 |
if (pcie_aer_root_does_trigger(root_cmd_set, root_status)) {
|
|
780 |
pci_msi_notify(dev, pcie_aer_root_get_vector(dev));
|
|
781 |
}
|
|
782 |
} else {
|
|
783 |
int int_level = pcie_aer_root_does_trigger(root_cmd, root_status);
|
|
784 |
qemu_set_irq(dev->irq[dev->exp.aer_intx], int_level);
|
|
785 |
}
|
|
786 |
}
|
|
787 |
}
|
|
788 |
|
|
789 |
static const VMStateDescription vmstate_pcie_aer_err = {
|
|
790 |
.name = "PCIE_AER_ERROR",
|
|
791 |
.version_id = 1,
|
|
792 |
.minimum_version_id = 1,
|
|
793 |
.minimum_version_id_old = 1,
|
|
794 |
.fields = (VMStateField[]) {
|
|
795 |
VMSTATE_UINT32(status, PCIEAERErr),
|
|
796 |
VMSTATE_UINT16(source_id, PCIEAERErr),
|
|
797 |
VMSTATE_UINT16(flags, PCIEAERErr),
|
|
798 |
VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4),
|
|
799 |
VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4),
|
|
800 |
VMSTATE_END_OF_LIST()
|
|
801 |
}
|
|
802 |
};
|
|
803 |
|
|
804 |
#define VMSTATE_PCIE_AER_ERRS(_field, _state, _field_num, _vmsd, _type) { \
|
|
805 |
.name = (stringify(_field)), \
|
|
806 |
.version_id = 0, \
|
|
807 |
.num_offset = vmstate_offset_value(_state, _field_num, uint16_t), \
|
|
808 |
.size = sizeof(_type), \
|
|
809 |
.vmsd = &(_vmsd), \
|
|
810 |
.flags = VMS_POINTER | VMS_VARRAY_UINT16 | VMS_STRUCT, \
|
|
811 |
.offset = vmstate_offset_pointer(_state, _field, _type), \
|
|
812 |
}
|
|
813 |
|
|
814 |
const VMStateDescription vmstate_pcie_aer_log = {
|
|
815 |
.name = "PCIE_AER_ERROR_LOG",
|
|
816 |
.version_id = 1,
|
|
817 |
.minimum_version_id = 1,
|
|
818 |
.minimum_version_id_old = 1,
|
|
819 |
.fields = (VMStateField[]) {
|
|
820 |
VMSTATE_UINT16(log_num, PCIEAERLog),
|
|
821 |
VMSTATE_UINT16(log_max, PCIEAERLog),
|
|
822 |
VMSTATE_PCIE_AER_ERRS(log, PCIEAERLog, log_num,
|
|
823 |
vmstate_pcie_aer_err, PCIEAERErr),
|
|
824 |
VMSTATE_END_OF_LIST()
|
|
825 |
}
|
|
826 |
};
|
|
827 |
|