Revision 3504fe17
| b/hw/dma.c | ||
|---|---|---|
| 136 | 136 |
return (val >> (ncont + (ff << 3))) & 0xff; |
| 137 | 137 |
} |
| 138 | 138 |
|
| 139 |
static void write_chan (uint32_t nport, int size, uint32_t data)
|
|
| 139 |
static void write_chan (CPUState *env, uint32_t nport, uint32_t data)
|
|
| 140 | 140 |
{
|
| 141 | 141 |
int ncont, ichan, nreg; |
| 142 | 142 |
struct dma_regs *r; |
| ... | ... | |
| 146 | 146 |
nreg = (nport >> ncont) & 1; |
| 147 | 147 |
r = dma_controllers[ncont].regs + ichan; |
| 148 | 148 |
|
| 149 |
if (2 == size) {
|
|
| 150 |
r->base[nreg] = data;
|
|
| 149 |
if (getff (ncont)) {
|
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| 150 |
r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00);
|
|
| 151 | 151 |
init_chan (ncont, ichan); |
| 152 |
} else {
|
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| 153 |
r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
|
| 152 | 154 |
} |
| 153 |
else {
|
|
| 154 |
if (getff (ncont)) {
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| 155 |
r->base[nreg] = (r->base[nreg] & 0xff) | ((data << 8) & 0xff00); |
|
| 156 |
init_chan (ncont, ichan); |
|
| 157 |
} |
|
| 158 |
else {
|
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| 159 |
r->base[nreg] = (r->base[nreg] & 0xff00) | (data & 0xff); |
|
| 160 |
} |
|
| 161 |
} |
|
| 162 |
} |
|
| 163 |
static void write_chanb (CPUState *env, uint32_t nport, uint32_t data) |
|
| 164 |
{
|
|
| 165 |
write_chan (nport, 1, data); |
|
| 166 |
} |
|
| 167 |
|
|
| 168 |
static void write_chanw (CPUState *env, uint32_t nport, uint32_t data) |
|
| 169 |
{
|
|
| 170 |
write_chan (nport, 2, data); |
|
| 171 | 155 |
} |
| 172 | 156 |
|
| 173 | 157 |
static void write_cont (CPUState *env, uint32_t nport, uint32_t data) |
| ... | ... | |
| 370 | 354 |
int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 };
|
| 371 | 355 |
|
| 372 | 356 |
for (i = 0; i < 8; i++) {
|
| 373 |
register_ioport_write (i, 1, write_chanb, 1); |
|
| 374 |
register_ioport_write (i, 1, write_chanw, 2); |
|
| 357 |
register_ioport_write (i, 1, write_chan, 1); |
|
| 375 | 358 |
|
| 376 |
register_ioport_write (0xc0 + (i << 1), 1, write_chanb, 1); |
|
| 377 |
register_ioport_write (0xc0 + (i << 1), 1, write_chanw, 2); |
|
| 359 |
register_ioport_write (0xc0 + (i << 1), 1, write_chan, 1); |
|
| 378 | 360 |
|
| 379 | 361 |
register_ioport_read (i, 1, read_chan, 1); |
| 380 |
register_ioport_read (0xc0 + (i << 1), 1, read_chan, 2);
|
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| 362 |
register_ioport_read (0xc0 + (i << 1), 1, read_chan, 1);
|
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| 381 | 363 |
} |
| 382 | 364 |
|
| 383 | 365 |
for (i = 0; i < LENOFA (page_port_list); i++) {
|
| ... | ... | |
| 390 | 372 |
register_ioport_write (0xd0 + (i << 1), 1, write_cont, 1); |
| 391 | 373 |
} |
| 392 | 374 |
|
| 393 |
write_cont (NULL, 0xd, 0); |
|
| 394 |
write_cont (NULL, 0xdd, 0);
|
|
| 375 |
write_cont (NULL, 0x0d, 0);
|
|
| 376 |
write_cont (NULL, 0xda, 0);
|
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| 395 | 377 |
} |
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