Revision 351326a6
| b/target-m68k/translate.c | ||
|---|---|---|
| 171 | 171 |
static void disas_##name (DisasContext *s, uint16_t insn) |
| 172 | 172 |
#endif |
| 173 | 173 |
|
| 174 |
/* FIXME: Remove this. */ |
|
| 175 |
#define gen_im32(val) tcg_const_i32(val) |
|
| 176 |
|
|
| 177 | 174 |
/* Generate a load from the specified address. Narrow values are |
| 178 | 175 |
sign extended to full register width. */ |
| 179 | 176 |
static inline TCGv gen_load(DisasContext * s, int opsize, TCGv addr, int sign) |
| ... | ... | |
| 339 | 336 |
if ((ext & 0x80) == 0) {
|
| 340 | 337 |
/* base not suppressed */ |
| 341 | 338 |
if (IS_NULL_QREG(base)) {
|
| 342 |
base = gen_im32(offset + bd);
|
|
| 339 |
base = tcg_const_i32(offset + bd);
|
|
| 343 | 340 |
bd = 0; |
| 344 | 341 |
} |
| 345 | 342 |
if (!IS_NULL_QREG(add)) {
|
| ... | ... | |
| 355 | 352 |
add = tmp; |
| 356 | 353 |
} |
| 357 | 354 |
} else {
|
| 358 |
add = gen_im32(bd);
|
|
| 355 |
add = tcg_const_i32(bd);
|
|
| 359 | 356 |
} |
| 360 | 357 |
if ((ext & 3) != 0) {
|
| 361 | 358 |
/* memory indirect */ |
| ... | ... | |
| 536 | 533 |
case 0: /* Absolute short. */ |
| 537 | 534 |
offset = ldsw_code(s->pc); |
| 538 | 535 |
s->pc += 2; |
| 539 |
return gen_im32(offset);
|
|
| 536 |
return tcg_const_i32(offset);
|
|
| 540 | 537 |
case 1: /* Absolute long. */ |
| 541 | 538 |
offset = read_im32(s); |
| 542 |
return gen_im32(offset);
|
|
| 539 |
return tcg_const_i32(offset);
|
|
| 543 | 540 |
case 2: /* pc displacement */ |
| 544 | 541 |
offset = s->pc; |
| 545 | 542 |
offset += ldsw_code(s->pc); |
| 546 | 543 |
s->pc += 2; |
| 547 |
return gen_im32(offset);
|
|
| 544 |
return tcg_const_i32(offset);
|
|
| 548 | 545 |
case 3: /* pc index+displacement. */ |
| 549 | 546 |
return gen_lea_indexed(s, opsize, NULL_QREG); |
| 550 | 547 |
case 4: /* Immediate. */ |
| ... | ... | |
| 1209 | 1206 |
break; |
| 1210 | 1207 |
case 2: /* subi */ |
| 1211 | 1208 |
tcg_gen_mov_i32(dest, src1); |
| 1212 |
gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im));
|
|
| 1209 |
gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
|
|
| 1213 | 1210 |
tcg_gen_subi_i32(dest, dest, im); |
| 1214 |
gen_update_cc_add(dest, gen_im32(im));
|
|
| 1211 |
gen_update_cc_add(dest, tcg_const_i32(im));
|
|
| 1215 | 1212 |
s->cc_op = CC_OP_SUB; |
| 1216 | 1213 |
break; |
| 1217 | 1214 |
case 3: /* addi */ |
| 1218 | 1215 |
tcg_gen_mov_i32(dest, src1); |
| 1219 | 1216 |
tcg_gen_addi_i32(dest, dest, im); |
| 1220 |
gen_update_cc_add(dest, gen_im32(im));
|
|
| 1221 |
gen_helper_xflag_lt(QREG_CC_X, dest, gen_im32(im));
|
|
| 1217 |
gen_update_cc_add(dest, tcg_const_i32(im));
|
|
| 1218 |
gen_helper_xflag_lt(QREG_CC_X, dest, tcg_const_i32(im));
|
|
| 1222 | 1219 |
s->cc_op = CC_OP_ADD; |
| 1223 | 1220 |
break; |
| 1224 | 1221 |
case 5: /* eori */ |
| ... | ... | |
| 1228 | 1225 |
case 6: /* cmpi */ |
| 1229 | 1226 |
tcg_gen_mov_i32(dest, src1); |
| 1230 | 1227 |
tcg_gen_subi_i32(dest, dest, im); |
| 1231 |
gen_update_cc_add(dest, gen_im32(im));
|
|
| 1228 |
gen_update_cc_add(dest, tcg_const_i32(im));
|
|
| 1232 | 1229 |
s->cc_op = CC_OP_SUB; |
| 1233 | 1230 |
break; |
| 1234 | 1231 |
default: |
| ... | ... | |
| 1324 | 1321 |
default: |
| 1325 | 1322 |
abort(); |
| 1326 | 1323 |
} |
| 1327 |
DEST_EA(insn, opsize, gen_im32(0), NULL);
|
|
| 1328 |
gen_logic_cc(s, gen_im32(0));
|
|
| 1324 |
DEST_EA(insn, opsize, tcg_const_i32(0), NULL);
|
|
| 1325 |
gen_logic_cc(s, tcg_const_i32(0));
|
|
| 1329 | 1326 |
} |
| 1330 | 1327 |
|
| 1331 | 1328 |
static TCGv gen_get_ccr(DisasContext *s) |
| ... | ... | |
| 1589 | 1586 |
} |
| 1590 | 1587 |
if ((insn & 0x40) == 0) {
|
| 1591 | 1588 |
/* jsr */ |
| 1592 |
gen_push(s, gen_im32(s->pc));
|
|
| 1589 |
gen_push(s, tcg_const_i32(s->pc));
|
|
| 1593 | 1590 |
} |
| 1594 | 1591 |
gen_jmp(s, tmp); |
| 1595 | 1592 |
} |
| ... | ... | |
| 1617 | 1614 |
tcg_gen_addi_i32(dest, dest, val); |
| 1618 | 1615 |
} |
| 1619 | 1616 |
} else {
|
| 1620 |
src2 = gen_im32(val);
|
|
| 1617 |
src2 = tcg_const_i32(val);
|
|
| 1621 | 1618 |
if (insn & 0x0100) {
|
| 1622 | 1619 |
gen_helper_xflag_lt(QREG_CC_X, dest, src2); |
| 1623 | 1620 |
tcg_gen_subi_i32(dest, dest, val); |
| ... | ... | |
| 1666 | 1663 |
} |
| 1667 | 1664 |
if (op == 1) {
|
| 1668 | 1665 |
/* bsr */ |
| 1669 |
gen_push(s, gen_im32(s->pc));
|
|
| 1666 |
gen_push(s, tcg_const_i32(s->pc));
|
|
| 1670 | 1667 |
} |
| 1671 | 1668 |
gen_flush_cc_op(s); |
| 1672 | 1669 |
if (op > 1) {
|
| ... | ... | |
| 1757 | 1754 |
val = (insn >> 9) & 7; |
| 1758 | 1755 |
if (val == 0) |
| 1759 | 1756 |
val = -1; |
| 1760 |
src = gen_im32(val);
|
|
| 1757 |
src = tcg_const_i32(val);
|
|
| 1761 | 1758 |
gen_logic_cc(s, src); |
| 1762 | 1759 |
DEST_EA(insn, OS_LONG, src, NULL); |
| 1763 | 1760 |
} |
| ... | ... | |
| 1883 | 1880 |
tmp = (insn >> 9) & 7; |
| 1884 | 1881 |
if (tmp == 0) |
| 1885 | 1882 |
tmp = 8; |
| 1886 |
shift = gen_im32(tmp);
|
|
| 1883 |
shift = tcg_const_i32(tmp);
|
|
| 1887 | 1884 |
/* No need to flush flags becuse we know we will set C flag. */ |
| 1888 | 1885 |
if (insn & 0x100) {
|
| 1889 | 1886 |
gen_helper_shl_cc(reg, cpu_env, reg, shift); |
| ... | ... | |
| 2191 | 2188 |
switch ((ext >> 10) & 7) {
|
| 2192 | 2189 |
case 4: /* FPCR */ |
| 2193 | 2190 |
/* Not implemented. Always return zero. */ |
| 2194 |
tmp32 = gen_im32(0);
|
|
| 2191 |
tmp32 = tcg_const_i32(0);
|
|
| 2195 | 2192 |
break; |
| 2196 | 2193 |
case 1: /* FPIAR */ |
| 2197 | 2194 |
case 2: /* FPSR */ |
| ... | ... | |
| 2592 | 2589 |
/* Skip the accumulate if the value is already saturated. */ |
| 2593 | 2590 |
l1 = gen_new_label(); |
| 2594 | 2591 |
tmp = tcg_temp_new(); |
| 2595 |
gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
|
|
| 2592 |
gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
|
|
| 2596 | 2593 |
gen_op_jmp_nz32(tmp, l1); |
| 2597 | 2594 |
} |
| 2598 | 2595 |
#endif |
| ... | ... | |
| 2626 | 2623 |
/* Skip the accumulate if the value is already saturated. */ |
| 2627 | 2624 |
l1 = gen_new_label(); |
| 2628 | 2625 |
tmp = tcg_temp_new(); |
| 2629 |
gen_op_and32(tmp, QREG_MACSR, gen_im32(MACSR_PAV0 << acc));
|
|
| 2626 |
gen_op_and32(tmp, QREG_MACSR, tcg_const_i32(MACSR_PAV0 << acc));
|
|
| 2630 | 2627 |
gen_op_jmp_nz32(tmp, l1); |
| 2631 | 2628 |
} |
| 2632 | 2629 |
#endif |
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