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1 | 4c9649a9 | j_mayer | /*
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2 | 4c9649a9 | j_mayer | * Alpha emulation cpu definitions for qemu.
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3 | 5fafdf24 | ths | *
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4 | 4c9649a9 | j_mayer | * Copyright (c) 2007 Jocelyn Mayer
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5 | 4c9649a9 | j_mayer | *
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6 | 4c9649a9 | j_mayer | * This library is free software; you can redistribute it and/or
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7 | 4c9649a9 | j_mayer | * modify it under the terms of the GNU Lesser General Public
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8 | 4c9649a9 | j_mayer | * License as published by the Free Software Foundation; either
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9 | 4c9649a9 | j_mayer | * version 2 of the License, or (at your option) any later version.
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10 | 4c9649a9 | j_mayer | *
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11 | 4c9649a9 | j_mayer | * This library is distributed in the hope that it will be useful,
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12 | 4c9649a9 | j_mayer | * but WITHOUT ANY WARRANTY; without even the implied warranty of
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13 | 4c9649a9 | j_mayer | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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14 | 4c9649a9 | j_mayer | * Lesser General Public License for more details.
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15 | 4c9649a9 | j_mayer | *
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16 | 4c9649a9 | j_mayer | * You should have received a copy of the GNU Lesser General Public
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17 | 8167ee88 | Blue Swirl | * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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18 | 4c9649a9 | j_mayer | */
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19 | 4c9649a9 | j_mayer | |
20 | 4c9649a9 | j_mayer | #if !defined (__CPU_ALPHA_H__)
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21 | 4c9649a9 | j_mayer | #define __CPU_ALPHA_H__
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22 | 4c9649a9 | j_mayer | |
23 | 4c9649a9 | j_mayer | #include "config.h" |
24 | 4c9649a9 | j_mayer | |
25 | 4c9649a9 | j_mayer | #define TARGET_LONG_BITS 64 |
26 | 4c9649a9 | j_mayer | |
27 | c2764719 | pbrook | #define CPUState struct CPUAlphaState |
28 | c2764719 | pbrook | |
29 | 4c9649a9 | j_mayer | #include "cpu-defs.h" |
30 | 4c9649a9 | j_mayer | |
31 | 4c9649a9 | j_mayer | #include <setjmp.h> |
32 | 4c9649a9 | j_mayer | |
33 | 4c9649a9 | j_mayer | #include "softfloat.h" |
34 | 4c9649a9 | j_mayer | |
35 | 4c9649a9 | j_mayer | #define TARGET_HAS_ICE 1 |
36 | 4c9649a9 | j_mayer | |
37 | f071b4d3 | j_mayer | #define ELF_MACHINE EM_ALPHA
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38 | 4c9649a9 | j_mayer | |
39 | 4c9649a9 | j_mayer | #define ICACHE_LINE_SIZE 32 |
40 | 4c9649a9 | j_mayer | #define DCACHE_LINE_SIZE 32 |
41 | 4c9649a9 | j_mayer | |
42 | b09d9d46 | aurel32 | #define TARGET_PAGE_BITS 13 |
43 | 4c9649a9 | j_mayer | |
44 | 52705890 | Richard Henderson | /* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44. */
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45 | 52705890 | Richard Henderson | #define TARGET_PHYS_ADDR_SPACE_BITS 44 |
46 | 52705890 | Richard Henderson | #define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS) |
47 | 4c9649a9 | j_mayer | |
48 | 4c9649a9 | j_mayer | /* Alpha major type */
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49 | 4c9649a9 | j_mayer | enum {
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50 | 4c9649a9 | j_mayer | ALPHA_EV3 = 1,
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51 | 4c9649a9 | j_mayer | ALPHA_EV4 = 2,
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52 | 4c9649a9 | j_mayer | ALPHA_SIM = 3,
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53 | 4c9649a9 | j_mayer | ALPHA_LCA = 4,
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54 | 4c9649a9 | j_mayer | ALPHA_EV5 = 5, /* 21164 */ |
55 | 4c9649a9 | j_mayer | ALPHA_EV45 = 6, /* 21064A */ |
56 | 4c9649a9 | j_mayer | ALPHA_EV56 = 7, /* 21164A */ |
57 | 4c9649a9 | j_mayer | }; |
58 | 4c9649a9 | j_mayer | |
59 | 4c9649a9 | j_mayer | /* EV4 minor type */
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60 | 4c9649a9 | j_mayer | enum {
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61 | 4c9649a9 | j_mayer | ALPHA_EV4_2 = 0,
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62 | 4c9649a9 | j_mayer | ALPHA_EV4_3 = 1,
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63 | 4c9649a9 | j_mayer | }; |
64 | 4c9649a9 | j_mayer | |
65 | 4c9649a9 | j_mayer | /* LCA minor type */
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66 | 4c9649a9 | j_mayer | enum {
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67 | 4c9649a9 | j_mayer | ALPHA_LCA_1 = 1, /* 21066 */ |
68 | 4c9649a9 | j_mayer | ALPHA_LCA_2 = 2, /* 20166 */ |
69 | 4c9649a9 | j_mayer | ALPHA_LCA_3 = 3, /* 21068 */ |
70 | 4c9649a9 | j_mayer | ALPHA_LCA_4 = 4, /* 21068 */ |
71 | 4c9649a9 | j_mayer | ALPHA_LCA_5 = 5, /* 21066A */ |
72 | 4c9649a9 | j_mayer | ALPHA_LCA_6 = 6, /* 21068A */ |
73 | 4c9649a9 | j_mayer | }; |
74 | 4c9649a9 | j_mayer | |
75 | 4c9649a9 | j_mayer | /* EV5 minor type */
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76 | 4c9649a9 | j_mayer | enum {
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77 | 4c9649a9 | j_mayer | ALPHA_EV5_1 = 1, /* Rev BA, CA */ |
78 | 4c9649a9 | j_mayer | ALPHA_EV5_2 = 2, /* Rev DA, EA */ |
79 | 4c9649a9 | j_mayer | ALPHA_EV5_3 = 3, /* Pass 3 */ |
80 | 4c9649a9 | j_mayer | ALPHA_EV5_4 = 4, /* Pass 3.2 */ |
81 | 4c9649a9 | j_mayer | ALPHA_EV5_5 = 5, /* Pass 4 */ |
82 | 4c9649a9 | j_mayer | }; |
83 | 4c9649a9 | j_mayer | |
84 | 4c9649a9 | j_mayer | /* EV45 minor type */
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85 | 4c9649a9 | j_mayer | enum {
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86 | 4c9649a9 | j_mayer | ALPHA_EV45_1 = 1, /* Pass 1 */ |
87 | 4c9649a9 | j_mayer | ALPHA_EV45_2 = 2, /* Pass 1.1 */ |
88 | 4c9649a9 | j_mayer | ALPHA_EV45_3 = 3, /* Pass 2 */ |
89 | 4c9649a9 | j_mayer | }; |
90 | 4c9649a9 | j_mayer | |
91 | 4c9649a9 | j_mayer | /* EV56 minor type */
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92 | 4c9649a9 | j_mayer | enum {
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93 | 4c9649a9 | j_mayer | ALPHA_EV56_1 = 1, /* Pass 1 */ |
94 | 4c9649a9 | j_mayer | ALPHA_EV56_2 = 2, /* Pass 2 */ |
95 | 4c9649a9 | j_mayer | }; |
96 | 4c9649a9 | j_mayer | |
97 | 4c9649a9 | j_mayer | enum {
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98 | 4c9649a9 | j_mayer | IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */ |
99 | 4c9649a9 | j_mayer | IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */ |
100 | 4c9649a9 | j_mayer | IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */ |
101 | 4c9649a9 | j_mayer | IMPLVER_21364 = 3, /* EV7 & EV79 */ |
102 | 4c9649a9 | j_mayer | }; |
103 | 4c9649a9 | j_mayer | |
104 | 4c9649a9 | j_mayer | enum {
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105 | 4c9649a9 | j_mayer | AMASK_BWX = 0x00000001,
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106 | 4c9649a9 | j_mayer | AMASK_FIX = 0x00000002,
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107 | 4c9649a9 | j_mayer | AMASK_CIX = 0x00000004,
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108 | 4c9649a9 | j_mayer | AMASK_MVI = 0x00000100,
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109 | 4c9649a9 | j_mayer | AMASK_TRAP = 0x00000200,
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110 | 4c9649a9 | j_mayer | AMASK_PREFETCH = 0x00001000,
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111 | 4c9649a9 | j_mayer | }; |
112 | 4c9649a9 | j_mayer | |
113 | 4c9649a9 | j_mayer | enum {
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114 | 4c9649a9 | j_mayer | VAX_ROUND_NORMAL = 0,
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115 | 4c9649a9 | j_mayer | VAX_ROUND_CHOPPED, |
116 | 4c9649a9 | j_mayer | }; |
117 | 4c9649a9 | j_mayer | |
118 | 4c9649a9 | j_mayer | enum {
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119 | 4c9649a9 | j_mayer | IEEE_ROUND_NORMAL = 0,
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120 | 4c9649a9 | j_mayer | IEEE_ROUND_DYNAMIC, |
121 | 4c9649a9 | j_mayer | IEEE_ROUND_PLUS, |
122 | 4c9649a9 | j_mayer | IEEE_ROUND_MINUS, |
123 | 4c9649a9 | j_mayer | IEEE_ROUND_CHOPPED, |
124 | 4c9649a9 | j_mayer | }; |
125 | 4c9649a9 | j_mayer | |
126 | 4c9649a9 | j_mayer | /* IEEE floating-point operations encoding */
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127 | 4c9649a9 | j_mayer | /* Trap mode */
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128 | 4c9649a9 | j_mayer | enum {
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129 | 4c9649a9 | j_mayer | FP_TRAP_I = 0x0,
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130 | 4c9649a9 | j_mayer | FP_TRAP_U = 0x1,
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131 | 4c9649a9 | j_mayer | FP_TRAP_S = 0x4,
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132 | 4c9649a9 | j_mayer | FP_TRAP_SU = 0x5,
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133 | 4c9649a9 | j_mayer | FP_TRAP_SUI = 0x7,
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134 | 4c9649a9 | j_mayer | }; |
135 | 4c9649a9 | j_mayer | |
136 | 4c9649a9 | j_mayer | /* Rounding mode */
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137 | 4c9649a9 | j_mayer | enum {
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138 | 4c9649a9 | j_mayer | FP_ROUND_CHOPPED = 0x0,
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139 | 4c9649a9 | j_mayer | FP_ROUND_MINUS = 0x1,
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140 | 4c9649a9 | j_mayer | FP_ROUND_NORMAL = 0x2,
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141 | 4c9649a9 | j_mayer | FP_ROUND_DYNAMIC = 0x3,
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142 | 4c9649a9 | j_mayer | }; |
143 | 4c9649a9 | j_mayer | |
144 | ba0e276d | Richard Henderson | /* FPCR bits */
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145 | ba0e276d | Richard Henderson | #define FPCR_SUM (1ULL << 63) |
146 | ba0e276d | Richard Henderson | #define FPCR_INED (1ULL << 62) |
147 | ba0e276d | Richard Henderson | #define FPCR_UNFD (1ULL << 61) |
148 | ba0e276d | Richard Henderson | #define FPCR_UNDZ (1ULL << 60) |
149 | ba0e276d | Richard Henderson | #define FPCR_DYN_SHIFT 58 |
150 | 8443effb | Richard Henderson | #define FPCR_DYN_CHOPPED (0ULL << FPCR_DYN_SHIFT) |
151 | 8443effb | Richard Henderson | #define FPCR_DYN_MINUS (1ULL << FPCR_DYN_SHIFT) |
152 | 8443effb | Richard Henderson | #define FPCR_DYN_NORMAL (2ULL << FPCR_DYN_SHIFT) |
153 | 8443effb | Richard Henderson | #define FPCR_DYN_PLUS (3ULL << FPCR_DYN_SHIFT) |
154 | ba0e276d | Richard Henderson | #define FPCR_DYN_MASK (3ULL << FPCR_DYN_SHIFT) |
155 | ba0e276d | Richard Henderson | #define FPCR_IOV (1ULL << 57) |
156 | ba0e276d | Richard Henderson | #define FPCR_INE (1ULL << 56) |
157 | ba0e276d | Richard Henderson | #define FPCR_UNF (1ULL << 55) |
158 | ba0e276d | Richard Henderson | #define FPCR_OVF (1ULL << 54) |
159 | ba0e276d | Richard Henderson | #define FPCR_DZE (1ULL << 53) |
160 | ba0e276d | Richard Henderson | #define FPCR_INV (1ULL << 52) |
161 | ba0e276d | Richard Henderson | #define FPCR_OVFD (1ULL << 51) |
162 | ba0e276d | Richard Henderson | #define FPCR_DZED (1ULL << 50) |
163 | ba0e276d | Richard Henderson | #define FPCR_INVD (1ULL << 49) |
164 | ba0e276d | Richard Henderson | #define FPCR_DNZ (1ULL << 48) |
165 | ba0e276d | Richard Henderson | #define FPCR_DNOD (1ULL << 47) |
166 | ba0e276d | Richard Henderson | #define FPCR_STATUS_MASK (FPCR_IOV | FPCR_INE | FPCR_UNF \
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167 | ba0e276d | Richard Henderson | | FPCR_OVF | FPCR_DZE | FPCR_INV) |
168 | ba0e276d | Richard Henderson | |
169 | ba0e276d | Richard Henderson | /* The silly software trap enables implemented by the kernel emulation.
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170 | ba0e276d | Richard Henderson | These are more or less architecturally required, since the real hardware
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171 | ba0e276d | Richard Henderson | has read-as-zero bits in the FPCR when the features aren't implemented.
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172 | ba0e276d | Richard Henderson | For the purposes of QEMU, we pretend the FPCR can hold everything. */
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173 | ba0e276d | Richard Henderson | #define SWCR_TRAP_ENABLE_INV (1ULL << 1) |
174 | ba0e276d | Richard Henderson | #define SWCR_TRAP_ENABLE_DZE (1ULL << 2) |
175 | ba0e276d | Richard Henderson | #define SWCR_TRAP_ENABLE_OVF (1ULL << 3) |
176 | ba0e276d | Richard Henderson | #define SWCR_TRAP_ENABLE_UNF (1ULL << 4) |
177 | ba0e276d | Richard Henderson | #define SWCR_TRAP_ENABLE_INE (1ULL << 5) |
178 | ba0e276d | Richard Henderson | #define SWCR_TRAP_ENABLE_DNO (1ULL << 6) |
179 | ba0e276d | Richard Henderson | #define SWCR_TRAP_ENABLE_MASK ((1ULL << 7) - (1ULL << 1)) |
180 | ba0e276d | Richard Henderson | |
181 | ba0e276d | Richard Henderson | #define SWCR_MAP_DMZ (1ULL << 12) |
182 | ba0e276d | Richard Henderson | #define SWCR_MAP_UMZ (1ULL << 13) |
183 | ba0e276d | Richard Henderson | #define SWCR_MAP_MASK (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
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184 | ba0e276d | Richard Henderson | |
185 | ba0e276d | Richard Henderson | #define SWCR_STATUS_INV (1ULL << 17) |
186 | ba0e276d | Richard Henderson | #define SWCR_STATUS_DZE (1ULL << 18) |
187 | ba0e276d | Richard Henderson | #define SWCR_STATUS_OVF (1ULL << 19) |
188 | ba0e276d | Richard Henderson | #define SWCR_STATUS_UNF (1ULL << 20) |
189 | ba0e276d | Richard Henderson | #define SWCR_STATUS_INE (1ULL << 21) |
190 | ba0e276d | Richard Henderson | #define SWCR_STATUS_DNO (1ULL << 22) |
191 | ba0e276d | Richard Henderson | #define SWCR_STATUS_MASK ((1ULL << 23) - (1ULL << 17)) |
192 | ba0e276d | Richard Henderson | |
193 | ba0e276d | Richard Henderson | #define SWCR_MASK (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
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194 | ba0e276d | Richard Henderson | |
195 | 4c9649a9 | j_mayer | /* Internal processor registers */
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196 | 4c9649a9 | j_mayer | /* XXX: TOFIX: most of those registers are implementation dependant */
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197 | 4c9649a9 | j_mayer | enum {
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198 | dad081ee | Richard Henderson | #if defined(CONFIG_USER_ONLY)
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199 | dad081ee | Richard Henderson | IPR_EXC_ADDR, |
200 | dad081ee | Richard Henderson | IPR_EXC_SUM, |
201 | dad081ee | Richard Henderson | IPR_EXC_MASK, |
202 | dad081ee | Richard Henderson | #else
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203 | 4c9649a9 | j_mayer | /* Ebox IPRs */
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204 | f8cc8534 | aurel32 | IPR_CC = 0xC0, /* 21264 */ |
205 | f8cc8534 | aurel32 | IPR_CC_CTL = 0xC1, /* 21264 */ |
206 | f8cc8534 | aurel32 | #define IPR_CC_CTL_ENA_SHIFT 32 |
207 | f8cc8534 | aurel32 | #define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL |
208 | f8cc8534 | aurel32 | IPR_VA = 0xC2, /* 21264 */ |
209 | f8cc8534 | aurel32 | IPR_VA_CTL = 0xC4, /* 21264 */ |
210 | f8cc8534 | aurel32 | #define IPR_VA_CTL_VA_48_SHIFT 1 |
211 | f8cc8534 | aurel32 | #define IPR_VA_CTL_VPTB_SHIFT 30 |
212 | f8cc8534 | aurel32 | IPR_VA_FORM = 0xC3, /* 21264 */ |
213 | 4c9649a9 | j_mayer | /* Ibox IPRs */
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214 | f8cc8534 | aurel32 | IPR_ITB_TAG = 0x00, /* 21264 */ |
215 | f8cc8534 | aurel32 | IPR_ITB_PTE = 0x01, /* 21264 */ |
216 | f8cc8534 | aurel32 | IPR_ITB_IAP = 0x02,
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217 | f8cc8534 | aurel32 | IPR_ITB_IA = 0x03, /* 21264 */ |
218 | 2642cdb3 | aurel32 | IPR_ITB_IS = 0x04, /* 21264 */ |
219 | 4c9649a9 | j_mayer | IPR_PMPC = 0x05,
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220 | f8cc8534 | aurel32 | IPR_EXC_ADDR = 0x06, /* 21264 */ |
221 | f8cc8534 | aurel32 | IPR_IVA_FORM = 0x07, /* 21264 */ |
222 | f8cc8534 | aurel32 | IPR_CM = 0x09, /* 21264 */ |
223 | f8cc8534 | aurel32 | #define IPR_CM_SHIFT 3 |
224 | f8cc8534 | aurel32 | #define IPR_CM_MASK (3ULL << IPR_CM_SHIFT) /* 21264 */ |
225 | f8cc8534 | aurel32 | IPR_IER = 0x0A, /* 21264 */ |
226 | f8cc8534 | aurel32 | #define IPR_IER_MASK 0x0000007fffffe000ULL |
227 | f8cc8534 | aurel32 | IPR_IER_CM = 0x0B, /* 21264: = CM | IER */ |
228 | f8cc8534 | aurel32 | IPR_SIRR = 0x0C, /* 21264 */ |
229 | f8cc8534 | aurel32 | #define IPR_SIRR_SHIFT 14 |
230 | f8cc8534 | aurel32 | #define IPR_SIRR_MASK 0x7fff |
231 | f8cc8534 | aurel32 | IPR_ISUM = 0x0D, /* 21264 */ |
232 | f8cc8534 | aurel32 | IPR_HW_INT_CLR = 0x0E, /* 21264 */ |
233 | 4c9649a9 | j_mayer | IPR_EXC_SUM = 0x0F,
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234 | 4c9649a9 | j_mayer | IPR_PAL_BASE = 0x10,
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235 | 4c9649a9 | j_mayer | IPR_I_CTL = 0x11,
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236 | f8cc8534 | aurel32 | #define IPR_I_CTL_CHIP_ID_SHIFT 24 /* 21264 */ |
237 | f8cc8534 | aurel32 | #define IPR_I_CTL_BIST_FAIL (1 << 23) /* 21264 */ |
238 | f8cc8534 | aurel32 | #define IPR_I_CTL_IC_EN_SHIFT 2 /* 21264 */ |
239 | f8cc8534 | aurel32 | #define IPR_I_CTL_SDE1_SHIFT 7 /* 21264 */ |
240 | f8cc8534 | aurel32 | #define IPR_I_CTL_HWE_SHIFT 12 /* 21264 */ |
241 | f8cc8534 | aurel32 | #define IPR_I_CTL_VA_48_SHIFT 15 /* 21264 */ |
242 | f8cc8534 | aurel32 | #define IPR_I_CTL_SPE_SHIFT 3 /* 21264 */ |
243 | f8cc8534 | aurel32 | #define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */ |
244 | f8cc8534 | aurel32 | IPR_I_STAT = 0x16, /* 21264 */ |
245 | f8cc8534 | aurel32 | IPR_IC_FLUSH = 0x13, /* 21264 */ |
246 | f8cc8534 | aurel32 | IPR_IC_FLUSH_ASM = 0x12, /* 21264 */ |
247 | 4c9649a9 | j_mayer | IPR_CLR_MAP = 0x15,
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248 | 4c9649a9 | j_mayer | IPR_SLEEP = 0x17,
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249 | 4c9649a9 | j_mayer | IPR_PCTX = 0x40,
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250 | f8cc8534 | aurel32 | IPR_PCTX_ASN = 0x01, /* field */ |
251 | f8cc8534 | aurel32 | #define IPR_PCTX_ASN_SHIFT 39 |
252 | f8cc8534 | aurel32 | IPR_PCTX_ASTER = 0x02, /* field */ |
253 | f8cc8534 | aurel32 | #define IPR_PCTX_ASTER_SHIFT 5 |
254 | f8cc8534 | aurel32 | IPR_PCTX_ASTRR = 0x04, /* field */ |
255 | f8cc8534 | aurel32 | #define IPR_PCTX_ASTRR_SHIFT 9 |
256 | f8cc8534 | aurel32 | IPR_PCTX_PPCE = 0x08, /* field */ |
257 | f8cc8534 | aurel32 | #define IPR_PCTX_PPCE_SHIFT 1 |
258 | f8cc8534 | aurel32 | IPR_PCTX_FPE = 0x10, /* field */ |
259 | f8cc8534 | aurel32 | #define IPR_PCTX_FPE_SHIFT 2 |
260 | f8cc8534 | aurel32 | IPR_PCTX_ALL = 0x5f, /* all fields */ |
261 | f8cc8534 | aurel32 | IPR_PCTR_CTL = 0x14, /* 21264 */ |
262 | 4c9649a9 | j_mayer | /* Mbox IPRs */
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263 | f8cc8534 | aurel32 | IPR_DTB_TAG0 = 0x20, /* 21264 */ |
264 | f8cc8534 | aurel32 | IPR_DTB_TAG1 = 0xA0, /* 21264 */ |
265 | f8cc8534 | aurel32 | IPR_DTB_PTE0 = 0x21, /* 21264 */ |
266 | f8cc8534 | aurel32 | IPR_DTB_PTE1 = 0xA1, /* 21264 */ |
267 | 4c9649a9 | j_mayer | IPR_DTB_ALTMODE = 0xA6,
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268 | f8cc8534 | aurel32 | IPR_DTB_ALTMODE0 = 0x26, /* 21264 */ |
269 | f8cc8534 | aurel32 | #define IPR_DTB_ALTMODE_MASK 3 |
270 | 4c9649a9 | j_mayer | IPR_DTB_IAP = 0xA2,
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271 | f8cc8534 | aurel32 | IPR_DTB_IA = 0xA3, /* 21264 */ |
272 | 4c9649a9 | j_mayer | IPR_DTB_IS0 = 0x24,
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273 | 4c9649a9 | j_mayer | IPR_DTB_IS1 = 0xA4,
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274 | f8cc8534 | aurel32 | IPR_DTB_ASN0 = 0x25, /* 21264 */ |
275 | f8cc8534 | aurel32 | IPR_DTB_ASN1 = 0xA5, /* 21264 */ |
276 | f8cc8534 | aurel32 | #define IPR_DTB_ASN_SHIFT 56 |
277 | f8cc8534 | aurel32 | IPR_MM_STAT = 0x27, /* 21264 */ |
278 | f8cc8534 | aurel32 | IPR_M_CTL = 0x28, /* 21264 */ |
279 | f8cc8534 | aurel32 | #define IPR_M_CTL_SPE_SHIFT 1 |
280 | f8cc8534 | aurel32 | #define IPR_M_CTL_SPE_MASK 7 |
281 | 2642cdb3 | aurel32 | IPR_DC_CTL = 0x29, /* 21264 */ |
282 | f8cc8534 | aurel32 | IPR_DC_STAT = 0x2A, /* 21264 */ |
283 | 4c9649a9 | j_mayer | /* Cbox IPRs */
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284 | 4c9649a9 | j_mayer | IPR_C_DATA = 0x2B,
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285 | 4c9649a9 | j_mayer | IPR_C_SHIFT = 0x2C,
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286 | 4c9649a9 | j_mayer | |
287 | 4c9649a9 | j_mayer | IPR_ASN, |
288 | 4c9649a9 | j_mayer | IPR_ASTEN, |
289 | 4c9649a9 | j_mayer | IPR_ASTSR, |
290 | 4c9649a9 | j_mayer | IPR_DATFX, |
291 | 4c9649a9 | j_mayer | IPR_ESP, |
292 | 4c9649a9 | j_mayer | IPR_FEN, |
293 | 4c9649a9 | j_mayer | IPR_IPIR, |
294 | 4c9649a9 | j_mayer | IPR_IPL, |
295 | 4c9649a9 | j_mayer | IPR_KSP, |
296 | 4c9649a9 | j_mayer | IPR_MCES, |
297 | 4c9649a9 | j_mayer | IPR_PERFMON, |
298 | 4c9649a9 | j_mayer | IPR_PCBB, |
299 | 4c9649a9 | j_mayer | IPR_PRBR, |
300 | 4c9649a9 | j_mayer | IPR_PTBR, |
301 | 4c9649a9 | j_mayer | IPR_SCBB, |
302 | 4c9649a9 | j_mayer | IPR_SISR, |
303 | 4c9649a9 | j_mayer | IPR_SSP, |
304 | 4c9649a9 | j_mayer | IPR_SYSPTBR, |
305 | 4c9649a9 | j_mayer | IPR_TBCHK, |
306 | 4c9649a9 | j_mayer | IPR_TBIA, |
307 | 4c9649a9 | j_mayer | IPR_TBIAP, |
308 | 4c9649a9 | j_mayer | IPR_TBIS, |
309 | 4c9649a9 | j_mayer | IPR_TBISD, |
310 | 4c9649a9 | j_mayer | IPR_TBISI, |
311 | 4c9649a9 | j_mayer | IPR_USP, |
312 | 4c9649a9 | j_mayer | IPR_VIRBND, |
313 | 4c9649a9 | j_mayer | IPR_VPTB, |
314 | 4c9649a9 | j_mayer | IPR_WHAMI, |
315 | 4c9649a9 | j_mayer | IPR_ALT_MODE, |
316 | dad081ee | Richard Henderson | #endif
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317 | 4c9649a9 | j_mayer | IPR_LAST, |
318 | 4c9649a9 | j_mayer | }; |
319 | 4c9649a9 | j_mayer | |
320 | 4c9649a9 | j_mayer | typedef struct CPUAlphaState CPUAlphaState; |
321 | 4c9649a9 | j_mayer | |
322 | 6ebbf390 | j_mayer | #define NB_MMU_MODES 4 |
323 | 6ebbf390 | j_mayer | |
324 | 4c9649a9 | j_mayer | struct CPUAlphaState {
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325 | 4c9649a9 | j_mayer | uint64_t ir[31];
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326 | 8443effb | Richard Henderson | float64 fir[31];
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327 | 4c9649a9 | j_mayer | uint64_t pc; |
328 | 4c9649a9 | j_mayer | uint64_t ipr[IPR_LAST]; |
329 | 4c9649a9 | j_mayer | uint64_t ps; |
330 | 4c9649a9 | j_mayer | uint64_t unique; |
331 | 6910b8f6 | Richard Henderson | uint64_t lock_addr; |
332 | 6910b8f6 | Richard Henderson | uint64_t lock_st_addr; |
333 | 6910b8f6 | Richard Henderson | uint64_t lock_value; |
334 | 8443effb | Richard Henderson | float_status fp_status; |
335 | 8443effb | Richard Henderson | /* The following fields make up the FPCR, but in FP_STATUS format. */
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336 | 8443effb | Richard Henderson | uint8_t fpcr_exc_status; |
337 | 8443effb | Richard Henderson | uint8_t fpcr_exc_mask; |
338 | 8443effb | Richard Henderson | uint8_t fpcr_dyn_round; |
339 | 8443effb | Richard Henderson | uint8_t fpcr_flush_to_zero; |
340 | 8443effb | Richard Henderson | uint8_t fpcr_dnz; |
341 | 8443effb | Richard Henderson | uint8_t fpcr_dnod; |
342 | 8443effb | Richard Henderson | uint8_t fpcr_undz; |
343 | 8443effb | Richard Henderson | |
344 | 8443effb | Richard Henderson | /* Used for HW_LD / HW_ST */
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345 | 8443effb | Richard Henderson | uint8_t saved_mode; |
346 | 8443effb | Richard Henderson | /* For RC and RS */
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347 | 8443effb | Richard Henderson | uint8_t intr_flag; |
348 | 4c9649a9 | j_mayer | |
349 | bf9525e9 | j_mayer | #if TARGET_LONG_BITS > HOST_LONG_BITS
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350 | bf9525e9 | j_mayer | /* temporary fixed-point registers
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351 | bf9525e9 | j_mayer | * used to emulate 64 bits target on 32 bits hosts
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352 | 5fafdf24 | ths | */
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353 | 04acd307 | aurel32 | target_ulong t0, t1; |
354 | bf9525e9 | j_mayer | #endif
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355 | 4c9649a9 | j_mayer | |
356 | 4c9649a9 | j_mayer | /* Those resources are used only in Qemu core */
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357 | 4c9649a9 | j_mayer | CPU_COMMON |
358 | 4c9649a9 | j_mayer | |
359 | 4c9649a9 | j_mayer | uint32_t hflags; |
360 | 4c9649a9 | j_mayer | |
361 | 4c9649a9 | j_mayer | int error_code;
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362 | 4c9649a9 | j_mayer | |
363 | 4c9649a9 | j_mayer | uint32_t features; |
364 | 4c9649a9 | j_mayer | uint32_t amask; |
365 | 4c9649a9 | j_mayer | int implver;
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366 | 4c9649a9 | j_mayer | }; |
367 | 4c9649a9 | j_mayer | |
368 | 9467d44c | ths | #define cpu_init cpu_alpha_init
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369 | 9467d44c | ths | #define cpu_exec cpu_alpha_exec
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370 | 9467d44c | ths | #define cpu_gen_code cpu_alpha_gen_code
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371 | 9467d44c | ths | #define cpu_signal_handler cpu_alpha_signal_handler
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372 | 9467d44c | ths | |
373 | 6ebbf390 | j_mayer | /* MMU modes definitions */
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374 | 6ebbf390 | j_mayer | #define MMU_MODE0_SUFFIX _kernel
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375 | 6ebbf390 | j_mayer | #define MMU_MODE1_SUFFIX _executive
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376 | 6ebbf390 | j_mayer | #define MMU_MODE2_SUFFIX _supervisor
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377 | 6ebbf390 | j_mayer | #define MMU_MODE3_SUFFIX _user
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378 | 6ebbf390 | j_mayer | #define MMU_USER_IDX 3 |
379 | 6ebbf390 | j_mayer | static inline int cpu_mmu_index (CPUState *env) |
380 | 6ebbf390 | j_mayer | { |
381 | 6ebbf390 | j_mayer | return (env->ps >> 3) & 3; |
382 | 6ebbf390 | j_mayer | } |
383 | 6ebbf390 | j_mayer | |
384 | 4c9649a9 | j_mayer | #include "cpu-all.h" |
385 | 4c9649a9 | j_mayer | |
386 | 4c9649a9 | j_mayer | enum {
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387 | 4c9649a9 | j_mayer | FEATURE_ASN = 0x00000001,
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388 | 4c9649a9 | j_mayer | FEATURE_SPS = 0x00000002,
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389 | 4c9649a9 | j_mayer | FEATURE_VIRBND = 0x00000004,
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390 | 4c9649a9 | j_mayer | FEATURE_TBCHK = 0x00000008,
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391 | 4c9649a9 | j_mayer | }; |
392 | 4c9649a9 | j_mayer | |
393 | 4c9649a9 | j_mayer | enum {
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394 | 4c9649a9 | j_mayer | EXCP_RESET = 0x0000,
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395 | 4c9649a9 | j_mayer | EXCP_MCHK = 0x0020,
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396 | 4c9649a9 | j_mayer | EXCP_ARITH = 0x0060,
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397 | 4c9649a9 | j_mayer | EXCP_HW_INTERRUPT = 0x00E0,
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398 | 4c9649a9 | j_mayer | EXCP_DFAULT = 0x01E0,
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399 | 4c9649a9 | j_mayer | EXCP_DTB_MISS_PAL = 0x09E0,
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400 | 4c9649a9 | j_mayer | EXCP_ITB_MISS = 0x03E0,
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401 | 4c9649a9 | j_mayer | EXCP_ITB_ACV = 0x07E0,
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402 | 4c9649a9 | j_mayer | EXCP_DTB_MISS_NATIVE = 0x08E0,
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403 | 4c9649a9 | j_mayer | EXCP_UNALIGN = 0x11E0,
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404 | 4c9649a9 | j_mayer | EXCP_OPCDEC = 0x13E0,
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405 | 4c9649a9 | j_mayer | EXCP_FEN = 0x17E0,
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406 | 4c9649a9 | j_mayer | EXCP_CALL_PAL = 0x2000,
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407 | 4c9649a9 | j_mayer | EXCP_CALL_PALP = 0x3000,
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408 | 4c9649a9 | j_mayer | EXCP_CALL_PALE = 0x4000,
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409 | 4c9649a9 | j_mayer | /* Pseudo exception for console */
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410 | 4c9649a9 | j_mayer | EXCP_CONSOLE_DISPATCH = 0x4001,
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411 | 4c9649a9 | j_mayer | EXCP_CONSOLE_FIXUP = 0x4002,
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412 | 6910b8f6 | Richard Henderson | EXCP_STL_C = 0x4003,
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413 | 6910b8f6 | Richard Henderson | EXCP_STQ_C = 0x4004,
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414 | 4c9649a9 | j_mayer | }; |
415 | 4c9649a9 | j_mayer | |
416 | 4c9649a9 | j_mayer | /* Arithmetic exception */
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417 | 866be65d | Richard Henderson | #define EXC_M_IOV (1<<16) /* Integer Overflow */ |
418 | 866be65d | Richard Henderson | #define EXC_M_INE (1<<15) /* Inexact result */ |
419 | 866be65d | Richard Henderson | #define EXC_M_UNF (1<<14) /* Underflow */ |
420 | 866be65d | Richard Henderson | #define EXC_M_FOV (1<<13) /* Overflow */ |
421 | 866be65d | Richard Henderson | #define EXC_M_DZE (1<<12) /* Division by zero */ |
422 | 866be65d | Richard Henderson | #define EXC_M_INV (1<<11) /* Invalid operation */ |
423 | 866be65d | Richard Henderson | #define EXC_M_SWC (1<<10) /* Software completion */ |
424 | 4c9649a9 | j_mayer | |
425 | 4c9649a9 | j_mayer | enum {
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426 | 4c9649a9 | j_mayer | IR_V0 = 0,
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427 | 4c9649a9 | j_mayer | IR_T0 = 1,
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428 | 4c9649a9 | j_mayer | IR_T1 = 2,
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429 | 4c9649a9 | j_mayer | IR_T2 = 3,
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430 | 4c9649a9 | j_mayer | IR_T3 = 4,
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431 | 4c9649a9 | j_mayer | IR_T4 = 5,
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432 | 4c9649a9 | j_mayer | IR_T5 = 6,
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433 | 4c9649a9 | j_mayer | IR_T6 = 7,
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434 | 4c9649a9 | j_mayer | IR_T7 = 8,
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435 | 4c9649a9 | j_mayer | IR_S0 = 9,
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436 | 4c9649a9 | j_mayer | IR_S1 = 10,
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437 | 4c9649a9 | j_mayer | IR_S2 = 11,
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438 | 4c9649a9 | j_mayer | IR_S3 = 12,
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439 | 4c9649a9 | j_mayer | IR_S4 = 13,
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440 | 4c9649a9 | j_mayer | IR_S5 = 14,
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441 | 4c9649a9 | j_mayer | IR_S6 = 15,
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442 | a4b388ff | Richard Henderson | IR_FP = IR_S6, |
443 | 4c9649a9 | j_mayer | IR_A0 = 16,
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444 | 4c9649a9 | j_mayer | IR_A1 = 17,
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445 | 4c9649a9 | j_mayer | IR_A2 = 18,
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446 | 4c9649a9 | j_mayer | IR_A3 = 19,
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447 | 4c9649a9 | j_mayer | IR_A4 = 20,
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448 | 4c9649a9 | j_mayer | IR_A5 = 21,
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449 | 4c9649a9 | j_mayer | IR_T8 = 22,
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450 | 4c9649a9 | j_mayer | IR_T9 = 23,
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451 | 4c9649a9 | j_mayer | IR_T10 = 24,
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452 | 4c9649a9 | j_mayer | IR_T11 = 25,
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453 | 4c9649a9 | j_mayer | IR_RA = 26,
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454 | 4c9649a9 | j_mayer | IR_T12 = 27,
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455 | a4b388ff | Richard Henderson | IR_PV = IR_T12, |
456 | 4c9649a9 | j_mayer | IR_AT = 28,
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457 | 4c9649a9 | j_mayer | IR_GP = 29,
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458 | 4c9649a9 | j_mayer | IR_SP = 30,
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459 | 4c9649a9 | j_mayer | IR_ZERO = 31,
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460 | 4c9649a9 | j_mayer | }; |
461 | 4c9649a9 | j_mayer | |
462 | aaed909a | bellard | CPUAlphaState * cpu_alpha_init (const char *cpu_model); |
463 | e96efcfc | j_mayer | int cpu_alpha_exec(CPUAlphaState *s);
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464 | e96efcfc | j_mayer | /* you can call this signal handler from your SIGBUS and SIGSEGV
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465 | e96efcfc | j_mayer | signal handlers to inform the virtual CPU of exceptions. non zero
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466 | e96efcfc | j_mayer | is returned if the signal was handled by the virtual CPU. */
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467 | 5fafdf24 | ths | int cpu_alpha_signal_handler(int host_signum, void *pinfo, |
468 | e96efcfc | j_mayer | void *puc);
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469 | 95870356 | aurel32 | int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw, |
470 | 95870356 | aurel32 | int mmu_idx, int is_softmmu); |
471 | 0b5c1ce8 | Nathan Froyd | #define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
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472 | 95870356 | aurel32 | void do_interrupt (CPUState *env);
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473 | 95870356 | aurel32 | |
474 | ba0e276d | Richard Henderson | uint64_t cpu_alpha_load_fpcr (CPUState *env); |
475 | ba0e276d | Richard Henderson | void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
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476 | 4c9649a9 | j_mayer | int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp); |
477 | 4c9649a9 | j_mayer | int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp); |
478 | 4c9649a9 | j_mayer | |
479 | 6b917547 | aliguori | static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, |
480 | 6b917547 | aliguori | target_ulong *cs_base, int *flags)
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481 | 6b917547 | aliguori | { |
482 | 6b917547 | aliguori | *pc = env->pc; |
483 | 6b917547 | aliguori | *cs_base = 0;
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484 | 6b917547 | aliguori | *flags = env->ps; |
485 | 6b917547 | aliguori | } |
486 | 6b917547 | aliguori | |
487 | a4b388ff | Richard Henderson | #if defined(CONFIG_USER_ONLY)
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488 | a4b388ff | Richard Henderson | static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) |
489 | a4b388ff | Richard Henderson | { |
490 | a4b388ff | Richard Henderson | if (newsp) {
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491 | a4b388ff | Richard Henderson | env->ir[IR_SP] = newsp; |
492 | a4b388ff | Richard Henderson | } |
493 | a4b388ff | Richard Henderson | env->ir[IR_V0] = 0;
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494 | a4b388ff | Richard Henderson | env->ir[IR_A3] = 0;
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495 | a4b388ff | Richard Henderson | } |
496 | a4b388ff | Richard Henderson | |
497 | a4b388ff | Richard Henderson | static inline void cpu_set_tls(CPUState *env, target_ulong newtls) |
498 | a4b388ff | Richard Henderson | { |
499 | a4b388ff | Richard Henderson | env->unique = newtls; |
500 | a4b388ff | Richard Henderson | } |
501 | a4b388ff | Richard Henderson | #endif
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502 | a4b388ff | Richard Henderson | |
503 | 4c9649a9 | j_mayer | #endif /* !defined (__CPU_ALPHA_H__) */ |