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target-alpha: Single-step properly across branches.
We were failing to generate EXC_DEBUG in the EXIT_PC_UPDATED path.This caused us not to stop at the instruction after a branch, buton the instruction afterward.
Signed-off-by: Richard Henderson <rth@twiddle.net>
target-alpha: Remove partial support for palcode emulation.
This code does not work, and will be replaced by a bios image.
Remove unused function parameters from gen_pc_load and rename the function
Function gen_pc_load was introduced in commitd2856f1ad4c259e5766847c49acbb4e390731bd4.The only reason for parameter searched_pc wasa debug statement in target-i386/translate.c....
Fix conversions from pointer to tcg_target_long
tcg_gen_exit_tb takes a parameter of type tcg_target_long,so the type casts of pointer to long should be replaced bytype casts of pointer to tcg_target_long (suggested by Blue Swirl).
These changes are needed for build environments where...
target-alpha: Implement cpys{, n, e} inline.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
target-alpha: Implement rs/rc properly.
This is a per-cpu flag; there's no need for a spinlock of any kind.
We were also failing to manipulate the flag with $31 as a target regand failing to clear the flag on execution of a return-from-interruptinstruction....
target-alpha: Implement cvtlq inline.
It's a simple shift and mask sequence.
target-alpha: Emit goto_tb opcodes.
Use an ExitStatus enumeration instead of magic numbers as the returnvalue from translate_one. Emit goto_tb opcodes when ending a TB viaa direct branch.
target-alpha: Update commentary for opcode 0x1A.
target-alpha: Indicate NORETURN status when raising exception.
When (indirectly) calling raise_exception, don't emit cleanupcode at the end of the TB, as it is unused.
target-alpha: Fix load-locked/store-conditional.
Use an exception plus start_exclusive to implement the compare-and-swap.This follows the example set by the MIPS and PPC ports.
alpha: remove dead assignments, spotted by clang analyzer
Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
target-alpha: Use setcond for int comparisons.
target-alpha: Use non-inverted arguments to gen_{f}cmov.
The inverted conditions as argument to the function looks wrongat a glance inside translate_one. Since we have an easy functionto produce the inversion now, use it.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
target-alpha: Implement cvtql inline.
It's a simple mask and shift sequence.Also, fix a typo in the actual masks used.
alpha-linux-user: Implement signals.
Move userland PALcode handling into linux-user main loop so thatwe can send signals from there. This also makes alpha_palcode.csystem-level only, so don't build it for userland. Add definesfor GENTRAP PALcall mapping to signals....
target-alpha: Implement IEEE FP qualifiers.
IEEE FP instructions are split up so that the rounding modecoming from the instruction and exceptions (both masking anddelivery) are handled external to the base FP operation.FP exceptions are properly raised for non-finite inputs to...
target-alpha: Reduce internal processor registers for user-mode.
The existing set of IPRs is totally irrelevant to user-mode emulation.Indeed, they most are irrelevant to implementing kernel-mode emulation,and would only be relevant to PAL-mode emulation, which I suspect that...
target-alpha: Initialize fpcr
Linux, at least, disables exceptions by default.
target-alpha: Emit tcg debug_insn_start.
target-alpha: Implement fp branch/cmov inline.
The old fcmov implementation had a typo:- tcg_gen_mov_i64(cpu_fir[rc], cpu_fir[ra]);which moved the condition, not the second source, to the destination.
But it's also easy to implement the simplified fp comparison inline....
target-alpha: Expand ins*l inline.
Similar in difficulty to ext*l, already expanded.
target-alpha: Expand msk*l inline.
target-alpha: Expand msk*h inline.
target-alpha: Expand ins*h inline.
target-alpha: Fix FMOV.
Properly handle move from the zero register.
target-alpha: Fix double log_cpu_state.
The proper logging is handled by generic code.
target-alpha: Implement RD/WRUNIQUE in the translator
When emulating user-mode only, there's no reason to exitthe translation block to effect a call_pal. We can generatea move to/from the unique slot directly.
target-alpha: Implement missing MVI instructions.
target-alpha: Fix -d in_asm
Generic disassembly was incorrectly keyed on ALPHA_DEBUG_DISASrather than the generic DEBUG_DISAS. Use qemu_log_mask foradditional LOG_DISAS output. Delete some random insn_countlogging noise from gen_intermediate_code_internal....
target-alpha: Expand zap/zapnot with immediate inline.
The vast majority of zap instructions have an immediate operand,since zapnot is the canonical method to zero-extend from u16 or u32.
target-alpha: Rewrite gen_ext_[hl] in terms of zapnot.
The architecture manual specifies the EXT instructionsin terms of the ZAPNOT operation; writing it that way inthe translator makes things a bit clearer.
target-alpha: Fix fbcond branch offset.
The instructions use a disp21 like all other branch insns,not the disp16 that was being passed.
target-alpha: Remove bogus DO_TB_FLUSH code from translator.
target-alpha: Honor the -cpu command line argument.
Also change the default cpu to ev67.
target-alpha: fix extlh instruction
The extlh instruction on Alpha currently doesn't work properly.It's a combination of a cut/paste bug (16 where it should be 32) as wellas a "shift by 64" bug.
Signed-off-by: Vince Weaver <vince@csl.cornell.edu>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Fix sys-queue.h conflict for good
Problem: Our file sys-queue.h is a copy of the BSD file, but there aresome additions and it's not entirely compatible. Because of that, there havebeen conflicts with system headers on BSD systems. Some hacks have beenintroduced in the commits 15cc9235840a22c289edbe064a9b3c19c5f49896,...
Replace always_inline with inline
We define inline as always_inline.
Update to a hopefully more future proof FSF address
qemu: introduce qemu_init_vcpu (Marcelo Tosatti)
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix emulation of ecb
As ECB is a hint, it can be safely emulated as a nop.
This change is necessary to boot Tru64.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7111 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: remove amask helper
The direct use of helper_amask in translate.c was bogus (as env is notassigned). Directly code amask in tcg and remove the helper.
Signed-off-by: Tristan Gingold <gingold@adacore.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: remove helper_load_implver
There is no need to use an helper. Directly load the value with tcg code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7074 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix palcode mask for user pal calls
(Also 6 bits for unprivileged calls)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7033 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: stop translation if too long
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7027 c046a42c-6fe2-441c-8c8c-71466251a162
Add new command line option -singlestep for tcg single stepping.
This replaces a compile time option for some targets and addsthis feature to targets which did not have a compile time option.
Add monitor command to enable or disable single step mode.
Modify monitor command "info status" to display single step mode....
target-alpha: bug fix: avoid nop to override next instruction
While searching PC, always store the pc of a new instruction.Instructions that didn't generate tcg code (such as nop) prevented the nextone to be referenced.
Signed-off-by: Tristan Gingold <gingold@adacore.com>...
target-alpha: add instruction name in comments for hw_ld opcode.
Make code slightly easier to read.Also unused hw_ld opcodes now generate an invalid opc fault.
target-alpha: fix temp free for hw_st
No need to stop translation after hw_st.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6925 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix bug: integer conditional branch offset is 21 bits wide.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6924 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: Fix bug: do not mask address LSBs for ldwu.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6923 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: Fix bug: palcode is at least 6 bits.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6922 c046a42c-6fe2-441c-8c8c-71466251a162
targets: remove error handling from qemu_malloc() callers (Avi Kivity)
Signed-off-by: Avi Kivity <avi@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost)
These are references to 'loglevel' that aren't on a simple 'if (loglevel &X) qemu_log()' statement.
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>...
Convert references to logfile/loglevel to use qemu_log*() macros
This is a large patch that changes all occurrences of logfile/loglevelglobal variables to use the new qemu_log*() macros.
Clean up debugging code #ifdefs (Eduardo Habkost)
Use macros to avoid #ifdefs on debugging code.
This patch doesn't try to merge logging macros from different files,but just unify the debugging code #ifdefs onto a macro on each file. Afurther cleanup can unify the debugging macros on a common header, later...
Update FSF address in GPL/LGPL boilerplate
The attached patch updates the FSF address in the GPL/LGPL boilerplatein most GPL/LGPLed files, and also in COPYING.LIB.
Signed-off-by: Stuart Brady <stuart.brady@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: gdb-stub support
(Vince Weaver)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5945 c046a42c-6fe2-441c-8c8c-71466251a162
Use sys-queue.h for break/watchpoint managment (Jan Kiszka)
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying thecode and also fixing a use after release issue incpu_break/watchpoint_remove_all.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>...
Refactor and enhance break/watchpoint API (Jan Kiszka)
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow thesucceeding enhancements this series comes with.
First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switchingto dynamically allocated data structures that are kept in linked lists....
TCG variable type checking.
Signed-off-by: Paul Brook <paul@codesourcery.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix decoding of CVTST /S
This patch fixes the decoding of CVTST /S which wasincorrectly being decoded as CVTTS.
This fixes SPEC2000 gcc with 200.i input.
Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>...
target-alpha: disable single stepping and TB flush by default
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5690 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix double TCG variable allocation
Noticed by Chris Krumme.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5671 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix the return value of stl_c/stq_c
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5649 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix locked loads/stores
Fix reading of cpu_lock in gen_qemu_stql_c, original patch from LaurentDesnogues.
A new flag was added to gen_store_mem to allocate local temps insteadof temps; this flag should be set when the tcg_gen_qemu_store callback...
target-alpha: Fix ret instruction
Hopefully pine doesn't corrupt this patch, I've had problems recently.
For an alpha "ret" instruction, of the type ret $26
The return was being ignored. This is because in translate.cregister $26 (the return address) was being over-written with the current...
target-alpha: use the new TCG logical operations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5502 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert palcode ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5360 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert locked load/store to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5359 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: misc fixes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5355 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert FP ops to TCG
- Convert FP ops to TCG- Fix S format- Implement F and G formats (untested)- Fix MF_FPCR an MT_FPCR- Fix FTOIS, FTOIT, ITOFF, ITOFS, ITOFT- Fix CPYSN, CPYSE
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5354 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: factorize load/store code
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5353 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: switch most load/store ops to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5255 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert remaining arith3 functions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5254 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix one more literal sign issue
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5251 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: instruction decoding simplification
Use a litteral value of 0 when rb31 is used. This reduces the testsin the instruction decoding. Also remove almost unused corner cases.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5250 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert cmp* instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5249 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: fix a missing literal sign issue
Reported by Tristan Gingold
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5248 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: switch a few helpers to TCG
Switch a few helpers to TCG and implement RC and RS instructions
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5247 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert byte manipulation instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5246 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: convert cmov and bcond to TCG
Patch mostly by Tristan Gingold
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5245 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: small optimizations
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5238 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: fix TCG register names
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5237 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert some arith3 instructions to TCG
Replace gen_arith3 generic macro and dyngen ops by instruction specificoptimized TCG code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5236 c046a42c-6fe2-441c-8c8c-71466251a162
target-alpha: convert arith2 instructions to TCG
Replace gen_arith2 generic macro and dyngon ops by instruction specificoptimized TCG code.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5235 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: fix lit sign
according to the alpha arch reference, the literal field of an operateinstruction is unsigned:
If bit <12> of the instruction is 1, an 8-bit zero-extended literalconstant is formed by bits<20:13> of the instruction. The l teral is interpreted as a positive...
fix alpha cmovxx instruction
The CMOV instruction is defined by the alpha manual as:
CMOVxx Ra.rq,Rb.rq,Rc.wq !Operate formatCMOVxx Ra.rq,#b.ib,Rc.wq !Operate format
Operation:IF TEST THENRc ← Rbv
The current qemu behavior inverses Ra and Rb. This is fixed by this...
alpha: convert a few more instructions to TCG
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5152 c046a42c-6fe2-441c-8c8c-71466251a162
alpha: directly access ir registers
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5151 c046a42c-6fe2-441c-8c8c-71466251a162
convert of few alpha insn to TCG
(based on a patch from Tristan Gingold)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5150 c046a42c-6fe2-441c-8c8c-71466251a162
Fix warnings that would be generated by gcc -Wstrict-prototypes
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5021 c046a42c-6fe2-441c-8c8c-71466251a162
Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
Add missing static qualifiers.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4801 c046a42c-6fe2-441c-8c8c-71466251a162
Add instruction counter.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
Factorize code in translate.c
(Glauber Costa)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
Remove osdep.c/qemu-img code duplication
(Kevin Wolf)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
use the TCG code generator
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
added cpu_model parameter to cpu_init()
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
Alpha coding style and inlining fixes.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3462 c046a42c-6fe2-441c-8c8c-71466251a162