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1
/*
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 *  Alpha emulation cpu definitions for qemu.
3
 *
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 *  Copyright (c) 2007 Jocelyn Mayer
5
 *
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 * This library is free software; you can redistribute it and/or
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 * modify it under the terms of the GNU Lesser General Public
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 * License as published by the Free Software Foundation; either
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 * version 2 of the License, or (at your option) any later version.
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 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
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 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
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 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
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 */
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#if !defined (__CPU_ALPHA_H__)
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#define __CPU_ALPHA_H__
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#include "config.h"
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#define TARGET_LONG_BITS 64
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#define CPUState struct CPUAlphaState
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#include "cpu-defs.h"
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#include <setjmp.h>
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#include "softfloat.h"
34

    
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#define TARGET_HAS_ICE 1
36

    
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#define ELF_MACHINE     EM_ALPHA
38

    
39
#define ICACHE_LINE_SIZE 32
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#define DCACHE_LINE_SIZE 32
41

    
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#define TARGET_PAGE_BITS 13
43

    
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/* ??? EV4 has 34 phys addr bits, EV5 has 40, EV6 has 44.  */
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#define TARGET_PHYS_ADDR_SPACE_BITS        44
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#define TARGET_VIRT_ADDR_SPACE_BITS        (30 + TARGET_PAGE_BITS)
47

    
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/* Alpha major type */
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enum {
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    ALPHA_EV3  = 1,
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    ALPHA_EV4  = 2,
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    ALPHA_SIM  = 3,
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    ALPHA_LCA  = 4,
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    ALPHA_EV5  = 5, /* 21164 */
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    ALPHA_EV45 = 6, /* 21064A */
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    ALPHA_EV56 = 7, /* 21164A */
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};
58

    
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/* EV4 minor type */
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enum {
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    ALPHA_EV4_2 = 0,
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    ALPHA_EV4_3 = 1,
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};
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/* LCA minor type */
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enum {
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    ALPHA_LCA_1 = 1, /* 21066 */
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    ALPHA_LCA_2 = 2, /* 20166 */
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    ALPHA_LCA_3 = 3, /* 21068 */
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    ALPHA_LCA_4 = 4, /* 21068 */
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    ALPHA_LCA_5 = 5, /* 21066A */
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    ALPHA_LCA_6 = 6, /* 21068A */
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};
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/* EV5 minor type */
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enum {
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    ALPHA_EV5_1 = 1, /* Rev BA, CA */
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    ALPHA_EV5_2 = 2, /* Rev DA, EA */
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    ALPHA_EV5_3 = 3, /* Pass 3 */
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    ALPHA_EV5_4 = 4, /* Pass 3.2 */
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    ALPHA_EV5_5 = 5, /* Pass 4 */
82
};
83

    
84
/* EV45 minor type */
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enum {
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    ALPHA_EV45_1 = 1, /* Pass 1 */
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    ALPHA_EV45_2 = 2, /* Pass 1.1 */
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    ALPHA_EV45_3 = 3, /* Pass 2 */
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};
90

    
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/* EV56 minor type */
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enum {
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    ALPHA_EV56_1 = 1, /* Pass 1 */
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    ALPHA_EV56_2 = 2, /* Pass 2 */
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};
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97
enum {
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    IMPLVER_2106x = 0, /* EV4, EV45 & LCA45 */
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    IMPLVER_21164 = 1, /* EV5, EV56 & PCA45 */
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    IMPLVER_21264 = 2, /* EV6, EV67 & EV68x */
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    IMPLVER_21364 = 3, /* EV7 & EV79 */
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};
103

    
104
enum {
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    AMASK_BWX      = 0x00000001,
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    AMASK_FIX      = 0x00000002,
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    AMASK_CIX      = 0x00000004,
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    AMASK_MVI      = 0x00000100,
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    AMASK_TRAP     = 0x00000200,
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    AMASK_PREFETCH = 0x00001000,
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};
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113
enum {
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    VAX_ROUND_NORMAL = 0,
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    VAX_ROUND_CHOPPED,
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};
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118
enum {
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    IEEE_ROUND_NORMAL = 0,
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    IEEE_ROUND_DYNAMIC,
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    IEEE_ROUND_PLUS,
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    IEEE_ROUND_MINUS,
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    IEEE_ROUND_CHOPPED,
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};
125

    
126
/* IEEE floating-point operations encoding */
127
/* Trap mode */
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enum {
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    FP_TRAP_I   = 0x0,
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    FP_TRAP_U   = 0x1,
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    FP_TRAP_S  = 0x4,
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    FP_TRAP_SU  = 0x5,
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    FP_TRAP_SUI = 0x7,
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};
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/* Rounding mode */
137
enum {
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    FP_ROUND_CHOPPED = 0x0,
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    FP_ROUND_MINUS   = 0x1,
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    FP_ROUND_NORMAL  = 0x2,
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    FP_ROUND_DYNAMIC = 0x3,
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};
143

    
144
/* FPCR bits */
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#define FPCR_SUM                (1ULL << 63)
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#define FPCR_INED                (1ULL << 62)
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#define FPCR_UNFD                (1ULL << 61)
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#define FPCR_UNDZ                (1ULL << 60)
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#define FPCR_DYN_SHIFT                58
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#define FPCR_DYN_CHOPPED        (0ULL << FPCR_DYN_SHIFT)
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#define FPCR_DYN_MINUS                (1ULL << FPCR_DYN_SHIFT)
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#define FPCR_DYN_NORMAL                (2ULL << FPCR_DYN_SHIFT)
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#define FPCR_DYN_PLUS                (3ULL << FPCR_DYN_SHIFT)
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#define FPCR_DYN_MASK                (3ULL << FPCR_DYN_SHIFT)
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#define FPCR_IOV                (1ULL << 57)
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#define FPCR_INE                (1ULL << 56)
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#define FPCR_UNF                (1ULL << 55)
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#define FPCR_OVF                (1ULL << 54)
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#define FPCR_DZE                (1ULL << 53)
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#define FPCR_INV                (1ULL << 52)
161
#define FPCR_OVFD                (1ULL << 51)
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#define FPCR_DZED                (1ULL << 50)
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#define FPCR_INVD                (1ULL << 49)
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#define FPCR_DNZ                (1ULL << 48)
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#define FPCR_DNOD                (1ULL << 47)
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#define FPCR_STATUS_MASK        (FPCR_IOV | FPCR_INE | FPCR_UNF \
167
                                 | FPCR_OVF | FPCR_DZE | FPCR_INV)
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169
/* The silly software trap enables implemented by the kernel emulation.
170
   These are more or less architecturally required, since the real hardware
171
   has read-as-zero bits in the FPCR when the features aren't implemented.
172
   For the purposes of QEMU, we pretend the FPCR can hold everything.  */
173
#define SWCR_TRAP_ENABLE_INV        (1ULL << 1)
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#define SWCR_TRAP_ENABLE_DZE        (1ULL << 2)
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#define SWCR_TRAP_ENABLE_OVF        (1ULL << 3)
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#define SWCR_TRAP_ENABLE_UNF        (1ULL << 4)
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#define SWCR_TRAP_ENABLE_INE        (1ULL << 5)
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#define SWCR_TRAP_ENABLE_DNO        (1ULL << 6)
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#define SWCR_TRAP_ENABLE_MASK        ((1ULL << 7) - (1ULL << 1))
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181
#define SWCR_MAP_DMZ                (1ULL << 12)
182
#define SWCR_MAP_UMZ                (1ULL << 13)
183
#define SWCR_MAP_MASK                (SWCR_MAP_DMZ | SWCR_MAP_UMZ)
184

    
185
#define SWCR_STATUS_INV                (1ULL << 17)
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#define SWCR_STATUS_DZE                (1ULL << 18)
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#define SWCR_STATUS_OVF                (1ULL << 19)
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#define SWCR_STATUS_UNF                (1ULL << 20)
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#define SWCR_STATUS_INE                (1ULL << 21)
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#define SWCR_STATUS_DNO                (1ULL << 22)
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#define SWCR_STATUS_MASK        ((1ULL << 23) - (1ULL << 17))
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193
#define SWCR_MASK  (SWCR_TRAP_ENABLE_MASK | SWCR_MAP_MASK | SWCR_STATUS_MASK)
194

    
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/* Internal processor registers */
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/* XXX: TOFIX: most of those registers are implementation dependant */
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enum {
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#if defined(CONFIG_USER_ONLY)
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    IPR_EXC_ADDR,
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    IPR_EXC_SUM,
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    IPR_EXC_MASK,
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#else
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    /* Ebox IPRs */
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    IPR_CC           = 0xC0,            /* 21264 */
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    IPR_CC_CTL       = 0xC1,            /* 21264 */
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#define IPR_CC_CTL_ENA_SHIFT 32
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#define IPR_CC_CTL_COUNTER_MASK 0xfffffff0UL
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    IPR_VA           = 0xC2,            /* 21264 */
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    IPR_VA_CTL       = 0xC4,            /* 21264 */
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#define IPR_VA_CTL_VA_48_SHIFT 1
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#define IPR_VA_CTL_VPTB_SHIFT 30
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    IPR_VA_FORM      = 0xC3,            /* 21264 */
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    /* Ibox IPRs */
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    IPR_ITB_TAG      = 0x00,            /* 21264 */
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    IPR_ITB_PTE      = 0x01,            /* 21264 */
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    IPR_ITB_IAP      = 0x02,
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    IPR_ITB_IA       = 0x03,            /* 21264 */
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    IPR_ITB_IS       = 0x04,            /* 21264 */
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    IPR_PMPC         = 0x05,
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    IPR_EXC_ADDR     = 0x06,            /* 21264 */
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    IPR_IVA_FORM     = 0x07,            /* 21264 */
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    IPR_CM           = 0x09,            /* 21264 */
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#define IPR_CM_SHIFT 3
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#define IPR_CM_MASK (3ULL << IPR_CM_SHIFT)      /* 21264 */
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    IPR_IER          = 0x0A,            /* 21264 */
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#define IPR_IER_MASK 0x0000007fffffe000ULL
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    IPR_IER_CM       = 0x0B,            /* 21264: = CM | IER */
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    IPR_SIRR         = 0x0C,            /* 21264 */
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#define IPR_SIRR_SHIFT 14
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#define IPR_SIRR_MASK 0x7fff
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    IPR_ISUM         = 0x0D,            /* 21264 */
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    IPR_HW_INT_CLR   = 0x0E,            /* 21264 */
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    IPR_EXC_SUM      = 0x0F,
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    IPR_PAL_BASE     = 0x10,
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    IPR_I_CTL        = 0x11,
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#define IPR_I_CTL_CHIP_ID_SHIFT 24      /* 21264 */
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#define IPR_I_CTL_BIST_FAIL (1 << 23)   /* 21264 */
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#define IPR_I_CTL_IC_EN_SHIFT 2         /* 21264 */
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#define IPR_I_CTL_SDE1_SHIFT 7          /* 21264 */
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#define IPR_I_CTL_HWE_SHIFT 12          /* 21264 */
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#define IPR_I_CTL_VA_48_SHIFT 15        /* 21264 */
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#define IPR_I_CTL_SPE_SHIFT 3           /* 21264 */
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#define IPR_I_CTL_CALL_PAL_R23_SHIFT 20 /* 21264 */
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    IPR_I_STAT       = 0x16,            /* 21264 */
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    IPR_IC_FLUSH     = 0x13,            /* 21264 */
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    IPR_IC_FLUSH_ASM = 0x12,            /* 21264 */
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    IPR_CLR_MAP      = 0x15,
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    IPR_SLEEP        = 0x17,
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    IPR_PCTX         = 0x40,
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    IPR_PCTX_ASN       = 0x01,  /* field */
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#define IPR_PCTX_ASN_SHIFT 39
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    IPR_PCTX_ASTER     = 0x02,  /* field */
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#define IPR_PCTX_ASTER_SHIFT 5
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    IPR_PCTX_ASTRR     = 0x04,  /* field */
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#define IPR_PCTX_ASTRR_SHIFT 9
256
    IPR_PCTX_PPCE      = 0x08,  /* field */
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#define IPR_PCTX_PPCE_SHIFT 1
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    IPR_PCTX_FPE       = 0x10,  /* field */
259
#define IPR_PCTX_FPE_SHIFT 2
260
    IPR_PCTX_ALL       = 0x5f,  /* all fields */
261
    IPR_PCTR_CTL     = 0x14,            /* 21264 */
262
    /* Mbox IPRs */
263
    IPR_DTB_TAG0     = 0x20,            /* 21264 */
264
    IPR_DTB_TAG1     = 0xA0,            /* 21264 */
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    IPR_DTB_PTE0     = 0x21,            /* 21264 */
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    IPR_DTB_PTE1     = 0xA1,            /* 21264 */
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    IPR_DTB_ALTMODE  = 0xA6,
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    IPR_DTB_ALTMODE0 = 0x26,            /* 21264 */
269
#define IPR_DTB_ALTMODE_MASK 3
270
    IPR_DTB_IAP      = 0xA2,
271
    IPR_DTB_IA       = 0xA3,            /* 21264 */
272
    IPR_DTB_IS0      = 0x24,
273
    IPR_DTB_IS1      = 0xA4,
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    IPR_DTB_ASN0     = 0x25,            /* 21264 */
275
    IPR_DTB_ASN1     = 0xA5,            /* 21264 */
276
#define IPR_DTB_ASN_SHIFT 56
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    IPR_MM_STAT      = 0x27,            /* 21264 */
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    IPR_M_CTL        = 0x28,            /* 21264 */
279
#define IPR_M_CTL_SPE_SHIFT 1
280
#define IPR_M_CTL_SPE_MASK 7
281
    IPR_DC_CTL       = 0x29,            /* 21264 */
282
    IPR_DC_STAT      = 0x2A,            /* 21264 */
283
    /* Cbox IPRs */
284
    IPR_C_DATA       = 0x2B,
285
    IPR_C_SHIFT      = 0x2C,
286

    
287
    IPR_ASN,
288
    IPR_ASTEN,
289
    IPR_ASTSR,
290
    IPR_DATFX,
291
    IPR_ESP,
292
    IPR_FEN,
293
    IPR_IPIR,
294
    IPR_IPL,
295
    IPR_KSP,
296
    IPR_MCES,
297
    IPR_PERFMON,
298
    IPR_PCBB,
299
    IPR_PRBR,
300
    IPR_PTBR,
301
    IPR_SCBB,
302
    IPR_SISR,
303
    IPR_SSP,
304
    IPR_SYSPTBR,
305
    IPR_TBCHK,
306
    IPR_TBIA,
307
    IPR_TBIAP,
308
    IPR_TBIS,
309
    IPR_TBISD,
310
    IPR_TBISI,
311
    IPR_USP,
312
    IPR_VIRBND,
313
    IPR_VPTB,
314
    IPR_WHAMI,
315
    IPR_ALT_MODE,
316
#endif
317
    IPR_LAST,
318
};
319

    
320
typedef struct CPUAlphaState CPUAlphaState;
321

    
322
#define NB_MMU_MODES 4
323

    
324
struct CPUAlphaState {
325
    uint64_t ir[31];
326
    float64 fir[31];
327
    uint64_t pc;
328
    uint64_t ipr[IPR_LAST];
329
    uint64_t ps;
330
    uint64_t unique;
331
    uint64_t lock_addr;
332
    uint64_t lock_st_addr;
333
    uint64_t lock_value;
334
    float_status fp_status;
335
    /* The following fields make up the FPCR, but in FP_STATUS format.  */
336
    uint8_t fpcr_exc_status;
337
    uint8_t fpcr_exc_mask;
338
    uint8_t fpcr_dyn_round;
339
    uint8_t fpcr_flush_to_zero;
340
    uint8_t fpcr_dnz;
341
    uint8_t fpcr_dnod;
342
    uint8_t fpcr_undz;
343

    
344
    /* Used for HW_LD / HW_ST */
345
    uint8_t saved_mode;
346
    /* For RC and RS */
347
    uint8_t intr_flag;
348

    
349
#if TARGET_LONG_BITS > HOST_LONG_BITS
350
    /* temporary fixed-point registers
351
     * used to emulate 64 bits target on 32 bits hosts
352
     */
353
    target_ulong t0, t1;
354
#endif
355

    
356
    /* Those resources are used only in Qemu core */
357
    CPU_COMMON
358

    
359
    uint32_t hflags;
360

    
361
    int error_code;
362

    
363
    uint32_t features;
364
    uint32_t amask;
365
    int implver;
366
};
367

    
368
#define cpu_init cpu_alpha_init
369
#define cpu_exec cpu_alpha_exec
370
#define cpu_gen_code cpu_alpha_gen_code
371
#define cpu_signal_handler cpu_alpha_signal_handler
372

    
373
/* MMU modes definitions */
374
#define MMU_MODE0_SUFFIX _kernel
375
#define MMU_MODE1_SUFFIX _executive
376
#define MMU_MODE2_SUFFIX _supervisor
377
#define MMU_MODE3_SUFFIX _user
378
#define MMU_USER_IDX 3
379
static inline int cpu_mmu_index (CPUState *env)
380
{
381
    return (env->ps >> 3) & 3;
382
}
383

    
384
#include "cpu-all.h"
385

    
386
enum {
387
    FEATURE_ASN    = 0x00000001,
388
    FEATURE_SPS    = 0x00000002,
389
    FEATURE_VIRBND = 0x00000004,
390
    FEATURE_TBCHK  = 0x00000008,
391
};
392

    
393
enum {
394
    EXCP_RESET            = 0x0000,
395
    EXCP_MCHK             = 0x0020,
396
    EXCP_ARITH            = 0x0060,
397
    EXCP_HW_INTERRUPT     = 0x00E0,
398
    EXCP_DFAULT           = 0x01E0,
399
    EXCP_DTB_MISS_PAL     = 0x09E0,
400
    EXCP_ITB_MISS         = 0x03E0,
401
    EXCP_ITB_ACV          = 0x07E0,
402
    EXCP_DTB_MISS_NATIVE  = 0x08E0,
403
    EXCP_UNALIGN          = 0x11E0,
404
    EXCP_OPCDEC           = 0x13E0,
405
    EXCP_FEN              = 0x17E0,
406
    EXCP_CALL_PAL         = 0x2000,
407
    EXCP_CALL_PALP        = 0x3000,
408
    EXCP_CALL_PALE        = 0x4000,
409
    /* Pseudo exception for console */
410
    EXCP_CONSOLE_DISPATCH = 0x4001,
411
    EXCP_CONSOLE_FIXUP    = 0x4002,
412
    EXCP_STL_C            = 0x4003,
413
    EXCP_STQ_C            = 0x4004,
414
};
415

    
416
/* Arithmetic exception */
417
#define EXC_M_IOV       (1<<16)         /* Integer Overflow */
418
#define EXC_M_INE       (1<<15)         /* Inexact result */
419
#define EXC_M_UNF       (1<<14)         /* Underflow */
420
#define EXC_M_FOV       (1<<13)         /* Overflow */
421
#define EXC_M_DZE       (1<<12)         /* Division by zero */
422
#define EXC_M_INV       (1<<11)         /* Invalid operation */
423
#define EXC_M_SWC       (1<<10)         /* Software completion */
424

    
425
enum {
426
    IR_V0   = 0,
427
    IR_T0   = 1,
428
    IR_T1   = 2,
429
    IR_T2   = 3,
430
    IR_T3   = 4,
431
    IR_T4   = 5,
432
    IR_T5   = 6,
433
    IR_T6   = 7,
434
    IR_T7   = 8,
435
    IR_S0   = 9,
436
    IR_S1   = 10,
437
    IR_S2   = 11,
438
    IR_S3   = 12,
439
    IR_S4   = 13,
440
    IR_S5   = 14,
441
    IR_S6   = 15,
442
    IR_FP   = IR_S6,
443
    IR_A0   = 16,
444
    IR_A1   = 17,
445
    IR_A2   = 18,
446
    IR_A3   = 19,
447
    IR_A4   = 20,
448
    IR_A5   = 21,
449
    IR_T8   = 22,
450
    IR_T9   = 23,
451
    IR_T10  = 24,
452
    IR_T11  = 25,
453
    IR_RA   = 26,
454
    IR_T12  = 27,
455
    IR_PV   = IR_T12,
456
    IR_AT   = 28,
457
    IR_GP   = 29,
458
    IR_SP   = 30,
459
    IR_ZERO = 31,
460
};
461

    
462
CPUAlphaState * cpu_alpha_init (const char *cpu_model);
463
int cpu_alpha_exec(CPUAlphaState *s);
464
/* you can call this signal handler from your SIGBUS and SIGSEGV
465
   signal handlers to inform the virtual CPU of exceptions. non zero
466
   is returned if the signal was handled by the virtual CPU.  */
467
int cpu_alpha_signal_handler(int host_signum, void *pinfo,
468
                             void *puc);
469
int cpu_alpha_handle_mmu_fault (CPUState *env, uint64_t address, int rw,
470
                                int mmu_idx, int is_softmmu);
471
#define cpu_handle_mmu_fault cpu_alpha_handle_mmu_fault
472
void do_interrupt (CPUState *env);
473

    
474
uint64_t cpu_alpha_load_fpcr (CPUState *env);
475
void cpu_alpha_store_fpcr (CPUState *env, uint64_t val);
476
int cpu_alpha_mfpr (CPUState *env, int iprn, uint64_t *valp);
477
int cpu_alpha_mtpr (CPUState *env, int iprn, uint64_t val, uint64_t *oldvalp);
478

    
479
static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
480
                                        target_ulong *cs_base, int *flags)
481
{
482
    *pc = env->pc;
483
    *cs_base = 0;
484
    *flags = env->ps;
485
}
486

    
487
#if defined(CONFIG_USER_ONLY)
488
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
489
{
490
    if (newsp) {
491
        env->ir[IR_SP] = newsp;
492
    }
493
    env->ir[IR_V0] = 0;
494
    env->ir[IR_A3] = 0;
495
}
496

    
497
static inline void cpu_set_tls(CPUState *env, target_ulong newtls)
498
{
499
    env->unique = newtls;
500
}
501
#endif
502

    
503
#endif /* !defined (__CPU_ALPHA_H__) */