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/*
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* QEMU Malta board support
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*
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* Copyright (c) 2006 Aurelien Jarno
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "vl.h" |
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#ifdef TARGET_WORDS_BIGENDIAN
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#define BIOS_FILENAME "mips_bios.bin" |
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#else
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#define BIOS_FILENAME "mipsel_bios.bin" |
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#endif
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#ifdef MIPS_HAS_MIPS64
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#define INITRD_LOAD_ADDR (int64_t)0x80800000 |
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#else
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#define INITRD_LOAD_ADDR (int32_t)0x80800000 |
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#endif
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#define ENVP_ADDR (int32_t)0x80002000 |
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#define VIRT_TO_PHYS_ADDEND (-((int64_t)(int32_t)0x80000000)) |
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|
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#define ENVP_NB_ENTRIES 16 |
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#define ENVP_ENTRY_SIZE 256 |
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extern FILE *logfile;
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typedef struct { |
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uint32_t leds; |
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uint32_t brk; |
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uint32_t gpout; |
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uint32_t i2coe; |
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uint32_t i2cout; |
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uint32_t i2csel; |
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CharDriverState *display; |
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char display_text[9]; |
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} MaltaFPGAState; |
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static PITState *pit;
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/* The 8259 is attached to the MIPS CPU INT0 pin, ie interrupt 2 */
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static void pic_irq_request(void *opaque, int level) |
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{ |
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cpu_mips_irq_request(opaque, 2, level);
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} |
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/* Malta FPGA */
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static void malta_fpga_update_display(void *opaque) |
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{ |
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char leds_text[9]; |
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int i;
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MaltaFPGAState *s = opaque; |
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for (i = 7 ; i >= 0 ; i--) { |
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if (s->leds & (1 << i)) |
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leds_text[i] = '#';
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else
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leds_text[i] = ' ';
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} |
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leds_text[8] = '\0'; |
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qemu_chr_printf(s->display, "\e[H\n\n|\e[32m%-8.8s\e[00m|\r\n", leds_text); |
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qemu_chr_printf(s->display, "\n\n\n\n|\e[31m%-8.8s\e[00m|", s->display_text); |
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} |
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static uint32_t malta_fpga_readl(void *opaque, target_phys_addr_t addr) |
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{ |
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MaltaFPGAState *s = opaque; |
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uint32_t val = 0;
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uint32_t saddr; |
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200: |
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val = 0x00000000; /* All switches closed */ |
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break;
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|
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/* STATUS Register */
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case 0x00208: |
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#ifdef TARGET_WORDS_BIGENDIAN
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val = 0x00000012;
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#else
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val = 0x00000010;
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#endif
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break;
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/* JMPRS Register */
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case 0x00210: |
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val = 0x00;
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break;
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/* LEDBAR Register */
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case 0x00408: |
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val = s->leds; |
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break;
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/* BRKRES Register */
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case 0x00508: |
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val = s->brk; |
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break;
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/* GPOUT Register */
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case 0x00a00: |
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val = s->gpout; |
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break;
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/* XXX: implement a real I2C controller */
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/* GPINP Register */
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case 0x00a08: |
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/* IN = OUT until a real I2C control is implemented */
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if (s->i2csel)
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val = s->i2cout; |
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else
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val = 0x00;
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break;
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/* I2CINP Register */
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case 0x00b00: |
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val = 0x00000003;
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break;
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/* I2COE Register */
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case 0x00b08: |
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val = s->i2coe; |
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break;
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/* I2COUT Register */
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case 0x00b10: |
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val = s->i2cout; |
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break;
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/* I2CSEL Register */
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case 0x00b18: |
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val = s->i2cout; |
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break;
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default:
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#if 0
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printf ("malta_fpga_read: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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#endif
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break;
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} |
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return val;
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} |
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static void malta_fpga_writel(void *opaque, target_phys_addr_t addr, |
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uint32_t val) |
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{ |
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MaltaFPGAState *s = opaque; |
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uint32_t saddr; |
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saddr = (addr & 0xfffff);
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switch (saddr) {
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/* SWITCH Register */
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case 0x00200: |
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break;
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/* JMPRS Register */
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case 0x00210: |
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break;
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/* LEDBAR Register */
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/* XXX: implement a 8-LED array */
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case 0x00408: |
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s->leds = val & 0xff;
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break;
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/* ASCIIWORD Register */
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case 0x00410: |
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snprintf(s->display_text, 9, "%08X", val); |
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malta_fpga_update_display(s); |
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break;
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/* ASCIIPOS0 to ASCIIPOS7 Registers */
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case 0x00418: |
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case 0x00420: |
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case 0x00428: |
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case 0x00430: |
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case 0x00438: |
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case 0x00440: |
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case 0x00448: |
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case 0x00450: |
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s->display_text[(saddr - 0x00418) >> 3] = (char) val; |
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malta_fpga_update_display(s); |
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break;
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/* SOFTRES Register */
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case 0x00500: |
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if (val == 0x42) |
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qemu_system_reset_request (); |
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break;
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/* BRKRES Register */
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case 0x00508: |
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s->brk = val & 0xff;
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break;
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/* GPOUT Register */
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case 0x00a00: |
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s->gpout = val & 0xff;
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break;
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/* I2COE Register */
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case 0x00b08: |
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s->i2coe = val & 0x03;
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break;
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/* I2COUT Register */
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case 0x00b10: |
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s->i2cout = val & 0x03;
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break;
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/* I2CSEL Register */
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case 0x00b18: |
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s->i2cout = val & 0x01;
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break;
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default:
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#if 0
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printf ("malta_fpga_write: Bad register offset 0x" TARGET_FMT_lx "\n",
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addr);
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#endif
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break;
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} |
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} |
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static CPUReadMemoryFunc *malta_fpga_read[] = {
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malta_fpga_readl, |
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malta_fpga_readl, |
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malta_fpga_readl |
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}; |
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static CPUWriteMemoryFunc *malta_fpga_write[] = {
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malta_fpga_writel, |
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malta_fpga_writel, |
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malta_fpga_writel |
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}; |
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void malta_fpga_reset(void *opaque) |
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{ |
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MaltaFPGAState *s = opaque; |
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s->leds = 0x00;
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s->brk = 0x0a;
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s->gpout = 0x00;
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s->i2coe = 0x0;
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s->i2cout = 0x3;
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s->i2csel = 0x1;
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s->display_text[8] = '\0'; |
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snprintf(s->display_text, 9, " "); |
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malta_fpga_update_display(s); |
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} |
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MaltaFPGAState *malta_fpga_init(target_phys_addr_t base) |
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{ |
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MaltaFPGAState *s; |
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int malta;
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s = (MaltaFPGAState *)qemu_mallocz(sizeof(MaltaFPGAState));
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malta = cpu_register_io_memory(0, malta_fpga_read,
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malta_fpga_write, s); |
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cpu_register_physical_memory(base, 0x100000, malta);
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s->display = qemu_chr_open("vc");
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qemu_chr_printf(s->display, "\e[HMalta LEDBAR\r\n"); |
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "\n");
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qemu_chr_printf(s->display, "Malta ASCII\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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qemu_chr_printf(s->display, "+ +\r\n");
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qemu_chr_printf(s->display, "+--------+\r\n");
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malta_fpga_reset(s); |
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qemu_register_reset(malta_fpga_reset, s); |
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return s;
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} |
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/* Audio support */
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#ifdef HAS_AUDIO
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static void audio_init (PCIBus *pci_bus) |
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{ |
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struct soundhw *c;
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int audio_enabled = 0; |
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for (c = soundhw; !audio_enabled && c->name; ++c) {
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audio_enabled = c->enabled; |
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} |
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if (audio_enabled) {
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AudioState *s; |
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s = AUD_init (); |
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if (s) {
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for (c = soundhw; c->name; ++c) {
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if (c->enabled) {
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if (c->isa) {
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fprintf(stderr, "qemu: Unsupported Sound Card: %s\n", c->name);
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exit(1);
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} |
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else {
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if (pci_bus) {
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c->init.init_pci (pci_bus, s); |
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} |
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} |
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} |
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} |
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} |
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} |
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} |
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#endif
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/* Network support */
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static void network_init (PCIBus *pci_bus) |
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{ |
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int i;
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NICInfo *nd; |
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for(i = 0; i < nb_nics; i++) { |
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nd = &nd_table[i]; |
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if (!nd->model) {
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nd->model = "pcnet";
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} |
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if (i == 0 && strcmp(nd->model, "pcnet") == 0) { |
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/* The malta board has a PCNet card using PCI SLOT 11 */
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pci_nic_init(pci_bus, nd, 88);
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} else {
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pci_nic_init(pci_bus, nd, -1);
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} |
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} |
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} |
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/* ROM and pseudo bootloader
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The following code implements a very very simple bootloader. It first
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loads the registers a0 to a3 to the values expected by the OS, and
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then jump at the kernel address.
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The bootloader should pass the locations of the kernel arguments and
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environment variables tables. Those tables contain the 32-bit address
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of NULL terminated strings. The environment variables table should be
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terminated by a NULL address.
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For a simpler implementation, the number of kernel arguments is fixed
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to two (the name of the kernel and the command line), and the two
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tables are actually the same one.
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The registers a0 to a3 should contain the following values:
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a0 - number of kernel arguments
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a1 - 32-bit address of the kernel arguments table
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a2 - 32-bit address of the environment variables table
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a3 - RAM size in bytes
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*/
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|
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static void write_bootloader (CPUState *env, unsigned long bios_offset, int64_t kernel_addr) |
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{ |
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uint32_t *p; |
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/* Small bootloader */
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p = (uint32_t *) (phys_ram_base + bios_offset); |
392 |
stl_raw(p++, 0x0bf00010); /* j 0x1fc00040 */ |
393 |
stl_raw(p++, 0x00000000); /* nop */ |
394 |
|
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/* Second part of the bootloader */
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p = (uint32_t *) (phys_ram_base + bios_offset + 0x040);
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stl_raw(p++, 0x3c040000); /* lui a0, 0 */ |
398 |
stl_raw(p++, 0x34840002); /* ori a0, a0, 2 */ |
399 |
stl_raw(p++, 0x3c050000 | ((ENVP_ADDR >> 16) & 0xffff)); /* lui a1, high(ENVP_ADDR) */ |
400 |
stl_raw(p++, 0x34a50000 | (ENVP_ADDR & 0xffff)); /* ori a1, a0, low(ENVP_ADDR) */ |
401 |
stl_raw(p++, 0x3c060000 | (((ENVP_ADDR + 8) >> 16) & 0xffff)); /* lui a2, high(ENVP_ADDR + 8) */ |
402 |
stl_raw(p++, 0x34c60000 | ((ENVP_ADDR + 8) & 0xffff)); /* ori a2, a2, low(ENVP_ADDR + 8) */ |
403 |
stl_raw(p++, 0x3c070000 | (env->ram_size >> 16)); /* lui a3, high(env->ram_size) */ |
404 |
stl_raw(p++, 0x34e70000 | (env->ram_size & 0xffff)); /* ori a3, a3, low(env->ram_size) */ |
405 |
stl_raw(p++, 0x3c1f0000 | ((kernel_addr >> 16) & 0xffff)); /* lui ra, high(kernel_addr) */; |
406 |
stl_raw(p++, 0x37ff0000 | (kernel_addr & 0xffff)); /* ori ra, ra, low(kernel_addr) */ |
407 |
stl_raw(p++, 0x03e00008); /* jr ra */ |
408 |
stl_raw(p++, 0x00000000); /* nop */ |
409 |
} |
410 |
|
411 |
static void prom_set(int index, const char *string, ...) |
412 |
{ |
413 |
va_list ap; |
414 |
int32_t *p; |
415 |
int32_t table_addr; |
416 |
char *s;
|
417 |
|
418 |
if (index >= ENVP_NB_ENTRIES)
|
419 |
return;
|
420 |
|
421 |
p = (int32_t *) (phys_ram_base + ENVP_ADDR + VIRT_TO_PHYS_ADDEND); |
422 |
p += index; |
423 |
|
424 |
if (string == NULL) { |
425 |
stl_raw(p, 0);
|
426 |
return;
|
427 |
} |
428 |
|
429 |
table_addr = ENVP_ADDR + sizeof(int32_t) * ENVP_NB_ENTRIES + index * ENVP_ENTRY_SIZE;
|
430 |
s = (char *) (phys_ram_base + VIRT_TO_PHYS_ADDEND + table_addr);
|
431 |
|
432 |
stl_raw(p, table_addr); |
433 |
|
434 |
va_start(ap, string); |
435 |
vsnprintf (s, ENVP_ENTRY_SIZE, string, ap); |
436 |
va_end(ap); |
437 |
} |
438 |
|
439 |
/* Kernel */
|
440 |
static int64_t load_kernel (CPUState *env)
|
441 |
{ |
442 |
int64_t kernel_addr = 0;
|
443 |
int index = 0; |
444 |
long initrd_size;
|
445 |
|
446 |
if (load_elf(env->kernel_filename, VIRT_TO_PHYS_ADDEND, &kernel_addr) < 0) { |
447 |
fprintf(stderr, "qemu: could not load kernel '%s'\n",
|
448 |
env->kernel_filename); |
449 |
exit(1);
|
450 |
} |
451 |
|
452 |
/* load initrd */
|
453 |
initrd_size = 0;
|
454 |
if (env->initrd_filename) {
|
455 |
initrd_size = load_image(env->initrd_filename, |
456 |
phys_ram_base + INITRD_LOAD_ADDR + VIRT_TO_PHYS_ADDEND); |
457 |
if (initrd_size == (target_ulong) -1) { |
458 |
fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
|
459 |
env->initrd_filename); |
460 |
exit(1);
|
461 |
} |
462 |
} |
463 |
|
464 |
/* Store command line. */
|
465 |
prom_set(index++, env->kernel_filename); |
466 |
if (initrd_size > 0) |
467 |
prom_set(index++, "rd_start=0x" TARGET_FMT_lx " rd_size=%li %s", INITRD_LOAD_ADDR, initrd_size, env->kernel_cmdline); |
468 |
else
|
469 |
prom_set(index++, env->kernel_cmdline); |
470 |
|
471 |
/* Setup minimum environment variables */
|
472 |
prom_set(index++, "memsize");
|
473 |
prom_set(index++, "%i", env->ram_size);
|
474 |
prom_set(index++, "modetty0");
|
475 |
prom_set(index++, "38400n8r");
|
476 |
prom_set(index++, NULL);
|
477 |
|
478 |
return kernel_addr;
|
479 |
} |
480 |
|
481 |
static void main_cpu_reset(void *opaque) |
482 |
{ |
483 |
CPUState *env = opaque; |
484 |
cpu_reset(env); |
485 |
|
486 |
/* The bootload does not need to be rewritten as it is located in a
|
487 |
read only location. The kernel location and the arguments table
|
488 |
location does not change. */
|
489 |
if (env->kernel_filename)
|
490 |
load_kernel (env); |
491 |
} |
492 |
|
493 |
static
|
494 |
void mips_malta_init (int ram_size, int vga_ram_size, int boot_device, |
495 |
DisplayState *ds, const char **fd_filename, int snapshot, |
496 |
const char *kernel_filename, const char *kernel_cmdline, |
497 |
const char *initrd_filename) |
498 |
{ |
499 |
char buf[1024]; |
500 |
unsigned long bios_offset; |
501 |
int64_t kernel_addr; |
502 |
PCIBus *pci_bus; |
503 |
CPUState *env; |
504 |
RTCState *rtc_state; |
505 |
/* fdctrl_t *floppy_controller; */
|
506 |
MaltaFPGAState *malta_fpga; |
507 |
int ret;
|
508 |
|
509 |
env = cpu_init(); |
510 |
register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
511 |
qemu_register_reset(main_cpu_reset, env); |
512 |
|
513 |
/* allocate RAM */
|
514 |
cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
515 |
|
516 |
/* Map the bios at two physical locations, as on the real board */
|
517 |
bios_offset = ram_size + vga_ram_size; |
518 |
cpu_register_physical_memory(0x1e000000LL,
|
519 |
BIOS_SIZE, bios_offset | IO_MEM_ROM); |
520 |
cpu_register_physical_memory(0x1fc00000LL,
|
521 |
BIOS_SIZE, bios_offset | IO_MEM_ROM); |
522 |
|
523 |
/* Load a BIOS image except if a kernel image has been specified. In
|
524 |
the later case, just write a small bootloader to the flash
|
525 |
location. */
|
526 |
if (kernel_filename) {
|
527 |
env->ram_size = ram_size; |
528 |
env->kernel_filename = kernel_filename; |
529 |
env->kernel_cmdline = kernel_cmdline; |
530 |
env->initrd_filename = initrd_filename; |
531 |
kernel_addr = load_kernel(env); |
532 |
write_bootloader(env, bios_offset, kernel_addr); |
533 |
} else {
|
534 |
snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
535 |
ret = load_image(buf, phys_ram_base + bios_offset); |
536 |
if (ret != BIOS_SIZE) {
|
537 |
fprintf(stderr, "qemu: Warning, could not load MIPS bios '%s'\n",
|
538 |
buf); |
539 |
exit(1);
|
540 |
} |
541 |
} |
542 |
|
543 |
/* Board ID = 0x420 (Malta Board with CoreLV)
|
544 |
XXX: theoretically 0x1e000010 should map to flash and 0x1fc00010 should
|
545 |
map to the board ID. */
|
546 |
stl_raw(phys_ram_base + bios_offset + 0x10, 0x00000420); |
547 |
|
548 |
/* Init internal devices */
|
549 |
cpu_mips_clock_init(env); |
550 |
cpu_mips_irqctrl_init(); |
551 |
|
552 |
/* FPGA */
|
553 |
malta_fpga = malta_fpga_init(0x1f000000LL);
|
554 |
|
555 |
/* Interrupt controller */
|
556 |
isa_pic = pic_init(pic_irq_request, env); |
557 |
|
558 |
/* Northbridge */
|
559 |
pci_bus = pci_gt64120_init(isa_pic); |
560 |
|
561 |
/* Southbridge */
|
562 |
piix4_init(pci_bus, 80);
|
563 |
pci_piix3_ide_init(pci_bus, bs_table, 81);
|
564 |
usb_uhci_init(pci_bus, 82);
|
565 |
piix4_pm_init(pci_bus, 83);
|
566 |
pit = pit_init(0x40, 0); |
567 |
DMA_init(0);
|
568 |
|
569 |
/* Super I/O */
|
570 |
kbd_init(); |
571 |
rtc_state = rtc_init(0x70, 8); |
572 |
serial_init(&pic_set_irq_new, isa_pic, 0x3f8, 4, serial_hds[0]); |
573 |
serial_init(&pic_set_irq_new, isa_pic, 0x2f8, 4, serial_hds[0]); |
574 |
parallel_init(0x378, 7, parallel_hds[0]); |
575 |
/* XXX: The floppy controller does not work correctly, something is
|
576 |
probably wrong.
|
577 |
floppy_controller = fdctrl_init(6, 2, 0, 0x3f0, fd_table); */
|
578 |
|
579 |
/* Sound card */
|
580 |
#ifdef HAS_AUDIO
|
581 |
audio_init(pci_bus); |
582 |
#endif
|
583 |
|
584 |
/* Network card */
|
585 |
network_init(pci_bus); |
586 |
} |
587 |
|
588 |
QEMUMachine mips_malta_machine = { |
589 |
"malta",
|
590 |
"MIPS Malta Core LV",
|
591 |
mips_malta_init, |
592 |
}; |