Archipelago » qemu

/*

 * QEMU PowerPC 405 embedded processors emulation

 *

 * Copyright (c) 2007 Jocelyn Mayer

 *

 * Permission is hereby granted, free of charge, to any person obtaining a copy

 * of this software and associated documentation files (the "Software"), to deal

 * in the Software without restriction, including without limitation the rights

 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell

 * copies of the Software, and to permit persons to whom the Software is

 * furnished to do so, subject to the following conditions:

 *

 * The above copyright notice and this permission notice shall be included in

 * all copies or substantial portions of the Software.

 *

 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR

 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,

 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL

 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER

 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,

 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN

 * THE SOFTWARE.

 */

#include "vl.h"

#include "ppc405.h"

extern int loglevel;

extern FILE *logfile;

//#define DEBUG_MMIO

#define DEBUG_OPBA

#define DEBUG_SDRAM

#define DEBUG_GPIO

#define DEBUG_SERIAL

#define DEBUG_OCM

//#define DEBUG_I2C

#define DEBUG_GPT

#define DEBUG_MAL

#define DEBUG_UIC

#define DEBUG_CLOCKS

//#define DEBUG_UNASSIGNED

/*****************************************************************************/

/* Generic PowerPC 405 processor instanciation */

CPUState *ppc405_init (const unsigned char *cpu_model,

                       clk_setup_t *cpu_clk, clk_setup_t *tb_clk,

                       uint32_t sysclk)

{

    CPUState *env;

    ppc_def_t *def;

    /* init CPUs */

    env = cpu_init();

    qemu_register_reset(&cpu_ppc_reset, env);

    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);

    ppc_find_by_name(cpu_model, &def);

    if (def == NULL) {

        cpu_abort(env, "Unable to find PowerPC %s CPU definition\n",

                  cpu_model);

    }

    cpu_ppc_register(env, def);

    cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */

    cpu_clk->opaque = env;

    /* Set time-base frequency to sysclk */

    tb_clk->cb = ppc_emb_timers_init(env, sysclk);

    tb_clk->opaque = env;

    ppc_dcr_init(env, NULL, NULL);

    return env;

}

ram_addr_t ppc405_set_bootinfo (CPUState *env, ppc4xx_bd_info_t *bd)

{

    ram_addr_t bdloc;

    int i, n;

    /* We put the bd structure at the top of memory */

    bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);

    stl_raw(phys_ram_base + bdloc + 0x00, bd->bi_memstart);

    stl_raw(phys_ram_base + bdloc + 0x04, bd->bi_memsize);

    stl_raw(phys_ram_base + bdloc + 0x08, bd->bi_flashstart);

    stl_raw(phys_ram_base + bdloc + 0x0C, bd->bi_flashsize);

    stl_raw(phys_ram_base + bdloc + 0x10, bd->bi_flashoffset);

    stl_raw(phys_ram_base + bdloc + 0x14, bd->bi_sramstart);

    stl_raw(phys_ram_base + bdloc + 0x18, bd->bi_sramsize);

    stl_raw(phys_ram_base + bdloc + 0x1C, bd->bi_bootflags);

    stl_raw(phys_ram_base + bdloc + 0x20, bd->bi_ipaddr);

    for (i = 0; i < 6; i++)

        stb_raw(phys_ram_base + bdloc + 0x24 + i, bd->bi_enetaddr[i]);

    stw_raw(phys_ram_base + bdloc + 0x2A, bd->bi_ethspeed);

    stl_raw(phys_ram_base + bdloc + 0x2C, bd->bi_intfreq);

    stl_raw(phys_ram_base + bdloc + 0x30, bd->bi_busfreq);

    stl_raw(phys_ram_base + bdloc + 0x34, bd->bi_baudrate);

    for (i = 0; i < 4; i++)

        stb_raw(phys_ram_base + bdloc + 0x38 + i, bd->bi_s_version[i]);

    for (i = 0; i < 32; i++)

        stb_raw(phys_ram_base + bdloc + 0x3C + i, bd->bi_s_version[i]);

    stl_raw(phys_ram_base + bdloc + 0x5C, bd->bi_plb_busfreq);

    stl_raw(phys_ram_base + bdloc + 0x60, bd->bi_pci_busfreq);

    for (i = 0; i < 6; i++)

        stb_raw(phys_ram_base + bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);

    n = 0x6A;

    if (env->spr[SPR_PVR] == CPU_PPC_405EP) {

        for (i = 0; i < 6; i++)

            stb_raw(phys_ram_base + bdloc + n++, bd->bi_pci_enetaddr2[i]);

    }

    stl_raw(phys_ram_base + bdloc + n, bd->bi_opbfreq);

    n += 4;

    for (i = 0; i < 2; i++) {

        stl_raw(phys_ram_base + bdloc + n, bd->bi_iic_fast[i]);

        n += 4;

    }

    return bdloc;

}

/*****************************************************************************/

/* Shared peripherals */

/*****************************************************************************/

/* Fake device used to map multiple devices in a single memory page */

#define MMIO_AREA_BITS 8

#define MMIO_AREA_LEN (1 << MMIO_AREA_BITS)

#define MMIO_AREA_NB (1 << (TARGET_PAGE_BITS - MMIO_AREA_BITS))

#define MMIO_IDX(addr) (((addr) >> MMIO_AREA_BITS) & (MMIO_AREA_NB - 1))

struct ppc4xx_mmio_t {

    target_phys_addr_t base;

    CPUReadMemoryFunc **mem_read[MMIO_AREA_NB];

    CPUWriteMemoryFunc **mem_write[MMIO_AREA_NB];

    void *opaque[MMIO_AREA_NB];

};

static uint32_t unassigned_mmio_readb (void *opaque, target_phys_addr_t addr)

{

#ifdef DEBUG_UNASSIGNED

    ppc4xx_mmio_t *mmio;

    mmio = opaque;

    printf("Unassigned mmio read 0x" PADDRX " base " PADDRX "\n",

           addr, mmio->base);

#endif

    return 0;

}

static void unassigned_mmio_writeb (void *opaque,

                                   target_phys_addr_t addr, uint32_t val)

{

#ifdef DEBUG_UNASSIGNED

    ppc4xx_mmio_t *mmio;

    mmio = opaque;

    printf("Unassigned mmio write 0x" PADDRX " = 0x%x base " PADDRX "\n",

           addr, val, mmio->base);

#endif

}

static CPUReadMemoryFunc *unassigned_mmio_read[3] = {

    unassigned_mmio_readb,

    unassigned_mmio_readb,

    unassigned_mmio_readb,

};

static CPUWriteMemoryFunc *unassigned_mmio_write[3] = {

    unassigned_mmio_writeb,

    unassigned_mmio_writeb,

    unassigned_mmio_writeb,

};

static uint32_t mmio_readlen (ppc4xx_mmio_t *mmio,

                              target_phys_addr_t addr, int len)

{

    CPUReadMemoryFunc **mem_read;

    uint32_t ret;

    int idx;

    idx = MMIO_IDX(addr - mmio->base);

#if defined(DEBUG_MMIO)

    printf("%s: mmio %p len %d addr " PADDRX " idx %d\n", __func__,

           mmio, len, addr, idx);

#endif

    mem_read = mmio->mem_read[idx];

    ret = (*mem_read[len])(mmio->opaque[idx], addr - mmio->base);

    return ret;

}

static void mmio_writelen (ppc4xx_mmio_t *mmio,

                           target_phys_addr_t addr, uint32_t value, int len)

{

    CPUWriteMemoryFunc **mem_write;

    int idx;

    idx = MMIO_IDX(addr - mmio->base);

#if defined(DEBUG_MMIO)

    printf("%s: mmio %p len %d addr " PADDRX " idx %d value %08x\n", __func__,

           mmio, len, addr, idx, value);

#endif

    mem_write = mmio->mem_write[idx];

    (*mem_write[len])(mmio->opaque[idx], addr - mmio->base, value);

}

static uint32_t mmio_readb (void *opaque, target_phys_addr_t addr)

{

#if defined(DEBUG_MMIO)

    printf("%s: addr " PADDRX "\n", __func__, addr);

#endif

    return mmio_readlen(opaque, addr, 0);

}

static void mmio_writeb (void *opaque,

                         target_phys_addr_t addr, uint32_t value)

{

#if defined(DEBUG_MMIO)

    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);

#endif

    mmio_writelen(opaque, addr, value, 0);

}

static uint32_t mmio_readw (void *opaque, target_phys_addr_t addr)

{

#if defined(DEBUG_MMIO)

    printf("%s: addr " PADDRX "\n", __func__, addr);

#endif

    return mmio_readlen(opaque, addr, 1);

}

static void mmio_writew (void *opaque,

                         target_phys_addr_t addr, uint32_t value)

{

#if defined(DEBUG_MMIO)

    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);

#endif

    mmio_writelen(opaque, addr, value, 1);

}

static uint32_t mmio_readl (void *opaque, target_phys_addr_t addr)

{

#if defined(DEBUG_MMIO)

    printf("%s: addr " PADDRX "\n", __func__, addr);

#endif

    return mmio_readlen(opaque, addr, 2);

}

static void mmio_writel (void *opaque,

                         target_phys_addr_t addr, uint32_t value)

{

#if defined(DEBUG_MMIO)

    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);

#endif

    mmio_writelen(opaque, addr, value, 2);

}

static CPUReadMemoryFunc *mmio_read[] = {

    &mmio_readb,

    &mmio_readw,

    &mmio_readl,

};

static CPUWriteMemoryFunc *mmio_write[] = {

    &mmio_writeb,

    &mmio_writew,

    &mmio_writel,

};

int ppc4xx_mmio_register (CPUState *env, ppc4xx_mmio_t *mmio,

                          target_phys_addr_t offset, uint32_t len,

                          CPUReadMemoryFunc **mem_read,

                          CPUWriteMemoryFunc **mem_write, void *opaque)

{

    uint32_t end;

    int idx, eidx;

    if ((offset + len) > TARGET_PAGE_SIZE)

        return -1;

    idx = MMIO_IDX(offset);

    end = offset + len - 1;

    eidx = MMIO_IDX(end);

#if defined(DEBUG_MMIO)

    printf("%s: offset %08x len %08x %08x %d %d\n", __func__, offset, len,

           end, idx, eidx);

#endif

    for (; idx <= eidx; idx++) {

        mmio->mem_read[idx] = mem_read;

        mmio->mem_write[idx] = mem_write;

        mmio->opaque[idx] = opaque;

    }

    return 0;

}

ppc4xx_mmio_t *ppc4xx_mmio_init (CPUState *env, target_phys_addr_t base)

{

    ppc4xx_mmio_t *mmio;

    int mmio_memory;

    mmio = qemu_mallocz(sizeof(ppc4xx_mmio_t));

    if (mmio != NULL) {

        mmio->base = base;

        mmio_memory = cpu_register_io_memory(0, mmio_read, mmio_write, mmio);

#if defined(DEBUG_MMIO)

        printf("%s: %p base %08x len %08x %d\n", __func__,

               mmio, base, TARGET_PAGE_SIZE, mmio_memory);

#endif

        cpu_register_physical_memory(base, TARGET_PAGE_SIZE, mmio_memory);

        ppc4xx_mmio_register(env, mmio, 0, TARGET_PAGE_SIZE,

                             unassigned_mmio_read, unassigned_mmio_write,

                             mmio);

    }

    return mmio;

}

/*****************************************************************************/

/* Peripheral local bus arbitrer */

enum {

    PLB0_BESR = 0x084,

    PLB0_BEAR = 0x086,

    PLB0_ACR  = 0x087,

};

typedef struct ppc4xx_plb_t ppc4xx_plb_t;

struct ppc4xx_plb_t {

    uint32_t acr;

    uint32_t bear;

    uint32_t besr;

};

static target_ulong dcr_read_plb (void *opaque, int dcrn)

{

    ppc4xx_plb_t *plb;

    target_ulong ret;

    plb = opaque;

    switch (dcrn) {

    case PLB0_ACR:

        ret = plb->acr;

        break;

    case PLB0_BEAR:

        ret = plb->bear;

        break;

    case PLB0_BESR:

        ret = plb->besr;

        break;

    default:

        /* Avoid gcc warning */

        ret = 0;

        break;

    }

    return ret;

}

static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)

{

    ppc4xx_plb_t *plb;

    plb = opaque;

    switch (dcrn) {

    case PLB0_ACR:

        /* We don't care about the actual parameters written as

         * we don't manage any priorities on the bus

         */

        plb->acr = val & 0xF8000000;

        break;

    case PLB0_BEAR:

        /* Read only */

        break;

    case PLB0_BESR:

        /* Write-clear */

        plb->besr &= ~val;

        break;

    }

}

static void ppc4xx_plb_reset (void *opaque)

{

    ppc4xx_plb_t *plb;

    plb = opaque;

    plb->acr = 0x00000000;

    plb->bear = 0x00000000;

    plb->besr = 0x00000000;

}

void ppc4xx_plb_init (CPUState *env)

{

    ppc4xx_plb_t *plb;

    plb = qemu_mallocz(sizeof(ppc4xx_plb_t));

    if (plb != NULL) {

        ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);

        ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);

        ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);

        ppc4xx_plb_reset(plb);

        qemu_register_reset(ppc4xx_plb_reset, plb);

    }

}

/*****************************************************************************/

/* PLB to OPB bridge */

enum {

    POB0_BESR0 = 0x0A0,

    POB0_BESR1 = 0x0A2,

    POB0_BEAR  = 0x0A4,

};

typedef struct ppc4xx_pob_t ppc4xx_pob_t;

struct ppc4xx_pob_t {

    uint32_t bear;

    uint32_t besr[2];

};

static target_ulong dcr_read_pob (void *opaque, int dcrn)

{

    ppc4xx_pob_t *pob;

    target_ulong ret;

    pob = opaque;

    switch (dcrn) {

    case POB0_BEAR:

        ret = pob->bear;

        break;

    case POB0_BESR0:

    case POB0_BESR1:

        ret = pob->besr[dcrn - POB0_BESR0];

        break;

    default:

        /* Avoid gcc warning */

        ret = 0;

        break;

    }

    return ret;

}

static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)

{

    ppc4xx_pob_t *pob;

    pob = opaque;

    switch (dcrn) {

    case POB0_BEAR:

        /* Read only */

        break;

    case POB0_BESR0:

    case POB0_BESR1:

        /* Write-clear */

        pob->besr[dcrn - POB0_BESR0] &= ~val;

        break;

    }

}

static void ppc4xx_pob_reset (void *opaque)

{

    ppc4xx_pob_t *pob;

    pob = opaque;

    /* No error */

    pob->bear = 0x00000000;

    pob->besr[0] = 0x0000000;

    pob->besr[1] = 0x0000000;

}

void ppc4xx_pob_init (CPUState *env)

{

    ppc4xx_pob_t *pob;

    pob = qemu_mallocz(sizeof(ppc4xx_pob_t));

    if (pob != NULL) {

        ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);

        ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);

        ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);

        qemu_register_reset(ppc4xx_pob_reset, pob);

        ppc4xx_pob_reset(env);

    }

}

/*****************************************************************************/

/* OPB arbitrer */

typedef struct ppc4xx_opba_t ppc4xx_opba_t;

struct ppc4xx_opba_t {

    target_phys_addr_t base;

    uint8_t cr;

    uint8_t pr;

};

static uint32_t opba_readb (void *opaque, target_phys_addr_t addr)

{

    ppc4xx_opba_t *opba;

    uint32_t ret;

#ifdef DEBUG_OPBA

    printf("%s: addr " PADDRX "\n", __func__, addr);

#endif

    opba = opaque;

    switch (addr - opba->base) {

    case 0x00:

        ret = opba->cr;

        break;

    case 0x01:

        ret = opba->pr;

        break;

    default:

        ret = 0x00;

        break;

    }

    return ret;

}

static void opba_writeb (void *opaque,

                         target_phys_addr_t addr, uint32_t value)

{

    ppc4xx_opba_t *opba;

#ifdef DEBUG_OPBA

    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);

#endif

    opba = opaque;

    switch (addr - opba->base) {

    case 0x00:

        opba->cr = value & 0xF8;

        break;

    case 0x01:

        opba->pr = value & 0xFF;

        break;

    default:

        break;

    }

}

static uint32_t opba_readw (void *opaque, target_phys_addr_t addr)

{

    uint32_t ret;

#ifdef DEBUG_OPBA

    printf("%s: addr " PADDRX "\n", __func__, addr);

#endif

    ret = opba_readb(opaque, addr) << 8;

    ret |= opba_readb(opaque, addr + 1);

    return ret;

}

static void opba_writew (void *opaque,

                         target_phys_addr_t addr, uint32_t value)

{

#ifdef DEBUG_OPBA

    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);

#endif

    opba_writeb(opaque, addr, value >> 8);

    opba_writeb(opaque, addr + 1, value);

}

static uint32_t opba_readl (void *opaque, target_phys_addr_t addr)

{

    uint32_t ret;

#ifdef DEBUG_OPBA

    printf("%s: addr " PADDRX "\n", __func__, addr);

#endif

    ret = opba_readb(opaque, addr) << 24;

    ret |= opba_readb(opaque, addr + 1) << 16;

    return ret;

}

static void opba_writel (void *opaque,

                         target_phys_addr_t addr, uint32_t value)

{

#ifdef DEBUG_OPBA

    printf("%s: addr " PADDRX " val %08x\n", __func__, addr, value);

#endif

    opba_writeb(opaque, addr, value >> 24);

    opba_writeb(opaque, addr + 1, value >> 16);

}

static CPUReadMemoryFunc *opba_read[] = {

    &opba_readb,

    &opba_readw,

    &opba_readl,

};

static CPUWriteMemoryFunc *opba_write[] = {

    &opba_writeb,

    &opba_writew,

    &opba_writel,

};

static void ppc4xx_opba_reset (void *opaque)

{

    ppc4xx_opba_t *opba;

    opba = opaque;

    opba->cr = 0x00; /* No dynamic priorities - park disabled */

    opba->pr = 0x11;

}

void ppc4xx_opba_init (CPUState *env, ppc4xx_mmio_t *mmio,

                       target_phys_addr_t offset)

{

    ppc4xx_opba_t *opba;

    opba = qemu_mallocz(sizeof(ppc4xx_opba_t));

    if (opba != NULL) {

        opba->base = offset;

#ifdef DEBUG_OPBA

        printf("%s: offset=" PADDRX "\n", __func__, offset);

#endif

        ppc4xx_mmio_register(env, mmio, offset, 0x002,

                             opba_read, opba_write, opba);

        qemu_register_reset(ppc4xx_opba_reset, opba);

        ppc4xx_opba_reset(opba);

    }

}

/*****************************************************************************/

/* "Universal" Interrupt controller */

enum {

    DCR_UICSR  = 0x000,

    DCR_UICSRS = 0x001,

    DCR_UICER  = 0x002,

    DCR_UICCR  = 0x003,

    DCR_UICPR  = 0x004,

    DCR_UICTR  = 0x005,

    DCR_UICMSR = 0x006,

    DCR_UICVR  = 0x007,

    DCR_UICVCR = 0x008,

    DCR_UICMAX = 0x009,

};

#define UIC_MAX_IRQ 32

typedef struct ppcuic_t ppcuic_t;

struct ppcuic_t {

    uint32_t dcr_base;

    int use_vectors;

    uint32_t uicsr;  /* Status register */

    uint32_t uicer;  /* Enable register */

    uint32_t uiccr;  /* Critical register */

    uint32_t uicpr;  /* Polarity register */

    uint32_t uictr;  /* Triggering register */

    uint32_t uicvcr; /* Vector configuration register */

    uint32_t uicvr;

    qemu_irq *irqs;

};

static void ppcuic_trigger_irq (ppcuic_t *uic)

{

    uint32_t ir, cr;

    int start, end, inc, i;

    /* Trigger interrupt if any is pending */

    ir = uic->uicsr & uic->uicer & (~uic->uiccr);

    cr = uic->uicsr & uic->uicer & uic->uiccr;

#ifdef DEBUG_UIC

    if (loglevel & CPU_LOG_INT) {

        fprintf(logfile, "%s: uicsr %08x uicer %08x uiccr %08x\n"

                "   %08x ir %08x cr %08x\n", __func__,

                uic->uicsr, uic->uicer, uic->uiccr,

                uic->uicsr & uic->uicer, ir, cr);

    }

#endif

    if (ir != 0x0000000) {

#ifdef DEBUG_UIC

        if (loglevel & CPU_LOG_INT) {

            fprintf(logfile, "Raise UIC interrupt\n");

        }

#endif

        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_INT]);

    } else {

#ifdef DEBUG_UIC

        if (loglevel & CPU_LOG_INT) {

            fprintf(logfile, "Lower UIC interrupt\n");

        }

#endif

        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_INT]);

    }

    /* Trigger critical interrupt if any is pending and update vector */

    if (cr != 0x0000000) {

        qemu_irq_raise(uic->irqs[PPCUIC_OUTPUT_CINT]);

        if (uic->use_vectors) {

            /* Compute critical IRQ vector */

            if (uic->uicvcr & 1) {

                start = 31;

                end = 0;

                inc = -1;

            } else {

                start = 0;

                end = 31;

                inc = 1;

            }

            uic->uicvr = uic->uicvcr & 0xFFFFFFFC;

            for (i = start; i <= end; i += inc) {

                if (cr & (1 << i)) {

                    uic->uicvr += (i - start) * 512 * inc;

                    break;

                }

            }

        }

#ifdef DEBUG_UIC

        if (loglevel & CPU_LOG_INT) {

            fprintf(logfile, "Raise UIC critical interrupt - vector %08x\n",

                    uic->uicvr);

        }

#endif

    } else {

#ifdef DEBUG_UIC

        if (loglevel & CPU_LOG_INT) {

            fprintf(logfile, "Lower UIC critical interrupt\n");

        }

#endif

        qemu_irq_lower(uic->irqs[PPCUIC_OUTPUT_CINT]);

        uic->uicvr = 0x00000000;

    }

}

static void ppcuic_set_irq (void *opaque, int irq_num, int level)

{

    ppcuic_t *uic;

    uint32_t mask, sr;

    uic = opaque;

    mask = 1 << irq_num;

#ifdef DEBUG_UIC

    if (loglevel & CPU_LOG_INT) {

        fprintf(logfile, "%s: irq %d level %d uicsr %08x mask %08x => %08x "

                "%08x\n", __func__, irq_num, level,

                uic->uicsr, mask, uic->uicsr & mask, level << irq_num);

    }

#endif

    if (irq_num < 0 || irq_num > 31)

        return;

    sr = uic->uicsr;

    if (!(uic->uicpr & mask)) {

        /* Negatively asserted IRQ */

        level = level == 0 ? 1 : 0;

    }

    /* Update status register */

    if (uic->uictr & mask) {

        /* Edge sensitive interrupt */

        if (level == 1)

            uic->uicsr |= mask;

    } else {

        /* Level sensitive interrupt */

        if (level == 1)

            uic->uicsr |= mask;

        else

            uic->uicsr &= ~mask;

    }

#ifdef DEBUG_UIC

    if (loglevel & CPU_LOG_INT) {

        fprintf(logfile, "%s: irq %d level %d sr %08x => %08x\n", __func__,

                irq_num, level, uic->uicsr, sr);

    }

#endif

    if (sr != uic->uicsr)

        ppcuic_trigger_irq(uic);

}

static target_ulong dcr_read_uic (void *opaque, int dcrn)

{

    ppcuic_t *uic;

    target_ulong ret;

    uic = opaque;

    dcrn -= uic->dcr_base;

    switch (dcrn) {

    case DCR_UICSR:

    case DCR_UICSRS:

        ret = uic->uicsr;

        break;

    case DCR_UICER:

        ret = uic->uicer;

        break;

    case DCR_UICCR:

        ret = uic->uiccr;

        break;

    case DCR_UICPR:

        ret = uic->uicpr;

        break;

    case DCR_UICTR:

        ret = uic->uictr;

        break;

    case DCR_UICMSR:

        ret = uic->uicsr & uic->uicer;

        break;

    case DCR_UICVR:

        if (!uic->use_vectors)

            goto no_read;

        ret = uic->uicvr;

        break;

    case DCR_UICVCR:

        if (!uic->use_vectors)

            goto no_read;

        ret = uic->uicvcr;

        break;

    default:

    no_read:

        ret = 0x00000000;

        break;

    }

    return ret;

}

static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)

{

    ppcuic_t *uic;

    uic = opaque;

    dcrn -= uic->dcr_base;

#ifdef DEBUG_UIC

    if (loglevel & CPU_LOG_INT) {

        fprintf(logfile, "%s: dcr %d val " ADDRX "\n", __func__, dcrn, val);

    }

#endif

    switch (dcrn) {

    case DCR_UICSR:

        uic->uicsr &= ~val;

        ppcuic_trigger_irq(uic);

        break;

    case DCR_UICSRS:

        uic->uicsr |= val;

        ppcuic_trigger_irq(uic);

        break;

    case DCR_UICER:

        uic->uicer = val;

        ppcuic_trigger_irq(uic);

        break;

    case DCR_UICCR:

        uic->uiccr = val;

        ppcuic_trigger_irq(uic);

        break;

    case DCR_UICPR:

        uic->uicpr = val;

        ppcuic_trigger_irq(uic);

        break;

    case DCR_UICTR:

        uic->uictr = val;

        ppcuic_trigger_irq(uic);

        break;

    case DCR_UICMSR:

        break;

    case DCR_UICVR:

        break;

    case DCR_UICVCR:

        uic->uicvcr = val & 0xFFFFFFFD;

        ppcuic_trigger_irq(uic);

        break;

    }

}

static void ppcuic_reset (void *opaque)

{

    ppcuic_t *uic;

    uic = opaque;

    uic->uiccr = 0x00000000;

    uic->uicer = 0x00000000;

    uic->uicpr = 0x00000000;

    uic->uicsr = 0x00000000;

    uic->uictr = 0x00000000;

    if (uic->use_vectors) {

        uic->uicvcr = 0x00000000;

        uic->uicvr = 0x0000000;

    }

}

qemu_irq *ppcuic_init (CPUState *env, qemu_irq *irqs,

                       uint32_t dcr_base, int has_ssr, int has_vr)

{

    ppcuic_t *uic;

    int i;

    uic = qemu_mallocz(sizeof(ppcuic_t));

    if (uic != NULL) {

        uic->dcr_base = dcr_base;

        uic->irqs = irqs;

        if (has_vr)

            uic->use_vectors = 1;

        for (i = 0; i < DCR_UICMAX; i++) {

            ppc_dcr_register(env, dcr_base + i, uic,

                             &dcr_read_uic, &dcr_write_uic);

        }

        qemu_register_reset(ppcuic_reset, uic);

        ppcuic_reset(uic);

    }