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1 | 9a64fbe4 | bellard | /*
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2 | a541f297 | bellard | * QEMU PPC PREP hardware System Emulator
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3 | 5fafdf24 | ths | *
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4 | 47103572 | j_mayer | * Copyright (c) 2003-2007 Jocelyn Mayer
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5 | 5fafdf24 | ths | *
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6 | a541f297 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | a541f297 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | a541f297 | bellard | * in the Software without restriction, including without limitation the rights
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9 | a541f297 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | a541f297 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | a541f297 | bellard | * furnished to do so, subject to the following conditions:
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12 | a541f297 | bellard | *
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13 | a541f297 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | a541f297 | bellard | * all copies or substantial portions of the Software.
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15 | a541f297 | bellard | *
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16 | a541f297 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | a541f297 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | a541f297 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | a541f297 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | a541f297 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | a541f297 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | a541f297 | bellard | * THE SOFTWARE.
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23 | 9a64fbe4 | bellard | */
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24 | 9a64fbe4 | bellard | #include "vl.h" |
25 | 9fddaa0c | bellard | |
26 | 9a64fbe4 | bellard | //#define HARD_DEBUG_PPC_IO
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27 | a541f297 | bellard | //#define DEBUG_PPC_IO
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28 | 9a64fbe4 | bellard | |
29 | b6b8bd18 | bellard | #define BIOS_FILENAME "ppc_rom.bin" |
30 | b6b8bd18 | bellard | #define KERNEL_LOAD_ADDR 0x01000000 |
31 | b6b8bd18 | bellard | #define INITRD_LOAD_ADDR 0x01800000 |
32 | 64201201 | bellard | |
33 | 9a64fbe4 | bellard | extern int loglevel; |
34 | 9a64fbe4 | bellard | extern FILE *logfile;
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35 | 9a64fbe4 | bellard | |
36 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
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37 | 9a64fbe4 | bellard | #define DEBUG_PPC_IO
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38 | 9a64fbe4 | bellard | #endif
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39 | 9a64fbe4 | bellard | |
40 | 9a64fbe4 | bellard | #if defined (HARD_DEBUG_PPC_IO)
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41 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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42 | 9a64fbe4 | bellard | do { \
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43 | b6b8bd18 | bellard | if (loglevel & CPU_LOG_IOPORT) { \
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44 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
45 | 9a64fbe4 | bellard | } else { \
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46 | 9a64fbe4 | bellard | printf("%s : " fmt, __func__ , ##args); \ |
47 | 9a64fbe4 | bellard | } \ |
48 | 9a64fbe4 | bellard | } while (0) |
49 | 9a64fbe4 | bellard | #elif defined (DEBUG_PPC_IO)
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50 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) \
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51 | 9a64fbe4 | bellard | do { \
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52 | b6b8bd18 | bellard | if (loglevel & CPU_LOG_IOPORT) { \
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53 | 9a64fbe4 | bellard | fprintf(logfile, "%s: " fmt, __func__ , ##args); \ |
54 | 9a64fbe4 | bellard | } \ |
55 | 9a64fbe4 | bellard | } while (0) |
56 | 9a64fbe4 | bellard | #else
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57 | 9a64fbe4 | bellard | #define PPC_IO_DPRINTF(fmt, args...) do { } while (0) |
58 | 9a64fbe4 | bellard | #endif
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59 | 9a64fbe4 | bellard | |
60 | 64201201 | bellard | /* Constants for devices init */
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61 | a541f297 | bellard | static const int ide_iobase[2] = { 0x1f0, 0x170 }; |
62 | a541f297 | bellard | static const int ide_iobase2[2] = { 0x3f6, 0x376 }; |
63 | a541f297 | bellard | static const int ide_irq[2] = { 13, 13 }; |
64 | a541f297 | bellard | |
65 | a541f297 | bellard | #define NE2000_NB_MAX 6 |
66 | a541f297 | bellard | |
67 | a541f297 | bellard | static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 }; |
68 | a541f297 | bellard | static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 }; |
69 | 9a64fbe4 | bellard | |
70 | 64201201 | bellard | //static PITState *pit;
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71 | 64201201 | bellard | |
72 | 64201201 | bellard | /* ISA IO ports bridge */
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73 | 9a64fbe4 | bellard | #define PPC_IO_BASE 0x80000000 |
74 | 9a64fbe4 | bellard | |
75 | 64201201 | bellard | /* Speaker port 0x61 */
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76 | 64201201 | bellard | int speaker_data_on;
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77 | 64201201 | bellard | int dummy_refresh_clock;
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78 | 64201201 | bellard | |
79 | 36081602 | j_mayer | static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val) |
80 | 9a64fbe4 | bellard | { |
81 | a541f297 | bellard | #if 0
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82 | 64201201 | bellard | speaker_data_on = (val >> 1) & 1;
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83 | 64201201 | bellard | pit_set_gate(pit, 2, val & 1);
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84 | a541f297 | bellard | #endif
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85 | 9a64fbe4 | bellard | } |
86 | 9a64fbe4 | bellard | |
87 | 47103572 | j_mayer | static uint32_t speaker_ioport_read (void *opaque, uint32_t addr) |
88 | 9a64fbe4 | bellard | { |
89 | a541f297 | bellard | #if 0
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90 | 64201201 | bellard | int out;
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91 | 64201201 | bellard | out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
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92 | 64201201 | bellard | dummy_refresh_clock ^= 1;
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93 | 64201201 | bellard | return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
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94 | 47103572 | j_mayer | (dummy_refresh_clock << 4);
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95 | a541f297 | bellard | #endif
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96 | 64201201 | bellard | return 0; |
97 | 9a64fbe4 | bellard | } |
98 | 9a64fbe4 | bellard | |
99 | 64201201 | bellard | /* PCI intack register */
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100 | 64201201 | bellard | /* Read-only register (?) */
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101 | 47103572 | j_mayer | static void _PPC_intack_write (void *opaque, |
102 | 47103572 | j_mayer | target_phys_addr_t addr, uint32_t value) |
103 | 64201201 | bellard | { |
104 | 64201201 | bellard | // printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
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105 | 64201201 | bellard | } |
106 | 64201201 | bellard | |
107 | 64201201 | bellard | static inline uint32_t _PPC_intack_read (target_phys_addr_t addr) |
108 | 64201201 | bellard | { |
109 | 64201201 | bellard | uint32_t retval = 0;
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110 | 64201201 | bellard | |
111 | 64201201 | bellard | if (addr == 0xBFFFFFF0) |
112 | 3de388f6 | bellard | retval = pic_intack_read(isa_pic); |
113 | 36081602 | j_mayer | // printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
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114 | 64201201 | bellard | |
115 | 64201201 | bellard | return retval;
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116 | 64201201 | bellard | } |
117 | 64201201 | bellard | |
118 | a4193c8a | bellard | static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr) |
119 | 64201201 | bellard | { |
120 | 64201201 | bellard | return _PPC_intack_read(addr);
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121 | 64201201 | bellard | } |
122 | 64201201 | bellard | |
123 | a4193c8a | bellard | static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr) |
124 | 9a64fbe4 | bellard | { |
125 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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126 | 64201201 | bellard | return bswap16(_PPC_intack_read(addr));
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127 | 64201201 | bellard | #else
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128 | 64201201 | bellard | return _PPC_intack_read(addr);
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129 | f658b4db | bellard | #endif
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130 | 9a64fbe4 | bellard | } |
131 | 9a64fbe4 | bellard | |
132 | a4193c8a | bellard | static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr) |
133 | 9a64fbe4 | bellard | { |
134 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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135 | 64201201 | bellard | return bswap32(_PPC_intack_read(addr));
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136 | 64201201 | bellard | #else
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137 | 64201201 | bellard | return _PPC_intack_read(addr);
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138 | f658b4db | bellard | #endif
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139 | 9a64fbe4 | bellard | } |
140 | 9a64fbe4 | bellard | |
141 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_intack_write[] = {
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142 | 64201201 | bellard | &_PPC_intack_write, |
143 | 64201201 | bellard | &_PPC_intack_write, |
144 | 64201201 | bellard | &_PPC_intack_write, |
145 | 64201201 | bellard | }; |
146 | 64201201 | bellard | |
147 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_intack_read[] = {
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148 | 64201201 | bellard | &PPC_intack_readb, |
149 | 64201201 | bellard | &PPC_intack_readw, |
150 | 64201201 | bellard | &PPC_intack_readl, |
151 | 64201201 | bellard | }; |
152 | 64201201 | bellard | |
153 | 64201201 | bellard | /* PowerPC control and status registers */
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154 | 64201201 | bellard | #if 0 // Not used
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155 | 64201201 | bellard | static struct {
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156 | 64201201 | bellard | /* IDs */
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157 | 64201201 | bellard | uint32_t veni_devi;
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158 | 64201201 | bellard | uint32_t revi;
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159 | 64201201 | bellard | /* Control and status */
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160 | 64201201 | bellard | uint32_t gcsr;
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161 | 64201201 | bellard | uint32_t xcfr;
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162 | 64201201 | bellard | uint32_t ct32;
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163 | 64201201 | bellard | uint32_t mcsr;
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164 | 64201201 | bellard | /* General purpose registers */
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165 | 64201201 | bellard | uint32_t gprg[6];
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166 | 64201201 | bellard | /* Exceptions */
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167 | 64201201 | bellard | uint32_t feen;
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168 | 64201201 | bellard | uint32_t fest;
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169 | 64201201 | bellard | uint32_t fema;
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170 | 64201201 | bellard | uint32_t fecl;
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171 | 64201201 | bellard | uint32_t eeen;
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172 | 64201201 | bellard | uint32_t eest;
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173 | 64201201 | bellard | uint32_t eecl;
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174 | 64201201 | bellard | uint32_t eeint;
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175 | 64201201 | bellard | uint32_t eemck0;
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176 | 64201201 | bellard | uint32_t eemck1;
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177 | 64201201 | bellard | /* Error diagnostic */
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178 | 64201201 | bellard | } XCSR;
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179 | 64201201 | bellard | |
180 | 36081602 | j_mayer | static void PPC_XCSR_writeb (void *opaque,
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181 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value)
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182 | 64201201 | bellard | {
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183 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
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184 | 64201201 | bellard | }
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185 | 64201201 | bellard | |
186 | 36081602 | j_mayer | static void PPC_XCSR_writew (void *opaque,
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187 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value)
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188 | 9a64fbe4 | bellard | {
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189 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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190 | 64201201 | bellard | value = bswap16(value);
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191 | f658b4db | bellard | #endif
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192 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
193 | 9a64fbe4 | bellard | } |
194 | 9a64fbe4 | bellard | |
195 | 36081602 | j_mayer | static void PPC_XCSR_writel (void *opaque, |
196 | 36081602 | j_mayer | target_phys_addr_t addr, uint32_t value) |
197 | 9a64fbe4 | bellard | { |
198 | f658b4db | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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199 | 64201201 | bellard | value = bswap32(value); |
200 | f658b4db | bellard | #endif
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201 | 64201201 | bellard | printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value); |
202 | 9a64fbe4 | bellard | } |
203 | 9a64fbe4 | bellard | |
204 | a4193c8a | bellard | static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr) |
205 | 64201201 | bellard | { |
206 | 64201201 | bellard | uint32_t retval = 0;
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207 | 9a64fbe4 | bellard | |
208 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
209 | 9a64fbe4 | bellard | |
210 | 64201201 | bellard | return retval;
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211 | 64201201 | bellard | } |
212 | 64201201 | bellard | |
213 | a4193c8a | bellard | static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr) |
214 | 9a64fbe4 | bellard | { |
215 | 64201201 | bellard | uint32_t retval = 0;
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216 | 64201201 | bellard | |
217 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
218 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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219 | 64201201 | bellard | retval = bswap16(retval); |
220 | 64201201 | bellard | #endif
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221 | 64201201 | bellard | |
222 | 64201201 | bellard | return retval;
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223 | 9a64fbe4 | bellard | } |
224 | 9a64fbe4 | bellard | |
225 | a4193c8a | bellard | static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr) |
226 | 9a64fbe4 | bellard | { |
227 | 9a64fbe4 | bellard | uint32_t retval = 0;
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228 | 9a64fbe4 | bellard | |
229 | 64201201 | bellard | printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval); |
230 | 64201201 | bellard | #ifdef TARGET_WORDS_BIGENDIAN
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231 | 64201201 | bellard | retval = bswap32(retval); |
232 | 64201201 | bellard | #endif
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233 | 9a64fbe4 | bellard | |
234 | 9a64fbe4 | bellard | return retval;
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235 | 9a64fbe4 | bellard | } |
236 | 9a64fbe4 | bellard | |
237 | 64201201 | bellard | static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
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238 | 64201201 | bellard | &PPC_XCSR_writeb, |
239 | 64201201 | bellard | &PPC_XCSR_writew, |
240 | 64201201 | bellard | &PPC_XCSR_writel, |
241 | 9a64fbe4 | bellard | }; |
242 | 9a64fbe4 | bellard | |
243 | 64201201 | bellard | static CPUReadMemoryFunc *PPC_XCSR_read[] = {
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244 | 64201201 | bellard | &PPC_XCSR_readb, |
245 | 64201201 | bellard | &PPC_XCSR_readw, |
246 | 64201201 | bellard | &PPC_XCSR_readl, |
247 | 9a64fbe4 | bellard | }; |
248 | b6b8bd18 | bellard | #endif
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249 | 9a64fbe4 | bellard | |
250 | 64201201 | bellard | /* Fake super-io ports for PREP platform (Intel 82378ZB) */
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251 | 64201201 | bellard | typedef struct sysctrl_t { |
252 | 64201201 | bellard | m48t59_t *nvram; |
253 | 64201201 | bellard | uint8_t state; |
254 | 64201201 | bellard | uint8_t syscontrol; |
255 | 64201201 | bellard | uint8_t fake_io[2];
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256 | da9b266b | bellard | int contiguous_map;
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257 | fb3444b8 | bellard | int endian;
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258 | 64201201 | bellard | } sysctrl_t; |
259 | 9a64fbe4 | bellard | |
260 | 64201201 | bellard | enum {
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261 | 64201201 | bellard | STATE_HARDFILE = 0x01,
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262 | 9a64fbe4 | bellard | }; |
263 | 9a64fbe4 | bellard | |
264 | 64201201 | bellard | static sysctrl_t *sysctrl;
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265 | 9a64fbe4 | bellard | |
266 | a541f297 | bellard | static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val) |
267 | 9a64fbe4 | bellard | { |
268 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
269 | 64201201 | bellard | |
270 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
271 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398] = val;
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272 | 9a64fbe4 | bellard | } |
273 | 9a64fbe4 | bellard | |
274 | a541f297 | bellard | static uint32_t PREP_io_read (void *opaque, uint32_t addr) |
275 | 9a64fbe4 | bellard | { |
276 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
277 | 9a64fbe4 | bellard | |
278 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, |
279 | 64201201 | bellard | sysctrl->fake_io[addr - 0x0398]);
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280 | 64201201 | bellard | return sysctrl->fake_io[addr - 0x0398]; |
281 | 64201201 | bellard | } |
282 | 9a64fbe4 | bellard | |
283 | a541f297 | bellard | static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val) |
284 | 9a64fbe4 | bellard | { |
285 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
286 | 64201201 | bellard | |
287 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val); |
288 | 9a64fbe4 | bellard | switch (addr) {
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289 | 9a64fbe4 | bellard | case 0x0092: |
290 | 9a64fbe4 | bellard | /* Special port 92 */
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291 | 9a64fbe4 | bellard | /* Check soft reset asked */
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292 | 64201201 | bellard | if (val & 0x01) { |
293 | 47103572 | j_mayer | // cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
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294 | 9a64fbe4 | bellard | } |
295 | 9a64fbe4 | bellard | /* Check LE mode */
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296 | 64201201 | bellard | if (val & 0x02) { |
297 | fb3444b8 | bellard | sysctrl->endian = 1;
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298 | fb3444b8 | bellard | } else {
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299 | fb3444b8 | bellard | sysctrl->endian = 0;
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300 | 9a64fbe4 | bellard | } |
301 | 9a64fbe4 | bellard | break;
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302 | 64201201 | bellard | case 0x0800: |
303 | 64201201 | bellard | /* Motorola CPU configuration register : read-only */
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304 | 64201201 | bellard | break;
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305 | 64201201 | bellard | case 0x0802: |
306 | 64201201 | bellard | /* Motorola base module feature register : read-only */
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307 | 64201201 | bellard | break;
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308 | 64201201 | bellard | case 0x0803: |
309 | 64201201 | bellard | /* Motorola base module status register : read-only */
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310 | 64201201 | bellard | break;
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311 | 9a64fbe4 | bellard | case 0x0808: |
312 | 64201201 | bellard | /* Hardfile light register */
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313 | 64201201 | bellard | if (val & 1) |
314 | 64201201 | bellard | sysctrl->state |= STATE_HARDFILE; |
315 | 64201201 | bellard | else
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316 | 64201201 | bellard | sysctrl->state &= ~STATE_HARDFILE; |
317 | 9a64fbe4 | bellard | break;
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318 | 9a64fbe4 | bellard | case 0x0810: |
319 | 9a64fbe4 | bellard | /* Password protect 1 register */
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320 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
321 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 1);
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322 | 9a64fbe4 | bellard | break;
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323 | 9a64fbe4 | bellard | case 0x0812: |
324 | 9a64fbe4 | bellard | /* Password protect 2 register */
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325 | 64201201 | bellard | if (sysctrl->nvram != NULL) |
326 | 64201201 | bellard | m48t59_toggle_lock(sysctrl->nvram, 2);
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327 | 9a64fbe4 | bellard | break;
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328 | 9a64fbe4 | bellard | case 0x0814: |
329 | 64201201 | bellard | /* L2 invalidate register */
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330 | c68ea704 | bellard | // tlb_flush(first_cpu, 1);
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331 | 9a64fbe4 | bellard | break;
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332 | 9a64fbe4 | bellard | case 0x081C: |
333 | 9a64fbe4 | bellard | /* system control register */
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334 | 64201201 | bellard | sysctrl->syscontrol = val & 0x0F;
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335 | 9a64fbe4 | bellard | break;
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336 | 9a64fbe4 | bellard | case 0x0850: |
337 | 9a64fbe4 | bellard | /* I/O map type register */
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338 | da9b266b | bellard | sysctrl->contiguous_map = val & 0x01;
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339 | 9a64fbe4 | bellard | break;
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340 | 9a64fbe4 | bellard | default:
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341 | 64201201 | bellard | printf("ERROR: unaffected IO port write: %04lx => %02x\n",
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342 | 64201201 | bellard | (long)addr, val);
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343 | 9a64fbe4 | bellard | break;
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344 | 9a64fbe4 | bellard | } |
345 | 9a64fbe4 | bellard | } |
346 | 9a64fbe4 | bellard | |
347 | a541f297 | bellard | static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr) |
348 | 9a64fbe4 | bellard | { |
349 | 64201201 | bellard | sysctrl_t *sysctrl = opaque; |
350 | 9a64fbe4 | bellard | uint32_t retval = 0xFF;
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351 | 9a64fbe4 | bellard | |
352 | 9a64fbe4 | bellard | switch (addr) {
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353 | 9a64fbe4 | bellard | case 0x0092: |
354 | 9a64fbe4 | bellard | /* Special port 92 */
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355 | 64201201 | bellard | retval = 0x00;
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356 | 64201201 | bellard | break;
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357 | 64201201 | bellard | case 0x0800: |
358 | 64201201 | bellard | /* Motorola CPU configuration register */
|
359 | 64201201 | bellard | retval = 0xEF; /* MPC750 */ |
360 | 64201201 | bellard | break;
|
361 | 64201201 | bellard | case 0x0802: |
362 | 64201201 | bellard | /* Motorola Base module feature register */
|
363 | 64201201 | bellard | retval = 0xAD; /* No ESCC, PMC slot neither ethernet */ |
364 | 64201201 | bellard | break;
|
365 | 64201201 | bellard | case 0x0803: |
366 | 64201201 | bellard | /* Motorola base module status register */
|
367 | 64201201 | bellard | retval = 0xE0; /* Standard MPC750 */ |
368 | 9a64fbe4 | bellard | break;
|
369 | 9a64fbe4 | bellard | case 0x080C: |
370 | 9a64fbe4 | bellard | /* Equipment present register:
|
371 | 9a64fbe4 | bellard | * no L2 cache
|
372 | 9a64fbe4 | bellard | * no upgrade processor
|
373 | 9a64fbe4 | bellard | * no cards in PCI slots
|
374 | 9a64fbe4 | bellard | * SCSI fuse is bad
|
375 | 9a64fbe4 | bellard | */
|
376 | 64201201 | bellard | retval = 0x3C;
|
377 | 64201201 | bellard | break;
|
378 | 64201201 | bellard | case 0x0810: |
379 | 64201201 | bellard | /* Motorola base module extended feature register */
|
380 | 64201201 | bellard | retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */ |
381 | 9a64fbe4 | bellard | break;
|
382 | da9b266b | bellard | case 0x0814: |
383 | da9b266b | bellard | /* L2 invalidate: don't care */
|
384 | da9b266b | bellard | break;
|
385 | 9a64fbe4 | bellard | case 0x0818: |
386 | 9a64fbe4 | bellard | /* Keylock */
|
387 | 9a64fbe4 | bellard | retval = 0x00;
|
388 | 9a64fbe4 | bellard | break;
|
389 | 9a64fbe4 | bellard | case 0x081C: |
390 | 9a64fbe4 | bellard | /* system control register
|
391 | 9a64fbe4 | bellard | * 7 - 6 / 1 - 0: L2 cache enable
|
392 | 9a64fbe4 | bellard | */
|
393 | 64201201 | bellard | retval = sysctrl->syscontrol; |
394 | 9a64fbe4 | bellard | break;
|
395 | 9a64fbe4 | bellard | case 0x0823: |
396 | 9a64fbe4 | bellard | /* */
|
397 | 9a64fbe4 | bellard | retval = 0x03; /* no L2 cache */ |
398 | 9a64fbe4 | bellard | break;
|
399 | 9a64fbe4 | bellard | case 0x0850: |
400 | 9a64fbe4 | bellard | /* I/O map type register */
|
401 | da9b266b | bellard | retval = sysctrl->contiguous_map; |
402 | 9a64fbe4 | bellard | break;
|
403 | 9a64fbe4 | bellard | default:
|
404 | 64201201 | bellard | printf("ERROR: unaffected IO port: %04lx read\n", (long)addr); |
405 | 9a64fbe4 | bellard | break;
|
406 | 9a64fbe4 | bellard | } |
407 | 64201201 | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval); |
408 | 9a64fbe4 | bellard | |
409 | 9a64fbe4 | bellard | return retval;
|
410 | 9a64fbe4 | bellard | } |
411 | 9a64fbe4 | bellard | |
412 | da9b266b | bellard | static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl, |
413 | da9b266b | bellard | target_phys_addr_t addr) |
414 | da9b266b | bellard | { |
415 | da9b266b | bellard | if (sysctrl->contiguous_map == 0) { |
416 | da9b266b | bellard | /* 64 KB contiguous space for IOs */
|
417 | da9b266b | bellard | addr &= 0xFFFF;
|
418 | da9b266b | bellard | } else {
|
419 | da9b266b | bellard | /* 8 MB non-contiguous space for IOs */
|
420 | da9b266b | bellard | addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7); |
421 | da9b266b | bellard | } |
422 | da9b266b | bellard | |
423 | da9b266b | bellard | return addr;
|
424 | da9b266b | bellard | } |
425 | da9b266b | bellard | |
426 | da9b266b | bellard | static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr, |
427 | da9b266b | bellard | uint32_t value) |
428 | da9b266b | bellard | { |
429 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
430 | da9b266b | bellard | |
431 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
432 | da9b266b | bellard | cpu_outb(NULL, addr, value);
|
433 | da9b266b | bellard | } |
434 | da9b266b | bellard | |
435 | da9b266b | bellard | static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr) |
436 | da9b266b | bellard | { |
437 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
438 | da9b266b | bellard | uint32_t ret; |
439 | da9b266b | bellard | |
440 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
441 | da9b266b | bellard | ret = cpu_inb(NULL, addr);
|
442 | da9b266b | bellard | |
443 | da9b266b | bellard | return ret;
|
444 | da9b266b | bellard | } |
445 | da9b266b | bellard | |
446 | da9b266b | bellard | static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr, |
447 | da9b266b | bellard | uint32_t value) |
448 | da9b266b | bellard | { |
449 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
450 | da9b266b | bellard | |
451 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
452 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
453 | da9b266b | bellard | value = bswap16(value); |
454 | da9b266b | bellard | #endif
|
455 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); |
456 | da9b266b | bellard | cpu_outw(NULL, addr, value);
|
457 | da9b266b | bellard | } |
458 | da9b266b | bellard | |
459 | da9b266b | bellard | static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr) |
460 | da9b266b | bellard | { |
461 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
462 | da9b266b | bellard | uint32_t ret; |
463 | da9b266b | bellard | |
464 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
465 | da9b266b | bellard | ret = cpu_inw(NULL, addr);
|
466 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
467 | da9b266b | bellard | ret = bswap16(ret); |
468 | da9b266b | bellard | #endif
|
469 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); |
470 | da9b266b | bellard | |
471 | da9b266b | bellard | return ret;
|
472 | da9b266b | bellard | } |
473 | da9b266b | bellard | |
474 | da9b266b | bellard | static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr, |
475 | da9b266b | bellard | uint32_t value) |
476 | da9b266b | bellard | { |
477 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
478 | da9b266b | bellard | |
479 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
480 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
481 | da9b266b | bellard | value = bswap32(value); |
482 | da9b266b | bellard | #endif
|
483 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value); |
484 | da9b266b | bellard | cpu_outl(NULL, addr, value);
|
485 | da9b266b | bellard | } |
486 | da9b266b | bellard | |
487 | da9b266b | bellard | static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr) |
488 | da9b266b | bellard | { |
489 | da9b266b | bellard | sysctrl_t *sysctrl = opaque; |
490 | da9b266b | bellard | uint32_t ret; |
491 | da9b266b | bellard | |
492 | da9b266b | bellard | addr = prep_IO_address(sysctrl, addr); |
493 | da9b266b | bellard | ret = cpu_inl(NULL, addr);
|
494 | da9b266b | bellard | #ifdef TARGET_WORDS_BIGENDIAN
|
495 | da9b266b | bellard | ret = bswap32(ret); |
496 | da9b266b | bellard | #endif
|
497 | da9b266b | bellard | PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret); |
498 | da9b266b | bellard | |
499 | da9b266b | bellard | return ret;
|
500 | da9b266b | bellard | } |
501 | da9b266b | bellard | |
502 | da9b266b | bellard | CPUWriteMemoryFunc *PPC_prep_io_write[] = { |
503 | da9b266b | bellard | &PPC_prep_io_writeb, |
504 | da9b266b | bellard | &PPC_prep_io_writew, |
505 | da9b266b | bellard | &PPC_prep_io_writel, |
506 | da9b266b | bellard | }; |
507 | da9b266b | bellard | |
508 | da9b266b | bellard | CPUReadMemoryFunc *PPC_prep_io_read[] = { |
509 | da9b266b | bellard | &PPC_prep_io_readb, |
510 | da9b266b | bellard | &PPC_prep_io_readw, |
511 | da9b266b | bellard | &PPC_prep_io_readl, |
512 | da9b266b | bellard | }; |
513 | da9b266b | bellard | |
514 | 64201201 | bellard | #define NVRAM_SIZE 0x2000 |
515 | a541f297 | bellard | |
516 | 26aa7d72 | bellard | /* PowerPC PREP hardware initialisation */
|
517 | 94fc95cd | j_mayer | static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device, |
518 | 94fc95cd | j_mayer | DisplayState *ds, const char **fd_filename, |
519 | 94fc95cd | j_mayer | int snapshot, const char *kernel_filename, |
520 | 94fc95cd | j_mayer | const char *kernel_cmdline, |
521 | 94fc95cd | j_mayer | const char *initrd_filename, |
522 | 94fc95cd | j_mayer | const char *cpu_model) |
523 | a541f297 | bellard | { |
524 | c68ea704 | bellard | CPUState *env; |
525 | a541f297 | bellard | char buf[1024]; |
526 | 64201201 | bellard | m48t59_t *nvram; |
527 | a541f297 | bellard | int PPC_io_memory;
|
528 | 4157a662 | bellard | int linux_boot, i, nb_nics1, bios_size;
|
529 | 64201201 | bellard | unsigned long bios_offset; |
530 | 64201201 | bellard | uint32_t kernel_base, kernel_size, initrd_base, initrd_size; |
531 | 3fc6c082 | bellard | ppc_def_t *def; |
532 | 46e50e9d | bellard | PCIBus *pci_bus; |
533 | d537cf6c | pbrook | qemu_irq *i8259; |
534 | 64201201 | bellard | |
535 | 64201201 | bellard | sysctrl = qemu_mallocz(sizeof(sysctrl_t));
|
536 | 64201201 | bellard | if (sysctrl == NULL) |
537 | 0a032cbe | j_mayer | return;
|
538 | a541f297 | bellard | |
539 | a541f297 | bellard | linux_boot = (kernel_filename != NULL);
|
540 | 0a032cbe | j_mayer | |
541 | c68ea704 | bellard | /* init CPUs */
|
542 | c68ea704 | bellard | |
543 | c68ea704 | bellard | env = cpu_init(); |
544 | 0a032cbe | j_mayer | qemu_register_reset(&cpu_ppc_reset, env); |
545 | c68ea704 | bellard | register_savevm("cpu", 0, 3, cpu_save, cpu_load, env); |
546 | 94fc95cd | j_mayer | |
547 | 94fc95cd | j_mayer | /* Default CPU is a 604 */
|
548 | 94fc95cd | j_mayer | if (cpu_model == NULL) |
549 | 94fc95cd | j_mayer | cpu_model = "604";
|
550 | 94fc95cd | j_mayer | ppc_find_by_name(cpu_model, &def); |
551 | c68ea704 | bellard | if (def == NULL) { |
552 | c68ea704 | bellard | cpu_abort(env, "Unable to find PowerPC CPU definition\n");
|
553 | c68ea704 | bellard | } |
554 | c68ea704 | bellard | cpu_ppc_register(env, def); |
555 | c68ea704 | bellard | /* Set time-base frequency to 100 Mhz */
|
556 | c68ea704 | bellard | cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); |
557 | a541f297 | bellard | |
558 | a541f297 | bellard | /* allocate RAM */
|
559 | 64201201 | bellard | cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
|
560 | 64201201 | bellard | |
561 | 64201201 | bellard | /* allocate and load BIOS */
|
562 | 64201201 | bellard | bios_offset = ram_size + vga_ram_size; |
563 | 64201201 | bellard | snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME); |
564 | 4157a662 | bellard | bios_size = load_image(buf, phys_ram_base + bios_offset); |
565 | 4157a662 | bellard | if (bios_size < 0 || bios_size > BIOS_SIZE) { |
566 | 4a057712 | j_mayer | cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
|
567 | 64201201 | bellard | exit(1);
|
568 | 64201201 | bellard | } |
569 | 4157a662 | bellard | bios_size = (bios_size + 0xfff) & ~0xfff; |
570 | 4a057712 | j_mayer | cpu_register_physical_memory((uint32_t)(-bios_size), |
571 | 4157a662 | bellard | bios_size, bios_offset | IO_MEM_ROM); |
572 | 26aa7d72 | bellard | |
573 | a541f297 | bellard | if (linux_boot) {
|
574 | 64201201 | bellard | kernel_base = KERNEL_LOAD_ADDR; |
575 | a541f297 | bellard | /* now we can load the kernel */
|
576 | 64201201 | bellard | kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base); |
577 | 64201201 | bellard | if (kernel_size < 0) { |
578 | 4a057712 | j_mayer | cpu_abort(env, "qemu: could not load kernel '%s'\n",
|
579 | 4a057712 | j_mayer | kernel_filename); |
580 | a541f297 | bellard | exit(1);
|
581 | a541f297 | bellard | } |
582 | a541f297 | bellard | /* load initrd */
|
583 | a541f297 | bellard | if (initrd_filename) {
|
584 | 64201201 | bellard | initrd_base = INITRD_LOAD_ADDR; |
585 | 64201201 | bellard | initrd_size = load_image(initrd_filename, |
586 | 64201201 | bellard | phys_ram_base + initrd_base); |
587 | a541f297 | bellard | if (initrd_size < 0) { |
588 | 4a057712 | j_mayer | cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
|
589 | 4a057712 | j_mayer | initrd_filename); |
590 | a541f297 | bellard | exit(1);
|
591 | a541f297 | bellard | } |
592 | 64201201 | bellard | } else {
|
593 | 64201201 | bellard | initrd_base = 0;
|
594 | 64201201 | bellard | initrd_size = 0;
|
595 | a541f297 | bellard | } |
596 | 64201201 | bellard | boot_device = 'm';
|
597 | a541f297 | bellard | } else {
|
598 | 64201201 | bellard | kernel_base = 0;
|
599 | 64201201 | bellard | kernel_size = 0;
|
600 | 64201201 | bellard | initrd_base = 0;
|
601 | 64201201 | bellard | initrd_size = 0;
|
602 | a541f297 | bellard | } |
603 | a541f297 | bellard | |
604 | 64201201 | bellard | isa_mem_base = 0xc0000000;
|
605 | dd37a5e4 | j_mayer | if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
|
606 | dd37a5e4 | j_mayer | cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
|
607 | dd37a5e4 | j_mayer | exit(1);
|
608 | dd37a5e4 | j_mayer | } |
609 | 24be5ae3 | j_mayer | i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]); |
610 | d537cf6c | pbrook | pci_bus = pci_prep_init(i8259); |
611 | da9b266b | bellard | // pci_bus = i440fx_init();
|
612 | da9b266b | bellard | /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
|
613 | da9b266b | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
|
614 | da9b266b | bellard | PPC_prep_io_write, sysctrl); |
615 | da9b266b | bellard | cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory); |
616 | 64201201 | bellard | |
617 | a541f297 | bellard | /* init basic PC hardware */
|
618 | 5fafdf24 | ths | pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size, |
619 | 89b6b508 | bellard | vga_ram_size, 0, 0); |
620 | 64201201 | bellard | // openpic = openpic_init(0x00000000, 0xF0000000, 1);
|
621 | d537cf6c | pbrook | // pit = pit_init(0x40, i8259[0]);
|
622 | d537cf6c | pbrook | rtc_init(0x70, i8259[8]); |
623 | a541f297 | bellard | |
624 | d537cf6c | pbrook | serial_init(0x3f8, i8259[4], serial_hds[0]); |
625 | a541f297 | bellard | nb_nics1 = nb_nics; |
626 | a541f297 | bellard | if (nb_nics1 > NE2000_NB_MAX)
|
627 | a541f297 | bellard | nb_nics1 = NE2000_NB_MAX; |
628 | a541f297 | bellard | for(i = 0; i < nb_nics1; i++) { |
629 | a41b2ff2 | pbrook | if (nd_table[0].model == NULL |
630 | a41b2ff2 | pbrook | || strcmp(nd_table[0].model, "ne2k_isa") == 0) { |
631 | d537cf6c | pbrook | isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]); |
632 | c4a7060c | blueswir1 | } else if (strcmp(nd_table[0].model, "?") == 0) { |
633 | c4a7060c | blueswir1 | fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
|
634 | c4a7060c | blueswir1 | exit (1);
|
635 | a41b2ff2 | pbrook | } else {
|
636 | 4a057712 | j_mayer | /* Why ? */
|
637 | 4a057712 | j_mayer | cpu_abort(env, "qemu: Unsupported NIC: %s\n", nd_table[0].model); |
638 | a41b2ff2 | pbrook | exit (1);
|
639 | a41b2ff2 | pbrook | } |
640 | a541f297 | bellard | } |
641 | a541f297 | bellard | |
642 | a541f297 | bellard | for(i = 0; i < 2; i++) { |
643 | d537cf6c | pbrook | isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]], |
644 | 69b91039 | bellard | bs_table[2 * i], bs_table[2 * i + 1]); |
645 | a541f297 | bellard | } |
646 | d537cf6c | pbrook | i8042_init(i8259[1], i8259[12], 0x60); |
647 | b6b8bd18 | bellard | DMA_init(1);
|
648 | 64201201 | bellard | // AUD_init();
|
649 | a541f297 | bellard | // SB16_init();
|
650 | a541f297 | bellard | |
651 | d537cf6c | pbrook | fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table); |
652 | a541f297 | bellard | |
653 | 64201201 | bellard | /* Register speaker port */
|
654 | 64201201 | bellard | register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL); |
655 | 64201201 | bellard | register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL); |
656 | a541f297 | bellard | /* Register fake IO ports for PREP */
|
657 | 64201201 | bellard | register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl); |
658 | 64201201 | bellard | register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl); |
659 | a541f297 | bellard | /* System control ports */
|
660 | 64201201 | bellard | register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl); |
661 | 64201201 | bellard | register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl); |
662 | 64201201 | bellard | register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl); |
663 | 64201201 | bellard | register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl); |
664 | 64201201 | bellard | /* PCI intack location */
|
665 | 64201201 | bellard | PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
|
666 | a4193c8a | bellard | PPC_intack_write, NULL);
|
667 | a541f297 | bellard | cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory); |
668 | 64201201 | bellard | /* PowerPC control and status register group */
|
669 | b6b8bd18 | bellard | #if 0
|
670 | 36081602 | j_mayer | PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
|
671 | 36081602 | j_mayer | NULL);
|
672 | 64201201 | bellard | cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
|
673 | b6b8bd18 | bellard | #endif
|
674 | a541f297 | bellard | |
675 | 0d92ed30 | pbrook | if (usb_enabled) {
|
676 | e24ad6f1 | pbrook | usb_ohci_init_pci(pci_bus, 3, -1); |
677 | 0d92ed30 | pbrook | } |
678 | 0d92ed30 | pbrook | |
679 | d537cf6c | pbrook | nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59); |
680 | 64201201 | bellard | if (nvram == NULL) |
681 | 64201201 | bellard | return;
|
682 | 64201201 | bellard | sysctrl->nvram = nvram; |
683 | 64201201 | bellard | |
684 | 64201201 | bellard | /* Initialise NVRAM */
|
685 | 64201201 | bellard | PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
|
686 | 64201201 | bellard | kernel_base, kernel_size, |
687 | b6b8bd18 | bellard | kernel_cmdline, |
688 | 64201201 | bellard | initrd_base, initrd_size, |
689 | 64201201 | bellard | /* XXX: need an option to load a NVRAM image */
|
690 | b6b8bd18 | bellard | 0,
|
691 | b6b8bd18 | bellard | graphic_width, graphic_height, graphic_depth); |
692 | c0e564d5 | bellard | |
693 | c0e564d5 | bellard | /* Special port to get debug messages from Open-Firmware */
|
694 | c0e564d5 | bellard | register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL); |
695 | a541f297 | bellard | } |
696 | c0e564d5 | bellard | |
697 | c0e564d5 | bellard | QEMUMachine prep_machine = { |
698 | c0e564d5 | bellard | "prep",
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699 | c0e564d5 | bellard | "PowerPC PREP platform",
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700 | c0e564d5 | bellard | ppc_prep_init, |
701 | c0e564d5 | bellard | }; |