Archipelago » qemu

/*

 *  PowerPC emulation helpers for qemu.

 *

 *  Copyright (c) 2003-2007 Jocelyn Mayer

 *

 * This library is free software; you can redistribute it and/or

 * modify it under the terms of the GNU Lesser General Public

 * License as published by the Free Software Foundation; either

 * version 2 of the License, or (at your option) any later version.

 *

 * This library is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU

 * Lesser General Public License for more details.

 *

 * You should have received a copy of the GNU Lesser General Public

 * License along with this library; if not, write to the Free Software

 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA

 */

#include <stdarg.h>

#include <stdlib.h>

#include <stdio.h>

#include <string.h>

#include <inttypes.h>

#include <signal.h>

#include <assert.h>

#include "cpu.h"

#include "exec-all.h"

//#define DEBUG_MMU

//#define DEBUG_BATS

//#define DEBUG_SOFTWARE_TLB

//#define DEBUG_EXCEPTIONS

//#define FLUSH_ALL_TLBS

/*****************************************************************************/

/* PowerPC MMU emulation */

#if defined(CONFIG_USER_ONLY)

int cpu_ppc_handle_mmu_fault (CPUState *env, target_ulong address, int rw,

                              int is_user, int is_softmmu)

{

    int exception, error_code;

    if (rw == 2) {

        exception = EXCP_ISI;

        error_code = 0;

    } else {

        exception = EXCP_DSI;

        error_code = 0;

        if (rw)

            error_code |= 0x02000000;

        env->spr[SPR_DAR] = address;

        env->spr[SPR_DSISR] = error_code;

    }

    env->exception_index = exception;

    env->error_code = error_code;

    return 1;

}

target_phys_addr_t cpu_get_phys_page_debug (CPUState *env, target_ulong addr)

{

    return addr;

}

#else

/* Common routines used by software and hardware TLBs emulation */

static inline int pte_is_valid (target_ulong pte0)

{

    return pte0 & 0x80000000 ? 1 : 0;

}

static inline void pte_invalidate (target_ulong *pte0)

{

    *pte0 &= ~0x80000000;

}

#define PTE_PTEM_MASK 0x7FFFFFBF

#define PTE_CHECK_MASK (TARGET_PAGE_MASK | 0x7B)

static int pte_check (mmu_ctx_t *ctx,

                      target_ulong pte0, target_ulong pte1, int h, int rw)

{

    int access, ret;

    access = 0;

    ret = -1;

    /* Check validity and table match */

    if (pte_is_valid(pte0) && (h == ((pte0 >> 6) & 1))) {

        /* Check vsid & api */

        if ((pte0 & PTE_PTEM_MASK) == ctx->ptem) {

            if (ctx->raddr != (target_ulong)-1) {

                /* all matches should have equal RPN, WIMG & PP */

                if ((ctx->raddr & PTE_CHECK_MASK) != (pte1 & PTE_CHECK_MASK)) {

                    if (loglevel > 0)

                        fprintf(logfile, "Bad RPN/WIMG/PP\n");

                    return -3;

                }

            }

            /* Compute access rights */

            if (ctx->key == 0) {

                access = PAGE_READ;

                if ((pte1 & 0x00000003) != 0x3)

                    access |= PAGE_WRITE;

            } else {

                switch (pte1 & 0x00000003) {

                case 0x0:

                    access = 0;

                    break;

                case 0x1:

                case 0x3:

                    access = PAGE_READ;

                    break;

                case 0x2:

                    access = PAGE_READ | PAGE_WRITE;

                    break;

                }

            }

            /* Keep the matching PTE informations */

            ctx->raddr = pte1;

            ctx->prot = access;

            if ((rw == 0 && (access & PAGE_READ)) ||

                (rw == 1 && (access & PAGE_WRITE))) {

                /* Access granted */

#if defined (DEBUG_MMU)

                if (loglevel != 0)

                    fprintf(logfile, "PTE access granted !\n");

#endif

                ret = 0;

            } else {

                /* Access right violation */

#if defined (DEBUG_MMU)

                if (loglevel != 0)

                    fprintf(logfile, "PTE access rejected\n");

#endif

                ret = -2;

            }

        }

    }

    return ret;

}

static int pte_update_flags (mmu_ctx_t *ctx, target_ulong *pte1p,

                             int ret, int rw)

{

    int store = 0;

    /* Update page flags */

    if (!(*pte1p & 0x00000100)) {

        /* Update accessed flag */

        *pte1p |= 0x00000100;

        store = 1;

    }

    if (!(*pte1p & 0x00000080)) {

        if (rw == 1 && ret == 0) {

            /* Update changed flag */

            *pte1p |= 0x00000080;

            store = 1;

        } else {

            /* Force page fault for first write access */

            ctx->prot &= ~PAGE_WRITE;

        }

    }

    return store;

}

/* Software driven TLB helpers */

static int ppc6xx_tlb_getnum (CPUState *env, target_ulong eaddr,

                              int way, int is_code)

{

    int nr;

    /* Select TLB num in a way from address */

    nr = (eaddr >> TARGET_PAGE_BITS) & (env->tlb_per_way - 1);

    /* Select TLB way */

    nr += env->tlb_per_way * way;

    /* 6xx have separate TLBs for instructions and data */

    if (is_code && env->id_tlbs == 1)

        nr += env->nb_tlb;

    return nr;

}

void ppc6xx_tlb_invalidate_all (CPUState *env)

{

    ppc6xx_tlb_t *tlb;

    int nr, max;

#if defined (DEBUG_SOFTWARE_TLB) && 0

    if (loglevel != 0) {

        fprintf(logfile, "Invalidate all TLBs\n");

    }

#endif

    /* Invalidate all defined software TLB */

    max = env->nb_tlb;

    if (env->id_tlbs == 1)

        max *= 2;

    for (nr = 0; nr < max; nr++) {

        tlb = &env->tlb[nr].tlb6;

#if !defined(FLUSH_ALL_TLBS)

        tlb_flush_page(env, tlb->EPN);

#endif

        pte_invalidate(&tlb->pte0);

    }

#if defined(FLUSH_ALL_TLBS)

    tlb_flush(env, 1);

#endif

}

static inline void __ppc6xx_tlb_invalidate_virt (CPUState *env,

                                                 target_ulong eaddr,

                                                 int is_code, int match_epn)

{

#if !defined(FLUSH_ALL_TLBS)

    ppc6xx_tlb_t *tlb;

    int way, nr;

    /* Invalidate ITLB + DTLB, all ways */

    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way, is_code);

        tlb = &env->tlb[nr].tlb6;

        if (pte_is_valid(tlb->pte0) && (match_epn == 0 || eaddr == tlb->EPN)) {

#if defined (DEBUG_SOFTWARE_TLB)

            if (loglevel != 0) {

                fprintf(logfile, "TLB invalidate %d/%d " ADDRX "\n",

                        nr, env->nb_tlb, eaddr);

            }

#endif

            pte_invalidate(&tlb->pte0);

            tlb_flush_page(env, tlb->EPN);

        }

    }

#else

    /* XXX: PowerPC specification say this is valid as well */

    ppc6xx_tlb_invalidate_all(env);

#endif

}

void ppc6xx_tlb_invalidate_virt (CPUState *env, target_ulong eaddr,

                                 int is_code)

{

    __ppc6xx_tlb_invalidate_virt(env, eaddr, is_code, 0);

}

void ppc6xx_tlb_store (CPUState *env, target_ulong EPN, int way, int is_code,

                       target_ulong pte0, target_ulong pte1)

{

    ppc6xx_tlb_t *tlb;

    int nr;

    nr = ppc6xx_tlb_getnum(env, EPN, way, is_code);

    tlb = &env->tlb[nr].tlb6;

#if defined (DEBUG_SOFTWARE_TLB)

    if (loglevel != 0) {

        fprintf(logfile, "Set TLB %d/%d EPN " ADDRX " PTE0 " ADDRX

                " PTE1 " ADDRX "\n", nr, env->nb_tlb, EPN, pte0, pte1);

    }

#endif

    /* Invalidate any pending reference in Qemu for this virtual address */

    __ppc6xx_tlb_invalidate_virt(env, EPN, is_code, 1);

    tlb->pte0 = pte0;

    tlb->pte1 = pte1;

    tlb->EPN = EPN;

    /* Store last way for LRU mechanism */

    env->last_way = way;

}

static int ppc6xx_tlb_check (CPUState *env, mmu_ctx_t *ctx,

                             target_ulong eaddr, int rw, int access_type)

{

    ppc6xx_tlb_t *tlb;

    int nr, best, way;

    int ret;

    best = -1;

    ret = -1; /* No TLB found */

    for (way = 0; way < env->nb_ways; way++) {

        nr = ppc6xx_tlb_getnum(env, eaddr, way,

                               access_type == ACCESS_CODE ? 1 : 0);

        tlb = &env->tlb[nr].tlb6;

        /* This test "emulates" the PTE index match for hardware TLBs */

        if ((eaddr & TARGET_PAGE_MASK) != tlb->EPN) {

#if defined (DEBUG_SOFTWARE_TLB)

            if (loglevel != 0) {

                fprintf(logfile, "TLB %d/%d %s [" ADDRX " " ADDRX

                        "] <> " ADDRX "\n",

                        nr, env->nb_tlb,

                        pte_is_valid(tlb->pte0) ? "valid" : "inval",

                        tlb->EPN, tlb->EPN + TARGET_PAGE_SIZE, eaddr);

            }

#endif

            continue;

        }

#if defined (DEBUG_SOFTWARE_TLB)

        if (loglevel != 0) {

            fprintf(logfile, "TLB %d/%d %s " ADDRX " <> " ADDRX " " ADDRX

                    " %c %c\n",

                    nr, env->nb_tlb,

                    pte_is_valid(tlb->pte0) ? "valid" : "inval",

                    tlb->EPN, eaddr, tlb->pte1,

                    rw ? 'S' : 'L', access_type == ACCESS_CODE ? 'I' : 'D');

        }

#endif

        switch (pte_check(ctx, tlb->pte0, tlb->pte1, 0, rw)) {

        case -3:

            /* TLB inconsistency */

            return -1;

        case -2:

            /* Access violation */

            ret = -2;

            best = nr;

            break;

        case -1:

        default:

            /* No match */

            break;

        case 0:

            /* access granted */

            /* XXX: we should go on looping to check all TLBs consistency

             *      but we can speed-up the whole thing as the

             *      result would be undefined if TLBs are not consistent.

             */

            ret = 0;

            best = nr;

            goto done;

        }

    }

    if (best != -1) {

    done:

#if defined (DEBUG_SOFTWARE_TLB)

        if (loglevel != 0) {

            fprintf(logfile, "found TLB at addr 0x%08lx prot=0x%01x ret=%d\n",

                    ctx->raddr & TARGET_PAGE_MASK, ctx->prot, ret);

        }

#endif

        /* Update page flags */

        pte_update_flags(ctx, &env->tlb[best].tlb6.pte1, ret, rw);

    }

    return ret;

}

/* Perform BAT hit & translation */

static int get_bat (CPUState *env, mmu_ctx_t *ctx,

                    target_ulong virtual, int rw, int type)

{

    target_ulong *BATlt, *BATut, *BATu, *BATl;

    target_ulong base, BEPIl, BEPIu, bl;

    int i;

    int ret = -1;

#if defined (DEBUG_BATS)

    if (loglevel != 0) {

        fprintf(logfile, "%s: %cBAT v 0x" ADDRX "\n", __func__,

                type == ACCESS_CODE ? 'I' : 'D', virtual);

    }

#endif

    switch (type) {

    case ACCESS_CODE:

        BATlt = env->IBAT[1];

        BATut = env->IBAT[0];

        break;

    default:

        BATlt = env->DBAT[1];

        BATut = env->DBAT[0];

        break;

    }

#if defined (DEBUG_BATS)

    if (loglevel != 0) {

        fprintf(logfile, "%s...: %cBAT v 0x" ADDRX "\n", __func__,

                type == ACCESS_CODE ? 'I' : 'D', virtual);

    }

#endif

    base = virtual & 0xFFFC0000;

    for (i = 0; i < 4; i++) {

        BATu = &BATut[i];

        BATl = &BATlt[i];

        BEPIu = *BATu & 0xF0000000;

        BEPIl = *BATu & 0x0FFE0000;

        bl = (*BATu & 0x00001FFC) << 15;

#if defined (DEBUG_BATS)

        if (loglevel != 0) {

            fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX

                    " BATl 0x" ADDRX "\n",

                    __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,

                    *BATu, *BATl);

        }

#endif

        if ((virtual & 0xF0000000) == BEPIu &&

            ((virtual & 0x0FFE0000) & ~bl) == BEPIl) {

            /* BAT matches */

            if ((msr_pr == 0 && (*BATu & 0x00000002)) ||

                (msr_pr == 1 && (*BATu & 0x00000001))) {

                /* Get physical address */

                ctx->raddr = (*BATl & 0xF0000000) |

                    ((virtual & 0x0FFE0000 & bl) | (*BATl & 0x0FFE0000)) |

                    (virtual & 0x0001F000);

                if (*BATl & 0x00000001)

                    ctx->prot = PAGE_READ;

                if (*BATl & 0x00000002)

                    ctx->prot = PAGE_WRITE | PAGE_READ;

#if defined (DEBUG_BATS)

                if (loglevel != 0) {

                    fprintf(logfile, "BAT %d match: r 0x" PADDRX

                            " prot=%c%c\n",

                            i, ctx->raddr, ctx->prot & PAGE_READ ? 'R' : '-',

                            ctx->prot & PAGE_WRITE ? 'W' : '-');

                }

#endif

                ret = 0;

                break;

            }

        }

    }

    if (ret < 0) {

#if defined (DEBUG_BATS)

        if (loglevel != 0) {

            fprintf(logfile, "no BAT match for 0x" ADDRX ":\n", virtual);

            for (i = 0; i < 4; i++) {

                BATu = &BATut[i];

                BATl = &BATlt[i];

                BEPIu = *BATu & 0xF0000000;

                BEPIl = *BATu & 0x0FFE0000;

                bl = (*BATu & 0x00001FFC) << 15;

                fprintf(logfile, "%s: %cBAT%d v 0x" ADDRX " BATu 0x" ADDRX

                        " BATl 0x" ADDRX " \n\t"

                        "0x" ADDRX " 0x" ADDRX " 0x" ADDRX "\n",

                        __func__, type == ACCESS_CODE ? 'I' : 'D', i, virtual,

                        *BATu, *BATl, BEPIu, BEPIl, bl);

            }

        }

#endif

    }

    /* No hit */

    return ret;

}

/* PTE table lookup */

static int find_pte (mmu_ctx_t *ctx, int h, int rw)

{

    target_ulong base, pte0, pte1;

    int i, good = -1;

    int ret;

    ret = -1; /* No entry found */

    base = ctx->pg_addr[h];

    for (i = 0; i < 8; i++) {

        pte0 = ldl_phys(base + (i * 8));

        pte1 =  ldl_phys(base + (i * 8) + 4);

#if defined (DEBUG_MMU)

        if (loglevel > 0) {

            fprintf(logfile, "Load pte from 0x" ADDRX " => 0x" ADDRX

                    " 0x" ADDRX " %d %d %d 0x" ADDRX "\n",

                    base + (i * 8), pte0, pte1,

                    pte0 >> 31, h, (pte0 >> 6) & 1, ctx->ptem);

        }

#endif

        switch (pte_check(ctx, pte0, pte1, h, rw)) {

        case -3:

            /* PTE inconsistency */

            return -1;

        case -2:

            /* Access violation */

            ret = -2;

            good = i;

            break;

        case -1:

        default:

            /* No PTE match */

            break;

        case 0:

            /* access granted */

            /* XXX: we should go on looping to check all PTEs consistency

             *      but if we can speed-up the whole thing as the

             *      result would be undefined if PTEs are not consistent.

             */

            ret = 0;

            good = i;

            goto done;

        }

    }

    if (good != -1) {

    done:

#if defined (DEBUG_MMU)

        if (loglevel != 0) {

            fprintf(logfile, "found PTE at addr 0x" PADDRX " prot=0x%01x "

                    "ret=%d\n",

                    ctx->raddr, ctx->prot, ret);

        }

#endif

        /* Update page flags */

        pte1 = ctx->raddr;

        if (pte_update_flags(ctx, &pte1, ret, rw) == 1)

            stl_phys_notdirty(base + (good * 8) + 4, pte1);

    }

    return ret;

}

static inline target_phys_addr_t get_pgaddr (target_phys_addr_t sdr1,

                                             target_phys_addr_t hash,

                                             target_phys_addr_t mask)

{

    return (sdr1 & 0xFFFF0000) | (hash & mask);

}

/* Perform segment based translation */

static int get_segment (CPUState *env, mmu_ctx_t *ctx,

                        target_ulong eaddr, int rw, int type)

{

    target_phys_addr_t sdr, hash, mask;

    target_ulong sr, vsid, pgidx;

    int ret = -1, ret2;

    sr = env->sr[eaddr >> 28];

#if defined (DEBUG_MMU)

    if (loglevel > 0) {

        fprintf(logfile, "Check segment v=0x" ADDRX " %d 0x" ADDRX " nip=0x"

                ADDRX " lr=0x" ADDRX " ir=%d dr=%d pr=%d %d t=%d\n",

                eaddr, eaddr >> 28, sr, env->nip,

                env->lr, msr_ir, msr_dr, msr_pr, rw, type);

    }

#endif

    ctx->key = (((sr & 0x20000000) && msr_pr == 1) ||

                ((sr & 0x40000000) && msr_pr == 0)) ? 1 : 0;

    if ((sr & 0x80000000) == 0) {

#if defined (DEBUG_MMU)

        if (loglevel > 0)

            fprintf(logfile, "pte segment: key=%d n=0x" ADDRX "\n",

                    ctx->key, sr & 0x10000000);

#endif

        /* Check if instruction fetch is allowed, if needed */

        if (type != ACCESS_CODE || (sr & 0x10000000) == 0) {

            /* Page address translation */

            pgidx = (eaddr >> TARGET_PAGE_BITS) & 0xFFFF;

            vsid = sr & 0x00FFFFFF;

            hash = ((vsid ^ pgidx) & 0x0007FFFF) << 6;

            /* Primary table address */

            sdr = env->sdr1;

            mask = ((sdr & 0x000001FF) << 16) | 0xFFC0;

            ctx->pg_addr[0] = get_pgaddr(sdr, hash, mask);

            /* Secondary table address */

            hash = (~hash) & 0x01FFFFC0;

            ctx->pg_addr[1] = get_pgaddr(sdr, hash, mask);

            ctx->ptem = (vsid << 7) | (pgidx >> 10);

            /* Initialize real address with an invalid value */

            ctx->raddr = (target_ulong)-1;

            if (unlikely(PPC_MMU(env) == PPC_FLAGS_MMU_SOFT_6xx)) {

                /* Software TLB search */

                ret = ppc6xx_tlb_check(env, ctx, eaddr, rw, type);

            } else {

#if defined (DEBUG_MMU)

                if (loglevel != 0) {

                    fprintf(logfile, "0 sdr1=0x" PADDRX " vsid=0x%06x "

                            "api=0x%04x hash=0x%07x pg_addr=0x" PADDRX "\n",

                            sdr, (uint32_t)vsid, (uint32_t)pgidx,

                            (uint32_t)hash, ctx->pg_addr[0]);

                }

#endif

                /* Primary table lookup */

                ret = find_pte(ctx, 0, rw);

                if (ret < 0) {

                    /* Secondary table lookup */

#if defined (DEBUG_MMU)

                    if (eaddr != 0xEFFFFFFF && loglevel != 0) {

                        fprintf(logfile,

                                "1 sdr1=0x" PADDRX " vsid=0x%06x api=0x%04x "

                                "hash=0x%05x pg_addr=0x" PADDRX "\n",

                                sdr, (uint32_t)vsid, (uint32_t)pgidx,

                                (uint32_t)hash, ctx->pg_addr[1]);

                    }

#endif

                    ret2 = find_pte(ctx, 1, rw);

                    if (ret2 != -1)

                        ret = ret2;

                }

            }

        } else {

#if defined (DEBUG_MMU)

            if (loglevel != 0)

                fprintf(logfile, "No access allowed\n");

#endif

            ret = -3;

        }

    } else {

#if defined (DEBUG_MMU)

        if (loglevel != 0)

            fprintf(logfile, "direct store...\n");

#endif

        /* Direct-store segment : absolutely *BUGGY* for now */

        switch (type) {

        case ACCESS_INT:

            /* Integer load/store : only access allowed */

            break;

        case ACCESS_CODE:

            /* No code fetch is allowed in direct-store areas */

            return -4;

        case ACCESS_FLOAT:

            /* Floating point load/store */

            return -4;

        case ACCESS_RES:

            /* lwarx, ldarx or srwcx. */

            return -4;

        case ACCESS_CACHE:

            /* dcba, dcbt, dcbtst, dcbf, dcbi, dcbst, dcbz, or icbi */

            /* Should make the instruction do no-op.

             * As it already do no-op, it's quite easy :-)

             */

            ctx->raddr = eaddr;

            return 0;

        case ACCESS_EXT:

            /* eciwx or ecowx */

            return -4;

        default:

            if (logfile) {

                fprintf(logfile, "ERROR: instruction should not need "

                        "address translation\n");

            }

            return -4;

        }

        if ((rw == 1 || ctx->key != 1) && (rw == 0 || ctx->key != 0)) {

            ctx->raddr = eaddr;

            ret = 2;

        } else {

            ret = -2;

        }

    }

    return ret;

}

/* Generic TLB check function for embedded PowerPC implementations */

static int ppcemb_tlb_check (CPUState *env, ppcemb_tlb_t *tlb,

                             target_phys_addr_t *raddrp,

                             target_ulong address,

                             uint32_t pid, int ext, int i)

{

    target_ulong mask;

    /* Check valid flag */

    if (!(tlb->prot & PAGE_VALID)) {

        if (loglevel != 0)

            fprintf(logfile, "%s: TLB %d not valid\n", __func__, i);

        return -1;

    }

    mask = ~(tlb->size - 1);

    if (loglevel != 0) {

        fprintf(logfile, "%s: TLB %d address " ADDRX " PID %d <=> "

                ADDRX " " ADDRX " %d\n",

                __func__, i, address, pid, tlb->EPN, mask, (int)tlb->PID);

    }

    /* Check PID */

    if (tlb->PID != 0 && tlb->PID != pid)

        return -1;

    /* Check effective address */

    if ((address & mask) != tlb->EPN)

        return -1;

    *raddrp = (tlb->RPN & mask) | (address & ~mask);

    if (ext) {

        /* Extend the physical address to 36 bits */

        *raddrp |= (target_phys_addr_t)(tlb->RPN & 0xF) << 32;

    }

    return 0;

}

/* Generic TLB search function for PowerPC embedded implementations */

int ppcemb_tlb_search (CPUPPCState *env, target_ulong address, uint32_t pid)

{

    ppcemb_tlb_t *tlb;

    target_phys_addr_t raddr;

    int i, ret;

    /* Default return value is no match */

    ret = -1;

    for (i = 0; i < 64; i++) {

        tlb = &env->tlb[i].tlbe;

        if (ppcemb_tlb_check(env, tlb, &raddr, address, pid, 0, i) == 0) {

            ret = i;

            break;

        }

    }

    return ret;

}

/* Helpers specific to PowerPC 40x implementations */

void ppc4xx_tlb_invalidate_all (CPUState *env)

{

    ppcemb_tlb_t *tlb;

    int i;

    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        if (tlb->prot & PAGE_VALID) {

#if 0 // XXX: TLB have variable sizes then we flush all Qemu TLB.

            end = tlb->EPN + tlb->size;

            for (page = tlb->EPN; page < end; page += TARGET_PAGE_SIZE)

                tlb_flush_page(env, page);

#endif

            tlb->prot &= ~PAGE_VALID;

        }

    }

    tlb_flush(env, 1);

}

int mmu40x_get_physical_address (CPUState *env, mmu_ctx_t *ctx,

                                 target_ulong address, int rw, int access_type)

{

    ppcemb_tlb_t *tlb;

    target_phys_addr_t raddr;

    int i, ret, zsel, zpr;

    ret = -1;

    raddr = -1;

    for (i = 0; i < env->nb_tlb; i++) {

        tlb = &env->tlb[i].tlbe;

        if (ppcemb_tlb_check(env, tlb, &raddr, address,

                             env->spr[SPR_40x_PID], 0, i) < 0)

            continue;

        zsel = (tlb->attr >> 4) & 0xF;

        zpr = (env->spr[SPR_40x_ZPR] >> (28 - (2 * zsel))) & 0x3;

        if (loglevel != 0) {

            fprintf(logfile, "%s: TLB %d zsel %d zpr %d rw %d attr %08x\n",

                    __func__, i, zsel, zpr, rw, tlb->attr);

        }

        if (access_type == ACCESS_CODE) {

            /* Check execute enable bit */

            switch (zpr) {

            case 0x2:

                if (msr_pr)

                    goto check_exec_perm;

                goto exec_granted;

            case 0x0:

                if (msr_pr) {

                    ctx->prot = 0;

                    ret = -3;

                    break;

                }

                /* No break here */

            case 0x1:

            check_exec_perm:

                /* Check from TLB entry */

                if (!(tlb->prot & PAGE_EXEC)) {

                    ret = -3;

                } else {

                    if (tlb->prot & PAGE_WRITE) {

                        ctx->prot = PAGE_READ | PAGE_WRITE;

                    } else {

                        ctx->prot = PAGE_READ;

                    }

                    ret = 0;

                }

                break;

            case 0x3:

            exec_granted:

                /* All accesses granted */

                ctx->prot = PAGE_READ | PAGE_WRITE;

                ret = 0;

                break;

            }

        } else {

            switch (zpr) {

            case 0x2:

                if (msr_pr)

                    goto check_rw_perm;

                goto rw_granted;

            case 0x0:

                if (msr_pr) {

                    ctx->prot = 0;

                    ret = -2;

                    break;

                }

                /* No break here */

            case 0x1:

            check_rw_perm:

                /* Check from TLB entry */

                /* Check write protection bit */

                if (tlb->prot & PAGE_WRITE) {

                    ctx->prot = PAGE_READ | PAGE_WRITE;

                    ret = 0;

                } else {

                    ctx->prot = PAGE_READ;

                    if (rw)

                        ret = -2;

                    else

                        ret = 0;

                }

                break;

            case 0x3:

            rw_granted:

                /* All accesses granted */

                ctx->prot = PAGE_READ | PAGE_WRITE;

                ret = 0;

                break;

            }

        }

        if (ret >= 0) {

            ctx->raddr = raddr;

            if (loglevel != 0) {

                fprintf(logfile, "%s: access granted " ADDRX " => " REGX

                        " %d %d\n", __func__, address, ctx->raddr, ctx->prot,

                        ret);

            }

            return 0;

        }

    }

    if (loglevel != 0) {

        fprintf(logfile, "%s: access refused " ADDRX " => " REGX

                " %d %d\n", __func__, address, raddr, ctx->prot,

                ret);

    }

    return ret;

}

void store_40x_sler (CPUPPCState *env, uint32_t val)

{

    /* XXX: TO BE FIXED */

    if (val != 0x00000000) {

        cpu_abort(env, "Little-endian regions are not supported by now\n");

    }

    env->spr[SPR_405_SLER] = val;

}

static int check_physical (CPUState *env, mmu_ctx_t *ctx,

                           target_ulong eaddr, int rw)

{

    int in_plb, ret;

    ctx->raddr = eaddr;

    ctx->prot = PAGE_READ;

    ret = 0;

    if (unlikely(msr_pe != 0 && PPC_MMU(env) == PPC_FLAGS_MMU_403)) {

        /* 403 family add some particular protections,

         * using PBL/PBU registers for accesses with no translation.

         */

        in_plb =

            /* Check PLB validity */

            (env->pb[0] < env->pb[1] &&

             /* and address in plb area */

             eaddr >= env->pb[0] && eaddr < env->pb[1]) ||

            (env->pb[2] < env->pb[3] &&

             eaddr >= env->pb[2] && eaddr < env->pb[3]) ? 1 : 0;

        if (in_plb ^ msr_px) {

            /* Access in protected area */

            if (rw == 1) {

                /* Access is not allowed */

                ret = -2;

            }