Revision 36081602 hw/ppc405_uc.c

b/hw/ppc405_uc.c
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    SDRAM0_CFGDATA = 0x011,
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};
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static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size)
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static uint32_t sdram_bcr (target_phys_addr_t ram_base,
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                           target_phys_addr_t ram_size)
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{
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    uint32_t bcr;
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......
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        sdram->irq = irq;
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        sdram->nbanks = nbanks;
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        memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t));
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        memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t));
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        memcpy(sdram->ram_bases, ram_bases,
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               nbanks * sizeof(target_phys_addr_t));
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        memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
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        memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t));
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        memcpy(sdram->ram_sizes, ram_sizes,
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               nbanks * sizeof(target_phys_addr_t));
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        sdram_reset(sdram);
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        qemu_register_reset(&sdram_reset, sdram);
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        ppc_dcr_register(env, SDRAM0_CFGADDR,
......
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        }
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        mask = mask >> 1;
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    }
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}
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static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
......
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            qemu_irq_lower(gpt->irqs[i]);
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        mask = mask >> 1;
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    }
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}
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static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)

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