Revision 36081602 hw/ppc405_uc.c
| b/hw/ppc405_uc.c | ||
|---|---|---|
| 924 | 924 |
SDRAM0_CFGDATA = 0x011, |
| 925 | 925 |
}; |
| 926 | 926 |
|
| 927 |
static uint32_t sdram_bcr (target_phys_addr_t ram_base, target_phys_addr_t ram_size) |
|
| 927 |
static uint32_t sdram_bcr (target_phys_addr_t ram_base, |
|
| 928 |
target_phys_addr_t ram_size) |
|
| 928 | 929 |
{
|
| 929 | 930 |
uint32_t bcr; |
| 930 | 931 |
|
| ... | ... | |
| 1217 | 1218 |
sdram->irq = irq; |
| 1218 | 1219 |
sdram->nbanks = nbanks; |
| 1219 | 1220 |
memset(sdram->ram_bases, 0, 4 * sizeof(target_phys_addr_t)); |
| 1220 |
memcpy(sdram->ram_bases, ram_bases, nbanks * sizeof(target_phys_addr_t)); |
|
| 1221 |
memcpy(sdram->ram_bases, ram_bases, |
|
| 1222 |
nbanks * sizeof(target_phys_addr_t)); |
|
| 1221 | 1223 |
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t)); |
| 1222 |
memcpy(sdram->ram_sizes, ram_sizes, nbanks * sizeof(target_phys_addr_t)); |
|
| 1224 |
memcpy(sdram->ram_sizes, ram_sizes, |
|
| 1225 |
nbanks * sizeof(target_phys_addr_t)); |
|
| 1223 | 1226 |
sdram_reset(sdram); |
| 1224 | 1227 |
qemu_register_reset(&sdram_reset, sdram); |
| 1225 | 1228 |
ppc_dcr_register(env, SDRAM0_CFGADDR, |
| ... | ... | |
| 2212 | 2215 |
} |
| 2213 | 2216 |
mask = mask >> 1; |
| 2214 | 2217 |
} |
| 2215 |
|
|
| 2216 | 2218 |
} |
| 2217 | 2219 |
|
| 2218 | 2220 |
static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt) |
| ... | ... | |
| 2228 | 2230 |
qemu_irq_lower(gpt->irqs[i]); |
| 2229 | 2231 |
mask = mask >> 1; |
| 2230 | 2232 |
} |
| 2231 |
|
|
| 2232 | 2233 |
} |
| 2233 | 2234 |
|
| 2234 | 2235 |
static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt) |
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