/hw/ppc_chrp.c - Diff - qemu - Greek Research and Technology Network's projects

Revision 36081602 hw/ppc_chrp.c

b/hw/ppc_chrp.c
46	46
47	47	/* DBDMA: currently no op - should suffice right now */
48	48
49		static void dbdma_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	49	static void dbdma_writeb (void *opaque,
	50	target_phys_addr_t addr, uint32_t value)
50	51	{
51	52	printf("%s: 0x" PADDRX " <= 0x%08x\n", __func__, addr, value);
52	53	}
53	54
54		static void dbdma_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
	55	static void dbdma_writew (void *opaque,
	56	target_phys_addr_t addr, uint32_t value)
55	57	{
56	58	}
57	59
58		static void dbdma_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
	60	static void dbdma_writel (void *opaque,
	61	target_phys_addr_t addr, uint32_t value)
59	62	{
60	63	}
61	64
62	65	static uint32_t dbdma_readb (void *opaque, target_phys_addr_t addr)
63	66	{
64	67	printf("%s: 0x" PADDRX " => 0x00000000\n", __func__, addr);
	68
65	69	return 0;
66	70	}
67	71
...	...
92	96	uint8_t data[0x2000];
93	97	} MacIONVRAMState;
94	98
95		static void macio_nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
	99	static void macio_nvram_writeb (void *opaque,
	100	target_phys_addr_t addr, uint32_t value)
96	101	{
97	102	MacIONVRAMState *s = opaque;
98	103	addr = (addr >> 4) & 0x1fff;
...	...
108	113	addr = (addr >> 4) & 0x1fff;
109	114	value = s->data[addr];
110	115	// printf("macio_nvram_readb %04x = %02x\n", addr, value);
	116
111	117	return value;
112	118	}
113	119
...	...
123	129	&macio_nvram_readb,
124	130	};
125	131
126		static MacIONVRAMState *macio_nvram_init(void)
	132	static MacIONVRAMState *macio_nvram_init (void)
127	133	{
128	134	MacIONVRAMState *s;
129	135	s = qemu_mallocz(sizeof(MacIONVRAMState));
...	...
131	137	return NULL;
132	138	macio_nvram_mem_index = cpu_register_io_memory(0, macio_nvram_read,
133	139	macio_nvram_write, s);
	140
134	141	return s;
135	142	}
136	143
137		static void macio_map(PCIDevice *pci_dev, int region_num,
138		uint32_t addr, uint32_t size, int type)
	144	static void macio_map (PCIDevice *pci_dev, int region_num,
	145	uint32_t addr, uint32_t size, int type)
139	146	{
140	147	if (heathrow_pic_mem_index >= 0) {
141	148	cpu_register_physical_memory(addr + 0x00000, 0x1000,
...	...
152	159	openpic_mem_index);
153	160	}
154	161	if (macio_nvram_mem_index >= 0)
155		cpu_register_physical_memory(addr + 0x60000, 0x20000, macio_nvram_mem_index);
	162	cpu_register_physical_memory(addr + 0x60000, 0x20000,
	163	macio_nvram_mem_index);
156	164	}
157	165
158		static void macio_init(PCIBus *bus, int device_id)
	166	static void macio_init (PCIBus *bus, int device_id)
159	167	{
160	168	PCIDevice *d;
161	169
...	...
204	212
205	213	/* temporary frame buffer OSI calls for the video.x driver. The right
206	214	solution is to modify the driver to use VGA PCI I/Os */
207		static int vga_osi_call(CPUState *env)
	215	/* XXX: to be removed. This is no way related to emulation */
	216	static int vga_osi_call (CPUState *env)
208	217	{
209	218	static int vga_vbl_enabled;
210	219	int linesize;
...	...
264	273	fprintf(stderr, "unsupported OSI call R5=" REGX "\n", env->gpr[5]);
265	274	break;
266	275	}
	276
267	277	return 1; /* osi_call handled */
268	278	}
269	279
270		static uint8_t nvram_chksum(const uint8_t *buf, int n)
	280	static uint8_t nvram_chksum (const uint8_t *buf, int n)
271	281	{
272	282	int sum, i;
273	283	sum = 0;
...	...
277	287	}
278	288
279	289	/* set a free Mac OS NVRAM partition */
280		void pmac_format_nvram_partition(uint8_t *buf, int len)
	290	void pmac_format_nvram_partition (uint8_t *buf, int len)
281	291	{
282	292	char partition_name[12] = "wwwwwwwwwwww";
283	293
...	...
503	513	((qemu_irq *)env->irq_inputs)[PPC970_INPUT_HRESET];
504	514	break;
505	515	default:
506		cpu_abort(env,
507		"Only bus model not supported on mac99 machine\n");
	516	cpu_abort(env, "Bus model not supported on mac99 machine\n");
508	517	exit(1);
509	518	}
510	519	}

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Revision 36081602 hw/ppc_chrp.c