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1
/*
2
 * QEMU PPC PREP hardware System Emulator
3
 *
4
 * Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
6
 * Permission is hereby granted, free of charge, to any person obtaining a copy
7
 * of this software and associated documentation files (the "Software"), to deal
8
 * in the Software without restriction, including without limitation the rights
9
 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10
 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
13
 * The above copyright notice and this permission notice shall be included in
14
 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
23
 */
24
#include "vl.h"
25

    
26
//#define HARD_DEBUG_PPC_IO
27
//#define DEBUG_PPC_IO
28

    
29
#define BIOS_FILENAME "ppc_rom.bin"
30
#define KERNEL_LOAD_ADDR 0x01000000
31
#define INITRD_LOAD_ADDR 0x01800000
32

    
33
extern int loglevel;
34
extern FILE *logfile;
35

    
36
#if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
37
#define DEBUG_PPC_IO
38
#endif
39

    
40
#if defined (HARD_DEBUG_PPC_IO)
41
#define PPC_IO_DPRINTF(fmt, args...)                     \
42
do {                                                     \
43
    if (loglevel & CPU_LOG_IOPORT) {                     \
44
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
45
    } else {                                             \
46
        printf("%s : " fmt, __func__ , ##args);          \
47
    }                                                    \
48
} while (0)
49
#elif defined (DEBUG_PPC_IO)
50
#define PPC_IO_DPRINTF(fmt, args...)                     \
51
do {                                                     \
52
    if (loglevel & CPU_LOG_IOPORT) {                     \
53
        fprintf(logfile, "%s: " fmt, __func__ , ##args); \
54
    }                                                    \
55
} while (0)
56
#else
57
#define PPC_IO_DPRINTF(fmt, args...) do { } while (0)
58
#endif
59

    
60
/* Constants for devices init */
61
static const int ide_iobase[2] = { 0x1f0, 0x170 };
62
static const int ide_iobase2[2] = { 0x3f6, 0x376 };
63
static const int ide_irq[2] = { 13, 13 };
64

    
65
#define NE2000_NB_MAX 6
66

    
67
static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
68
static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
69

    
70
//static PITState *pit;
71

    
72
/* ISA IO ports bridge */
73
#define PPC_IO_BASE 0x80000000
74

    
75
/* Speaker port 0x61 */
76
int speaker_data_on;
77
int dummy_refresh_clock;
78

    
79
static void speaker_ioport_write (void *opaque, uint32_t addr, uint32_t val)
80
{
81
#if 0
82
    speaker_data_on = (val >> 1) & 1;
83
    pit_set_gate(pit, 2, val & 1);
84
#endif
85
}
86

    
87
static uint32_t speaker_ioport_read (void *opaque, uint32_t addr)
88
{
89
#if 0
90
    int out;
91
    out = pit_get_out(pit, 2, qemu_get_clock(vm_clock));
92
    dummy_refresh_clock ^= 1;
93
    return (speaker_data_on << 1) | pit_get_gate(pit, 2) | (out << 5) |
94
        (dummy_refresh_clock << 4);
95
#endif
96
    return 0;
97
}
98

    
99
/* PCI intack register */
100
/* Read-only register (?) */
101
static void _PPC_intack_write (void *opaque,
102
                               target_phys_addr_t addr, uint32_t value)
103
{
104
    //    printf("%s: 0x%08x => 0x%08x\n", __func__, addr, value);
105
}
106

    
107
static inline uint32_t _PPC_intack_read (target_phys_addr_t addr)
108
{
109
    uint32_t retval = 0;
110

    
111
    if (addr == 0xBFFFFFF0)
112
        retval = pic_intack_read(isa_pic);
113
    //   printf("%s: 0x%08x <= %d\n", __func__, addr, retval);
114

    
115
    return retval;
116
}
117

    
118
static uint32_t PPC_intack_readb (void *opaque, target_phys_addr_t addr)
119
{
120
    return _PPC_intack_read(addr);
121
}
122

    
123
static uint32_t PPC_intack_readw (void *opaque, target_phys_addr_t addr)
124
{
125
#ifdef TARGET_WORDS_BIGENDIAN
126
    return bswap16(_PPC_intack_read(addr));
127
#else
128
    return _PPC_intack_read(addr);
129
#endif
130
}
131

    
132
static uint32_t PPC_intack_readl (void *opaque, target_phys_addr_t addr)
133
{
134
#ifdef TARGET_WORDS_BIGENDIAN
135
    return bswap32(_PPC_intack_read(addr));
136
#else
137
    return _PPC_intack_read(addr);
138
#endif
139
}
140

    
141
static CPUWriteMemoryFunc *PPC_intack_write[] = {
142
    &_PPC_intack_write,
143
    &_PPC_intack_write,
144
    &_PPC_intack_write,
145
};
146

    
147
static CPUReadMemoryFunc *PPC_intack_read[] = {
148
    &PPC_intack_readb,
149
    &PPC_intack_readw,
150
    &PPC_intack_readl,
151
};
152

    
153
/* PowerPC control and status registers */
154
#if 0 // Not used
155
static struct {
156
    /* IDs */
157
    uint32_t veni_devi;
158
    uint32_t revi;
159
    /* Control and status */
160
    uint32_t gcsr;
161
    uint32_t xcfr;
162
    uint32_t ct32;
163
    uint32_t mcsr;
164
    /* General purpose registers */
165
    uint32_t gprg[6];
166
    /* Exceptions */
167
    uint32_t feen;
168
    uint32_t fest;
169
    uint32_t fema;
170
    uint32_t fecl;
171
    uint32_t eeen;
172
    uint32_t eest;
173
    uint32_t eecl;
174
    uint32_t eeint;
175
    uint32_t eemck0;
176
    uint32_t eemck1;
177
    /* Error diagnostic */
178
} XCSR;
179

180
static void PPC_XCSR_writeb (void *opaque,
181
                             target_phys_addr_t addr, uint32_t value)
182
{
183
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
184
}
185

186
static void PPC_XCSR_writew (void *opaque,
187
                             target_phys_addr_t addr, uint32_t value)
188
{
189
#ifdef TARGET_WORDS_BIGENDIAN
190
    value = bswap16(value);
191
#endif
192
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
193
}
194

    
195
static void PPC_XCSR_writel (void *opaque,
196
                             target_phys_addr_t addr, uint32_t value)
197
{
198
#ifdef TARGET_WORDS_BIGENDIAN
199
    value = bswap32(value);
200
#endif
201
    printf("%s: 0x%08lx => 0x%08x\n", __func__, (long)addr, value);
202
}
203

    
204
static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
205
{
206
    uint32_t retval = 0;
207

    
208
    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
209

    
210
    return retval;
211
}
212

    
213
static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
214
{
215
    uint32_t retval = 0;
216

    
217
    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
218
#ifdef TARGET_WORDS_BIGENDIAN
219
    retval = bswap16(retval);
220
#endif
221

    
222
    return retval;
223
}
224

    
225
static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
226
{
227
    uint32_t retval = 0;
228

    
229
    printf("%s: 0x%08lx <= %d\n", __func__, (long)addr, retval);
230
#ifdef TARGET_WORDS_BIGENDIAN
231
    retval = bswap32(retval);
232
#endif
233

    
234
    return retval;
235
}
236

    
237
static CPUWriteMemoryFunc *PPC_XCSR_write[] = {
238
    &PPC_XCSR_writeb,
239
    &PPC_XCSR_writew,
240
    &PPC_XCSR_writel,
241
};
242

    
243
static CPUReadMemoryFunc *PPC_XCSR_read[] = {
244
    &PPC_XCSR_readb,
245
    &PPC_XCSR_readw,
246
    &PPC_XCSR_readl,
247
};
248
#endif
249

    
250
/* Fake super-io ports for PREP platform (Intel 82378ZB) */
251
typedef struct sysctrl_t {
252
    m48t59_t *nvram;
253
    uint8_t state;
254
    uint8_t syscontrol;
255
    uint8_t fake_io[2];
256
    int contiguous_map;
257
    int endian;
258
} sysctrl_t;
259

    
260
enum {
261
    STATE_HARDFILE = 0x01,
262
};
263

    
264
static sysctrl_t *sysctrl;
265

    
266
static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
267
{
268
    sysctrl_t *sysctrl = opaque;
269

    
270
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
271
    sysctrl->fake_io[addr - 0x0398] = val;
272
}
273

    
274
static uint32_t PREP_io_read (void *opaque, uint32_t addr)
275
{
276
    sysctrl_t *sysctrl = opaque;
277

    
278
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE,
279
                   sysctrl->fake_io[addr - 0x0398]);
280
    return sysctrl->fake_io[addr - 0x0398];
281
}
282

    
283
static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
284
{
285
    sysctrl_t *sysctrl = opaque;
286

    
287
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr - PPC_IO_BASE, val);
288
    switch (addr) {
289
    case 0x0092:
290
        /* Special port 92 */
291
        /* Check soft reset asked */
292
        if (val & 0x01) {
293
            //            cpu_interrupt(first_cpu, PPC_INTERRUPT_RESET);
294
        }
295
        /* Check LE mode */
296
        if (val & 0x02) {
297
            sysctrl->endian = 1;
298
        } else {
299
            sysctrl->endian = 0;
300
        }
301
        break;
302
    case 0x0800:
303
        /* Motorola CPU configuration register : read-only */
304
        break;
305
    case 0x0802:
306
        /* Motorola base module feature register : read-only */
307
        break;
308
    case 0x0803:
309
        /* Motorola base module status register : read-only */
310
        break;
311
    case 0x0808:
312
        /* Hardfile light register */
313
        if (val & 1)
314
            sysctrl->state |= STATE_HARDFILE;
315
        else
316
            sysctrl->state &= ~STATE_HARDFILE;
317
        break;
318
    case 0x0810:
319
        /* Password protect 1 register */
320
        if (sysctrl->nvram != NULL)
321
            m48t59_toggle_lock(sysctrl->nvram, 1);
322
        break;
323
    case 0x0812:
324
        /* Password protect 2 register */
325
        if (sysctrl->nvram != NULL)
326
            m48t59_toggle_lock(sysctrl->nvram, 2);
327
        break;
328
    case 0x0814:
329
        /* L2 invalidate register */
330
        //        tlb_flush(first_cpu, 1);
331
        break;
332
    case 0x081C:
333
        /* system control register */
334
        sysctrl->syscontrol = val & 0x0F;
335
        break;
336
    case 0x0850:
337
        /* I/O map type register */
338
        sysctrl->contiguous_map = val & 0x01;
339
        break;
340
    default:
341
        printf("ERROR: unaffected IO port write: %04lx => %02x\n",
342
               (long)addr, val);
343
        break;
344
    }
345
}
346

    
347
static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
348
{
349
    sysctrl_t *sysctrl = opaque;
350
    uint32_t retval = 0xFF;
351

    
352
    switch (addr) {
353
    case 0x0092:
354
        /* Special port 92 */
355
        retval = 0x00;
356
        break;
357
    case 0x0800:
358
        /* Motorola CPU configuration register */
359
        retval = 0xEF; /* MPC750 */
360
        break;
361
    case 0x0802:
362
        /* Motorola Base module feature register */
363
        retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
364
        break;
365
    case 0x0803:
366
        /* Motorola base module status register */
367
        retval = 0xE0; /* Standard MPC750 */
368
        break;
369
    case 0x080C:
370
        /* Equipment present register:
371
         *  no L2 cache
372
         *  no upgrade processor
373
         *  no cards in PCI slots
374
         *  SCSI fuse is bad
375
         */
376
        retval = 0x3C;
377
        break;
378
    case 0x0810:
379
        /* Motorola base module extended feature register */
380
        retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
381
        break;
382
    case 0x0814:
383
        /* L2 invalidate: don't care */
384
        break;
385
    case 0x0818:
386
        /* Keylock */
387
        retval = 0x00;
388
        break;
389
    case 0x081C:
390
        /* system control register
391
         * 7 - 6 / 1 - 0: L2 cache enable
392
         */
393
        retval = sysctrl->syscontrol;
394
        break;
395
    case 0x0823:
396
        /* */
397
        retval = 0x03; /* no L2 cache */
398
        break;
399
    case 0x0850:
400
        /* I/O map type register */
401
        retval = sysctrl->contiguous_map;
402
        break;
403
    default:
404
        printf("ERROR: unaffected IO port: %04lx read\n", (long)addr);
405
        break;
406
    }
407
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr - PPC_IO_BASE, retval);
408

    
409
    return retval;
410
}
411

    
412
static inline target_phys_addr_t prep_IO_address (sysctrl_t *sysctrl,
413
                                                  target_phys_addr_t addr)
414
{
415
    if (sysctrl->contiguous_map == 0) {
416
        /* 64 KB contiguous space for IOs */
417
        addr &= 0xFFFF;
418
    } else {
419
        /* 8 MB non-contiguous space for IOs */
420
        addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
421
    }
422

    
423
    return addr;
424
}
425

    
426
static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
427
                                uint32_t value)
428
{
429
    sysctrl_t *sysctrl = opaque;
430

    
431
    addr = prep_IO_address(sysctrl, addr);
432
    cpu_outb(NULL, addr, value);
433
}
434

    
435
static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
436
{
437
    sysctrl_t *sysctrl = opaque;
438
    uint32_t ret;
439

    
440
    addr = prep_IO_address(sysctrl, addr);
441
    ret = cpu_inb(NULL, addr);
442

    
443
    return ret;
444
}
445

    
446
static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
447
                                uint32_t value)
448
{
449
    sysctrl_t *sysctrl = opaque;
450

    
451
    addr = prep_IO_address(sysctrl, addr);
452
#ifdef TARGET_WORDS_BIGENDIAN
453
    value = bswap16(value);
454
#endif
455
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
456
    cpu_outw(NULL, addr, value);
457
}
458

    
459
static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
460
{
461
    sysctrl_t *sysctrl = opaque;
462
    uint32_t ret;
463

    
464
    addr = prep_IO_address(sysctrl, addr);
465
    ret = cpu_inw(NULL, addr);
466
#ifdef TARGET_WORDS_BIGENDIAN
467
    ret = bswap16(ret);
468
#endif
469
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
470

    
471
    return ret;
472
}
473

    
474
static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
475
                                uint32_t value)
476
{
477
    sysctrl_t *sysctrl = opaque;
478

    
479
    addr = prep_IO_address(sysctrl, addr);
480
#ifdef TARGET_WORDS_BIGENDIAN
481
    value = bswap32(value);
482
#endif
483
    PPC_IO_DPRINTF("0x%08lx => 0x%08x\n", (long)addr, value);
484
    cpu_outl(NULL, addr, value);
485
}
486

    
487
static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
488
{
489
    sysctrl_t *sysctrl = opaque;
490
    uint32_t ret;
491

    
492
    addr = prep_IO_address(sysctrl, addr);
493
    ret = cpu_inl(NULL, addr);
494
#ifdef TARGET_WORDS_BIGENDIAN
495
    ret = bswap32(ret);
496
#endif
497
    PPC_IO_DPRINTF("0x%08lx <= 0x%08x\n", (long)addr, ret);
498

    
499
    return ret;
500
}
501

    
502
CPUWriteMemoryFunc *PPC_prep_io_write[] = {
503
    &PPC_prep_io_writeb,
504
    &PPC_prep_io_writew,
505
    &PPC_prep_io_writel,
506
};
507

    
508
CPUReadMemoryFunc *PPC_prep_io_read[] = {
509
    &PPC_prep_io_readb,
510
    &PPC_prep_io_readw,
511
    &PPC_prep_io_readl,
512
};
513

    
514
#define NVRAM_SIZE        0x2000
515

    
516
/* PowerPC PREP hardware initialisation */
517
static void ppc_prep_init (int ram_size, int vga_ram_size, int boot_device,
518
                           DisplayState *ds, const char **fd_filename,
519
                           int snapshot, const char *kernel_filename,
520
                           const char *kernel_cmdline,
521
                           const char *initrd_filename,
522
                           const char *cpu_model)
523
{
524
    CPUState *env;
525
    char buf[1024];
526
    m48t59_t *nvram;
527
    int PPC_io_memory;
528
    int linux_boot, i, nb_nics1, bios_size;
529
    unsigned long bios_offset;
530
    uint32_t kernel_base, kernel_size, initrd_base, initrd_size;
531
    ppc_def_t *def;
532
    PCIBus *pci_bus;
533
    qemu_irq *i8259;
534

    
535
    sysctrl = qemu_mallocz(sizeof(sysctrl_t));
536
    if (sysctrl == NULL)
537
        return;
538

    
539
    linux_boot = (kernel_filename != NULL);
540

    
541
    /* init CPUs */
542

    
543
    env = cpu_init();
544
    qemu_register_reset(&cpu_ppc_reset, env);
545
    register_savevm("cpu", 0, 3, cpu_save, cpu_load, env);
546

    
547
    /* Default CPU is a 604 */
548
    if (cpu_model == NULL)
549
        cpu_model = "604";
550
    ppc_find_by_name(cpu_model, &def);
551
    if (def == NULL) {
552
        cpu_abort(env, "Unable to find PowerPC CPU definition\n");
553
    }
554
    cpu_ppc_register(env, def);
555
    /* Set time-base frequency to 100 Mhz */
556
    cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
557

    
558
    /* allocate RAM */
559
    cpu_register_physical_memory(0, ram_size, IO_MEM_RAM);
560

    
561
    /* allocate and load BIOS */
562
    bios_offset = ram_size + vga_ram_size;
563
    snprintf(buf, sizeof(buf), "%s/%s", bios_dir, BIOS_FILENAME);
564
    bios_size = load_image(buf, phys_ram_base + bios_offset);
565
    if (bios_size < 0 || bios_size > BIOS_SIZE) {
566
        cpu_abort(env, "qemu: could not load PPC PREP bios '%s'\n", buf);
567
        exit(1);
568
    }
569
    bios_size = (bios_size + 0xfff) & ~0xfff;
570
    cpu_register_physical_memory((uint32_t)(-bios_size),
571
                                 bios_size, bios_offset | IO_MEM_ROM);
572

    
573
    if (linux_boot) {
574
        kernel_base = KERNEL_LOAD_ADDR;
575
        /* now we can load the kernel */
576
        kernel_size = load_image(kernel_filename, phys_ram_base + kernel_base);
577
        if (kernel_size < 0) {
578
            cpu_abort(env, "qemu: could not load kernel '%s'\n",
579
                      kernel_filename);
580
            exit(1);
581
        }
582
        /* load initrd */
583
        if (initrd_filename) {
584
            initrd_base = INITRD_LOAD_ADDR;
585
            initrd_size = load_image(initrd_filename,
586
                                     phys_ram_base + initrd_base);
587
            if (initrd_size < 0) {
588
                cpu_abort(env, "qemu: could not load initial ram disk '%s'\n",
589
                          initrd_filename);
590
                exit(1);
591
            }
592
        } else {
593
            initrd_base = 0;
594
            initrd_size = 0;
595
        }
596
        boot_device = 'm';
597
    } else {
598
        kernel_base = 0;
599
        kernel_size = 0;
600
        initrd_base = 0;
601
        initrd_size = 0;
602
    }
603

    
604
    isa_mem_base = 0xc0000000;
605
    if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
606
        cpu_abort(env, "Only 6xx bus is supported on PREP machine\n");
607
        exit(1);
608
    }
609
    i8259 = i8259_init(first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
610
    pci_bus = pci_prep_init(i8259);
611
    //    pci_bus = i440fx_init();
612
    /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
613
    PPC_io_memory = cpu_register_io_memory(0, PPC_prep_io_read,
614
                                           PPC_prep_io_write, sysctrl);
615
    cpu_register_physical_memory(0x80000000, 0x00800000, PPC_io_memory);
616

    
617
    /* init basic PC hardware */
618
    pci_vga_init(pci_bus, ds, phys_ram_base + ram_size, ram_size,
619
                 vga_ram_size, 0, 0);
620
    //    openpic = openpic_init(0x00000000, 0xF0000000, 1);
621
    //    pit = pit_init(0x40, i8259[0]);
622
    rtc_init(0x70, i8259[8]);
623

    
624
    serial_init(0x3f8, i8259[4], serial_hds[0]);
625
    nb_nics1 = nb_nics;
626
    if (nb_nics1 > NE2000_NB_MAX)
627
        nb_nics1 = NE2000_NB_MAX;
628
    for(i = 0; i < nb_nics1; i++) {
629
        if (nd_table[0].model == NULL
630
            || strcmp(nd_table[0].model, "ne2k_isa") == 0) {
631
            isa_ne2000_init(ne2000_io[i], i8259[ne2000_irq[i]], &nd_table[i]);
632
        } else if (strcmp(nd_table[0].model, "?") == 0) {
633
            fprintf(stderr, "qemu: Supported NICs: ne2k_isa\n");
634
            exit (1);
635
        } else {
636
            /* Why ? */
637
            cpu_abort(env, "qemu: Unsupported NIC: %s\n", nd_table[0].model);
638
            exit (1);
639
        }
640
    }
641

    
642
    for(i = 0; i < 2; i++) {
643
        isa_ide_init(ide_iobase[i], ide_iobase2[i], i8259[ide_irq[i]],
644
                     bs_table[2 * i], bs_table[2 * i + 1]);
645
    }
646
    i8042_init(i8259[1], i8259[12], 0x60);
647
    DMA_init(1);
648
    //    AUD_init();
649
    //    SB16_init();
650

    
651
    fdctrl_init(i8259[6], 2, 0, 0x3f0, fd_table);
652

    
653
    /* Register speaker port */
654
    register_ioport_read(0x61, 1, 1, speaker_ioport_read, NULL);
655
    register_ioport_write(0x61, 1, 1, speaker_ioport_write, NULL);
656
    /* Register fake IO ports for PREP */
657
    register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
658
    register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
659
    /* System control ports */
660
    register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
661
    register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
662
    register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
663
    register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
664
    /* PCI intack location */
665
    PPC_io_memory = cpu_register_io_memory(0, PPC_intack_read,
666
                                           PPC_intack_write, NULL);
667
    cpu_register_physical_memory(0xBFFFFFF0, 0x4, PPC_io_memory);
668
    /* PowerPC control and status register group */
669
#if 0
670
    PPC_io_memory = cpu_register_io_memory(0, PPC_XCSR_read, PPC_XCSR_write,
671
                                           NULL);
672
    cpu_register_physical_memory(0xFEFF0000, 0x1000, PPC_io_memory);
673
#endif
674

    
675
    if (usb_enabled) {
676
        usb_ohci_init_pci(pci_bus, 3, -1);
677
    }
678

    
679
    nvram = m48t59_init(i8259[8], 0, 0x0074, NVRAM_SIZE, 59);
680
    if (nvram == NULL)
681
        return;
682
    sysctrl->nvram = nvram;
683

    
684
    /* Initialise NVRAM */
685
    PPC_NVRAM_set_params(nvram, NVRAM_SIZE, "PREP", ram_size, boot_device,
686
                         kernel_base, kernel_size,
687
                         kernel_cmdline,
688
                         initrd_base, initrd_size,
689
                         /* XXX: need an option to load a NVRAM image */
690
                         0,
691
                         graphic_width, graphic_height, graphic_depth);
692

    
693
    /* Special port to get debug messages from Open-Firmware */
694
    register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
695
}
696

    
697
QEMUMachine prep_machine = {
698
    "prep",
699
    "PowerPC PREP platform",
700
    ppc_prep_init,
701
};