Revision 36388314
| b/hw/mips_int.c | ||
|---|---|---|
| 24 | 24 |
#include "mips_cpudevs.h" |
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#include "cpu.h" |
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/* Raise IRQ to CPU if necessary. It must be called every time the active |
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IRQ may change */ |
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void cpu_mips_update_irq(CPUState *env) |
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{
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if ((env->CP0_Status & (1 << CP0St_IE)) && |
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!(env->CP0_Status & (1 << CP0St_EXL)) && |
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!(env->CP0_Status & (1 << CP0St_ERL)) && |
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!(env->hflags & MIPS_HFLAG_DM)) {
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if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) && |
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!(env->interrupt_request & CPU_INTERRUPT_HARD)) {
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} else |
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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static void cpu_mips_irq_request(void *opaque, int irq, int level) |
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{
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CPUState *env = (CPUState *)opaque; |
| ... | ... | |
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} else {
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env->CP0_Cause &= ~(1 << (irq + CP0Ca_IP)); |
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} |
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cpu_mips_update_irq(env); |
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|
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if (env->CP0_Cause & CP0Ca_IP_mask) {
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cpu_interrupt(env, CPU_INTERRUPT_HARD); |
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} else {
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cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
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} |
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} |
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|
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void cpu_mips_irq_init_cpu(CPUState *env) |
| b/target-mips/cpu.h | ||
|---|---|---|
| 597 | 597 |
void cpu_mips_start_count(CPUState *env); |
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void cpu_mips_stop_count(CPUState *env); |
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/* mips_int.c */ |
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void cpu_mips_update_irq (CPUState *env); |
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|
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/* helper.c */ |
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int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, |
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int mmu_idx, int is_softmmu); |
| b/target-mips/op_helper.c | ||
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default: cpu_abort(env, "Invalid MMU mode!\n"); break; |
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} |
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} |
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cpu_mips_update_irq(env); |
|
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} |
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|
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void helper_mttc0_status(target_ulong arg1) |
| ... | ... | |
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else |
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cpu_mips_start_count(env); |
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} |
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|
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/* Handle the software interrupt as an hardware one, as they |
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are very similar */ |
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if (arg1 & CP0Ca_IP_mask) {
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cpu_mips_update_irq(env); |
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} |
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} |
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|
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void helper_mtc0_ebase (target_ulong arg1) |
| ... | ... | |
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target_ulong t0 = env->CP0_Status; |
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env->CP0_Status = t0 & ~(1 << CP0St_IE); |
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cpu_mips_update_irq(env); |
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return t0; |
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} |
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|
| ... | ... | |
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target_ulong t0 = env->CP0_Status; |
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|
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env->CP0_Status = t0 | (1 << CP0St_IE); |
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cpu_mips_update_irq(env); |
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|
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return t0; |
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} |
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