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root / target-mips @ 36388314

Name Size
TODO 1.9 kB
cpu.h 18 kB
exec.h 2.6 kB
helper.c 21 kB
helper.h 8.6 kB
machine.c 10.6 kB
mips-defs.h 2.1 kB
op_helper.c 96 kB
translate.c 359.5 kB
translate_init.c 22.5 kB

Latest revisions

# Date Author Comment
36388314 07/24/2010 02:40 pm Edgar E. Iglesias

mips: Correct MIPS interrupt glue logic for icount

When hw interrupt pending bits in CP0_Cause are set, the CPU should
see the hw interrupt line as active. The CPU may or may not take the
interrupt based on internal state (global irq mask etc) but the glue...
3fc00a7b 07/17/2010 05:13 pm Aurelien Jarno

target-mips: fix xtlb exception for loongson

Loongson 2E and 2F use the same entry for xtlb and tlb exception, at
offset 0x000.

Signed-off-by: Aurelien Jarno <>
161f85e6 07/11/2010 11:24 am Aurelien Jarno

target-mips: add loongson 2E & 2F integer instructions

This patch adds support for loongson 2E & 2F instructions. They are the
same instructions, but differ by the opcode encoding.

Signed-off-by: Aurelien Jarno <>
a88790a1 07/03/2010 09:48 am Paolo Bonzini

remove exec-all.h inclusion from cpu.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>
10eb0cc0 07/03/2010 09:48 am Paolo Bonzini

move cpu_pc_from_tb to target-*/exec.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>
83dae095 07/03/2010 09:47 am Paolo Bonzini

remove unused stuff from */exec.h

Signed-off-by: Paolo Bonzini <>
Signed-off-by: Blue Swirl <>
afa88c3a 07/02/2010 12:45 am Aurelien Jarno

target-mips: add Loongson support prefetch

Loongson CPU uses a load to zero register for prefetch.
Emulate it as a NOP.

Signed-off-by: Aurelien Jarno <>
5c13fdfd 07/01/2010 08:48 am Aurelien Jarno

target-mips: split load and store

Signed-off-by: Aurelien Jarno <>
6fbab869 06/30/2010 09:00 pm Aurelien Jarno

target-mips: fix DINSU instruction

Signed-off-by: Aurelien Jarno <>
aa8f4009 06/30/2010 12:26 am Aurelien Jarno

target-mips: enable movn/movz on loongson 2E & 2F

Signed-off-by: Aurelien Jarno <>

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