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/*
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* gdb server stub
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*
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* Copyright (c) 2003-2005 Fabrice Bellard
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#include "config.h" |
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#ifdef CONFIG_USER_ONLY
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#include <stdlib.h> |
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#include <stdio.h> |
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#include <stdarg.h> |
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#include <string.h> |
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#include <errno.h> |
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#include <unistd.h> |
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#include <fcntl.h> |
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#include "qemu.h" |
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#else
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#include "qemu-common.h" |
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#include "qemu-char.h" |
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#include "sysemu.h" |
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#include "gdbstub.h" |
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#endif
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#include "qemu_socket.h" |
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#ifdef _WIN32
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/* XXX: these constants may be independent of the host ones even for Unix */
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#ifndef SIGTRAP
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#define SIGTRAP 5 |
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#endif
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#ifndef SIGINT
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#define SIGINT 2 |
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#endif
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#else
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#include <signal.h> |
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#endif
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//#define DEBUG_GDB
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enum RSState {
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RS_IDLE, |
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RS_GETLINE, |
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RS_CHKSUM1, |
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RS_CHKSUM2, |
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RS_SYSCALL, |
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}; |
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typedef struct GDBState { |
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CPUState *env; /* current CPU */
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enum RSState state; /* parsing state */ |
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char line_buf[4096]; |
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int line_buf_index;
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int line_csum;
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uint8_t last_packet[4100];
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int last_packet_len;
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int signal;
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#ifdef CONFIG_USER_ONLY
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int fd;
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int running_state;
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#else
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CharDriverState *chr; |
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#endif
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} GDBState; |
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/* By default use no IRQs and no timers while single stepping so as to
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* make single stepping like an ICE HW step.
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*/
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static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER; |
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#ifdef CONFIG_USER_ONLY
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/* XXX: This is not thread safe. Do we care? */
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static int gdbserver_fd = -1; |
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/* XXX: remove this hack. */
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static GDBState gdbserver_state;
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static int get_char(GDBState *s) |
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{
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uint8_t ch; |
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int ret;
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for(;;) {
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ret = recv(s->fd, &ch, 1, 0); |
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if (ret < 0) { |
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if (errno == ECONNRESET)
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s->fd = -1;
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if (errno != EINTR && errno != EAGAIN)
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return -1; |
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} else if (ret == 0) { |
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close(s->fd); |
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s->fd = -1;
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return -1; |
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} else {
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break;
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} |
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} |
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return ch;
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} |
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#endif
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/* GDB stub state for use by semihosting syscalls. */
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static GDBState *gdb_syscall_state;
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static gdb_syscall_complete_cb gdb_current_syscall_cb;
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enum {
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GDB_SYS_UNKNOWN, |
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GDB_SYS_ENABLED, |
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GDB_SYS_DISABLED, |
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} gdb_syscall_mode; |
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/* If gdb is connected when the first semihosting syscall occurs then use
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remote gdb syscalls. Otherwise use native file IO. */
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int use_gdb_syscalls(void) |
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{
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if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
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gdb_syscall_mode = (gdb_syscall_state ? GDB_SYS_ENABLED |
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: GDB_SYS_DISABLED); |
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} |
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return gdb_syscall_mode == GDB_SYS_ENABLED;
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} |
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/* Resume execution. */
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static inline void gdb_continue(GDBState *s) |
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{
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#ifdef CONFIG_USER_ONLY
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s->running_state = 1;
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#else
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vm_start(); |
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#endif
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} |
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static void put_buffer(GDBState *s, const uint8_t *buf, int len) |
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{
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#ifdef CONFIG_USER_ONLY
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int ret;
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while (len > 0) { |
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ret = send(s->fd, buf, len, 0);
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if (ret < 0) { |
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if (errno != EINTR && errno != EAGAIN)
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return;
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} else {
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buf += ret; |
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len -= ret; |
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} |
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} |
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#else
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qemu_chr_write(s->chr, buf, len); |
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#endif
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} |
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static inline int fromhex(int v) |
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{
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if (v >= '0' && v <= '9') |
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return v - '0'; |
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else if (v >= 'A' && v <= 'F') |
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return v - 'A' + 10; |
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else if (v >= 'a' && v <= 'f') |
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return v - 'a' + 10; |
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else
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return 0; |
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} |
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static inline int tohex(int v) |
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{
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if (v < 10) |
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return v + '0'; |
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else
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return v - 10 + 'a'; |
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} |
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static void memtohex(char *buf, const uint8_t *mem, int len) |
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{
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int i, c;
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char *q;
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q = buf; |
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for(i = 0; i < len; i++) { |
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c = mem[i]; |
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*q++ = tohex(c >> 4);
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*q++ = tohex(c & 0xf);
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} |
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*q = '\0';
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} |
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static void hextomem(uint8_t *mem, const char *buf, int len) |
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{
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int i;
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for(i = 0; i < len; i++) { |
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mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]); |
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buf += 2;
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} |
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} |
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/* return -1 if error, 0 if OK */
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static int put_packet(GDBState *s, char *buf) |
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{
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int len, csum, i;
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uint8_t *p; |
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#ifdef DEBUG_GDB
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printf("reply='%s'\n", buf);
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#endif
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for(;;) {
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p = s->last_packet; |
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*(p++) = '$';
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len = strlen(buf); |
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memcpy(p, buf, len); |
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p += len; |
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csum = 0;
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for(i = 0; i < len; i++) { |
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csum += buf[i]; |
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} |
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*(p++) = '#';
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*(p++) = tohex((csum >> 4) & 0xf); |
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*(p++) = tohex((csum) & 0xf);
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s->last_packet_len = p - s->last_packet; |
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put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len); |
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#ifdef CONFIG_USER_ONLY
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i = get_char(s); |
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if (i < 0) |
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return -1; |
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if (i == '+') |
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break;
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#else
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break;
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#endif
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} |
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return 0; |
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} |
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#if defined(TARGET_I386)
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#ifdef TARGET_X86_64
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static const uint8_t gdb_x86_64_regs[16] = { |
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R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP, |
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8, 9, 10, 11, 12, 13, 14, 15, |
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}; |
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#endif
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static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
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{
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int i, fpus, nb_regs;
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uint8_t *p; |
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p = mem_buf; |
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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nb_regs = 16;
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for(i = 0; i < 16; i++) { |
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*(uint64_t *)p = tswap64(env->regs[gdb_x86_64_regs[i]]); |
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p += 8;
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} |
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*(uint64_t *)p = tswap64(env->eip); |
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p += 8;
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} else
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#endif
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{
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nb_regs = 8;
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for(i = 0; i < 8; i++) { |
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*(uint32_t *)p = tswap32(env->regs[i]); |
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p += 4;
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} |
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*(uint32_t *)p = tswap32(env->eip); |
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p += 4;
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} |
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*(uint32_t *)p = tswap32(env->eflags); |
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_CS].selector); |
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_SS].selector); |
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_DS].selector); |
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_ES].selector); |
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_FS].selector); |
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p += 4;
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*(uint32_t *)p = tswap32(env->segs[R_GS].selector); |
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p += 4;
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for(i = 0; i < 8; i++) { |
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/* XXX: convert floats */
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#ifdef USE_X86LDOUBLE
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memcpy(p, &env->fpregs[i], 10);
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#else
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memset(p, 0, 10); |
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#endif
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p += 10;
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} |
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*(uint32_t *)p = tswap32(env->fpuc); /* fctrl */
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p += 4;
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fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11; |
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*(uint32_t *)p = tswap32(fpus); /* fstat */
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p += 4;
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*(uint32_t *)p = 0; /* ftag */ |
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p += 4;
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*(uint32_t *)p = 0; /* fiseg */ |
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p += 4;
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*(uint32_t *)p = 0; /* fioff */ |
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p += 4;
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*(uint32_t *)p = 0; /* foseg */ |
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p += 4;
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*(uint32_t *)p = 0; /* fooff */ |
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p += 4;
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*(uint32_t *)p = 0; /* fop */ |
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p += 4;
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for(i = 0; i < nb_regs; i++) { |
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*(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(0));
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p += 8;
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*(uint64_t *)p = tswap64(env->xmm_regs[i].XMM_Q(1));
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p += 8;
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} |
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*(uint32_t *)p = tswap32(env->mxcsr); |
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p += 4;
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return p - mem_buf;
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} |
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|
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static inline void cpu_gdb_load_seg(CPUState *env, const uint8_t **pp, |
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int sreg)
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{
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const uint8_t *p;
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uint32_t sel; |
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p = *pp; |
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sel = tswap32(*(uint32_t *)p); |
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p += 4;
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if (sel != env->segs[sreg].selector) {
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#if defined(CONFIG_USER_ONLY)
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cpu_x86_load_seg(env, sreg, sel); |
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#else
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/* XXX: do it with a debug function which does not raise an
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exception */
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#endif
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} |
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*pp = p; |
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} |
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|
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static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
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{
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const uint8_t *p = mem_buf;
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int i, nb_regs;
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uint16_t fpus; |
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#ifdef TARGET_X86_64
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if (env->hflags & HF_CS64_MASK) {
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nb_regs = 16;
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for(i = 0; i < 16; i++) { |
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env->regs[gdb_x86_64_regs[i]] = tswap64(*(uint64_t *)p); |
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p += 8;
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} |
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env->eip = tswap64(*(uint64_t *)p); |
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p += 8;
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} else
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#endif
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{
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nb_regs = 8;
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for(i = 0; i < 8; i++) { |
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env->regs[i] = tswap32(*(uint32_t *)p); |
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p += 4;
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} |
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env->eip = tswap32(*(uint32_t *)p); |
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p += 4;
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} |
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env->eflags = tswap32(*(uint32_t *)p); |
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p += 4;
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cpu_gdb_load_seg(env, &p, R_CS); |
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cpu_gdb_load_seg(env, &p, R_SS); |
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cpu_gdb_load_seg(env, &p, R_DS); |
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cpu_gdb_load_seg(env, &p, R_ES); |
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cpu_gdb_load_seg(env, &p, R_FS); |
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cpu_gdb_load_seg(env, &p, R_GS); |
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|
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/* FPU state */
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for(i = 0; i < 8; i++) { |
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/* XXX: convert floats */
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#ifdef USE_X86LDOUBLE
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memcpy(&env->fpregs[i], p, 10);
|
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#endif
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p += 10;
|
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} |
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env->fpuc = tswap32(*(uint32_t *)p); /* fctrl */
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p += 4;
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fpus = tswap32(*(uint32_t *)p); |
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p += 4;
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env->fpstt = (fpus >> 11) & 7; |
| 401 |
env->fpus = fpus & ~0x3800;
|
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p += 4 * 6; |
| 403 |
|
| 404 |
if (size >= ((p - mem_buf) + 16 * nb_regs + 4)) { |
| 405 |
/* SSE state */
|
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for(i = 0; i < nb_regs; i++) { |
| 407 |
env->xmm_regs[i].XMM_Q(0) = tswap64(*(uint64_t *)p);
|
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p += 8;
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env->xmm_regs[i].XMM_Q(1) = tswap64(*(uint64_t *)p);
|
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p += 8;
|
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} |
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env->mxcsr = tswap32(*(uint32_t *)p); |
| 413 |
p += 4;
|
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} |
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} |
| 416 |
|
| 417 |
#elif defined (TARGET_PPC)
|
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static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 419 |
{
|
| 420 |
uint32_t *registers = (uint32_t *)mem_buf, tmp; |
| 421 |
int i;
|
| 422 |
|
| 423 |
/* fill in gprs */
|
| 424 |
for(i = 0; i < 32; i++) { |
| 425 |
registers[i] = tswapl(env->gpr[i]); |
| 426 |
} |
| 427 |
/* fill in fprs */
|
| 428 |
for (i = 0; i < 32; i++) { |
| 429 |
registers[(i * 2) + 32] = tswapl(*((uint32_t *)&env->fpr[i])); |
| 430 |
registers[(i * 2) + 33] = tswapl(*((uint32_t *)&env->fpr[i] + 1)); |
| 431 |
} |
| 432 |
/* nip, msr, ccr, lnk, ctr, xer, mq */
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registers[96] = tswapl(env->nip);
|
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registers[97] = tswapl(env->msr);
|
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tmp = 0;
|
| 436 |
for (i = 0; i < 8; i++) |
| 437 |
tmp |= env->crf[i] << (32 - ((i + 1) * 4)); |
| 438 |
registers[98] = tswapl(tmp);
|
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registers[99] = tswapl(env->lr);
|
| 440 |
registers[100] = tswapl(env->ctr);
|
| 441 |
registers[101] = tswapl(ppc_load_xer(env));
|
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registers[102] = 0; |
| 443 |
|
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return 103 * 4; |
| 445 |
} |
| 446 |
|
| 447 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 448 |
{
|
| 449 |
uint32_t *registers = (uint32_t *)mem_buf; |
| 450 |
int i;
|
| 451 |
|
| 452 |
/* fill in gprs */
|
| 453 |
for (i = 0; i < 32; i++) { |
| 454 |
env->gpr[i] = tswapl(registers[i]); |
| 455 |
} |
| 456 |
/* fill in fprs */
|
| 457 |
for (i = 0; i < 32; i++) { |
| 458 |
*((uint32_t *)&env->fpr[i]) = tswapl(registers[(i * 2) + 32]); |
| 459 |
*((uint32_t *)&env->fpr[i] + 1) = tswapl(registers[(i * 2) + 33]); |
| 460 |
} |
| 461 |
/* nip, msr, ccr, lnk, ctr, xer, mq */
|
| 462 |
env->nip = tswapl(registers[96]);
|
| 463 |
ppc_store_msr(env, tswapl(registers[97]));
|
| 464 |
registers[98] = tswapl(registers[98]); |
| 465 |
for (i = 0; i < 8; i++) |
| 466 |
env->crf[i] = (registers[98] >> (32 - ((i + 1) * 4))) & 0xF; |
| 467 |
env->lr = tswapl(registers[99]);
|
| 468 |
env->ctr = tswapl(registers[100]);
|
| 469 |
ppc_store_xer(env, tswapl(registers[101]));
|
| 470 |
} |
| 471 |
#elif defined (TARGET_SPARC)
|
| 472 |
#ifdef TARGET_ABI32
|
| 473 |
#define tswap_abi(val) tswap32(val &0xffffffff) |
| 474 |
#else
|
| 475 |
#define tswap_abi(val) tswapl(val)
|
| 476 |
#endif
|
| 477 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 478 |
{
|
| 479 |
#ifdef TARGET_ABI32
|
| 480 |
abi_ulong *registers = (abi_ulong *)mem_buf; |
| 481 |
#else
|
| 482 |
target_ulong *registers = (target_ulong *)mem_buf; |
| 483 |
#endif
|
| 484 |
int i;
|
| 485 |
|
| 486 |
/* fill in g0..g7 */
|
| 487 |
for(i = 0; i < 8; i++) { |
| 488 |
registers[i] = tswap_abi(env->gregs[i]); |
| 489 |
} |
| 490 |
/* fill in register window */
|
| 491 |
for(i = 0; i < 24; i++) { |
| 492 |
registers[i + 8] = tswap_abi(env->regwptr[i]);
|
| 493 |
} |
| 494 |
#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
|
| 495 |
/* fill in fprs */
|
| 496 |
for (i = 0; i < 32; i++) { |
| 497 |
registers[i + 32] = tswap_abi(*((uint32_t *)&env->fpr[i]));
|
| 498 |
} |
| 499 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
| 500 |
registers[64] = tswap_abi(env->y);
|
| 501 |
{
|
| 502 |
uint32_t tmp; |
| 503 |
|
| 504 |
tmp = GET_PSR(env); |
| 505 |
registers[65] = tswap32(tmp);
|
| 506 |
} |
| 507 |
registers[66] = tswap_abi(env->wim);
|
| 508 |
registers[67] = tswap_abi(env->tbr);
|
| 509 |
registers[68] = tswap_abi(env->pc);
|
| 510 |
registers[69] = tswap_abi(env->npc);
|
| 511 |
registers[70] = tswap_abi(env->fsr);
|
| 512 |
registers[71] = 0; /* csr */ |
| 513 |
registers[72] = 0; |
| 514 |
return 73 * sizeof(uint32_t); |
| 515 |
#else
|
| 516 |
/* fill in fprs */
|
| 517 |
for (i = 0; i < 64; i += 2) { |
| 518 |
uint64_t tmp; |
| 519 |
|
| 520 |
tmp = ((uint64_t)*(uint32_t *)&env->fpr[i]) << 32;
|
| 521 |
tmp |= *(uint32_t *)&env->fpr[i + 1];
|
| 522 |
registers[i / 2 + 32] = tswap64(tmp); |
| 523 |
} |
| 524 |
registers[64] = tswapl(env->pc);
|
| 525 |
registers[65] = tswapl(env->npc);
|
| 526 |
registers[66] = tswapl(((uint64_t)GET_CCR(env) << 32) | |
| 527 |
((env->asi & 0xff) << 24) | |
| 528 |
((env->pstate & 0xfff) << 8) | |
| 529 |
GET_CWP64(env)); |
| 530 |
registers[67] = tswapl(env->fsr);
|
| 531 |
registers[68] = tswapl(env->fprs);
|
| 532 |
registers[69] = tswapl(env->y);
|
| 533 |
return 70 * sizeof(target_ulong); |
| 534 |
#endif
|
| 535 |
} |
| 536 |
|
| 537 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 538 |
{
|
| 539 |
#ifdef TARGET_ABI32
|
| 540 |
abi_ulong *registers = (abi_ulong *)mem_buf; |
| 541 |
#else
|
| 542 |
target_ulong *registers = (target_ulong *)mem_buf; |
| 543 |
#endif
|
| 544 |
int i;
|
| 545 |
|
| 546 |
/* fill in g0..g7 */
|
| 547 |
for(i = 0; i < 7; i++) { |
| 548 |
env->gregs[i] = tswap_abi(registers[i]); |
| 549 |
} |
| 550 |
/* fill in register window */
|
| 551 |
for(i = 0; i < 24; i++) { |
| 552 |
env->regwptr[i] = tswap_abi(registers[i + 8]);
|
| 553 |
} |
| 554 |
#if !defined(TARGET_SPARC64) || defined(TARGET_ABI32)
|
| 555 |
/* fill in fprs */
|
| 556 |
for (i = 0; i < 32; i++) { |
| 557 |
*((uint32_t *)&env->fpr[i]) = tswap_abi(registers[i + 32]);
|
| 558 |
} |
| 559 |
/* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
|
| 560 |
env->y = tswap_abi(registers[64]);
|
| 561 |
PUT_PSR(env, tswap_abi(registers[65]));
|
| 562 |
env->wim = tswap_abi(registers[66]);
|
| 563 |
env->tbr = tswap_abi(registers[67]);
|
| 564 |
env->pc = tswap_abi(registers[68]);
|
| 565 |
env->npc = tswap_abi(registers[69]);
|
| 566 |
env->fsr = tswap_abi(registers[70]);
|
| 567 |
#else
|
| 568 |
for (i = 0; i < 64; i += 2) { |
| 569 |
uint64_t tmp; |
| 570 |
|
| 571 |
tmp = tswap64(registers[i / 2 + 32]); |
| 572 |
*((uint32_t *)&env->fpr[i]) = tmp >> 32;
|
| 573 |
*((uint32_t *)&env->fpr[i + 1]) = tmp & 0xffffffff; |
| 574 |
} |
| 575 |
env->pc = tswapl(registers[64]);
|
| 576 |
env->npc = tswapl(registers[65]);
|
| 577 |
{
|
| 578 |
uint64_t tmp = tswapl(registers[66]);
|
| 579 |
|
| 580 |
PUT_CCR(env, tmp >> 32);
|
| 581 |
env->asi = (tmp >> 24) & 0xff; |
| 582 |
env->pstate = (tmp >> 8) & 0xfff; |
| 583 |
PUT_CWP64(env, tmp & 0xff);
|
| 584 |
} |
| 585 |
env->fsr = tswapl(registers[67]);
|
| 586 |
env->fprs = tswapl(registers[68]);
|
| 587 |
env->y = tswapl(registers[69]);
|
| 588 |
#endif
|
| 589 |
} |
| 590 |
#undef tswap_abi
|
| 591 |
#elif defined (TARGET_ARM)
|
| 592 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 593 |
{
|
| 594 |
int i;
|
| 595 |
uint8_t *ptr; |
| 596 |
|
| 597 |
ptr = mem_buf; |
| 598 |
/* 16 core integer registers (4 bytes each). */
|
| 599 |
for (i = 0; i < 16; i++) |
| 600 |
{
|
| 601 |
*(uint32_t *)ptr = tswapl(env->regs[i]); |
| 602 |
ptr += 4;
|
| 603 |
} |
| 604 |
/* 8 FPA registers (12 bytes each), FPS (4 bytes).
|
| 605 |
Not yet implemented. */
|
| 606 |
memset (ptr, 0, 8 * 12 + 4); |
| 607 |
ptr += 8 * 12 + 4; |
| 608 |
/* CPSR (4 bytes). */
|
| 609 |
*(uint32_t *)ptr = tswapl (cpsr_read(env)); |
| 610 |
ptr += 4;
|
| 611 |
|
| 612 |
return ptr - mem_buf;
|
| 613 |
} |
| 614 |
|
| 615 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 616 |
{
|
| 617 |
int i;
|
| 618 |
uint8_t *ptr; |
| 619 |
|
| 620 |
ptr = mem_buf; |
| 621 |
/* Core integer registers. */
|
| 622 |
for (i = 0; i < 16; i++) |
| 623 |
{
|
| 624 |
env->regs[i] = tswapl(*(uint32_t *)ptr); |
| 625 |
ptr += 4;
|
| 626 |
} |
| 627 |
/* Ignore FPA regs and scr. */
|
| 628 |
ptr += 8 * 12 + 4; |
| 629 |
cpsr_write (env, tswapl(*(uint32_t *)ptr), 0xffffffff);
|
| 630 |
} |
| 631 |
#elif defined (TARGET_M68K)
|
| 632 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 633 |
{
|
| 634 |
int i;
|
| 635 |
uint8_t *ptr; |
| 636 |
CPU_DoubleU u; |
| 637 |
|
| 638 |
ptr = mem_buf; |
| 639 |
/* D0-D7 */
|
| 640 |
for (i = 0; i < 8; i++) { |
| 641 |
*(uint32_t *)ptr = tswapl(env->dregs[i]); |
| 642 |
ptr += 4;
|
| 643 |
} |
| 644 |
/* A0-A7 */
|
| 645 |
for (i = 0; i < 8; i++) { |
| 646 |
*(uint32_t *)ptr = tswapl(env->aregs[i]); |
| 647 |
ptr += 4;
|
| 648 |
} |
| 649 |
*(uint32_t *)ptr = tswapl(env->sr); |
| 650 |
ptr += 4;
|
| 651 |
*(uint32_t *)ptr = tswapl(env->pc); |
| 652 |
ptr += 4;
|
| 653 |
/* F0-F7. The 68881/68040 have 12-bit extended precision registers.
|
| 654 |
ColdFire has 8-bit double precision registers. */
|
| 655 |
for (i = 0; i < 8; i++) { |
| 656 |
u.d = env->fregs[i]; |
| 657 |
*(uint32_t *)ptr = tswap32(u.l.upper); |
| 658 |
*(uint32_t *)ptr = tswap32(u.l.lower); |
| 659 |
} |
| 660 |
/* FP control regs (not implemented). */
|
| 661 |
memset (ptr, 0, 3 * 4); |
| 662 |
ptr += 3 * 4; |
| 663 |
|
| 664 |
return ptr - mem_buf;
|
| 665 |
} |
| 666 |
|
| 667 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 668 |
{
|
| 669 |
int i;
|
| 670 |
uint8_t *ptr; |
| 671 |
CPU_DoubleU u; |
| 672 |
|
| 673 |
ptr = mem_buf; |
| 674 |
/* D0-D7 */
|
| 675 |
for (i = 0; i < 8; i++) { |
| 676 |
env->dregs[i] = tswapl(*(uint32_t *)ptr); |
| 677 |
ptr += 4;
|
| 678 |
} |
| 679 |
/* A0-A7 */
|
| 680 |
for (i = 0; i < 8; i++) { |
| 681 |
env->aregs[i] = tswapl(*(uint32_t *)ptr); |
| 682 |
ptr += 4;
|
| 683 |
} |
| 684 |
env->sr = tswapl(*(uint32_t *)ptr); |
| 685 |
ptr += 4;
|
| 686 |
env->pc = tswapl(*(uint32_t *)ptr); |
| 687 |
ptr += 4;
|
| 688 |
/* F0-F7. The 68881/68040 have 12-bit extended precision registers.
|
| 689 |
ColdFire has 8-bit double precision registers. */
|
| 690 |
for (i = 0; i < 8; i++) { |
| 691 |
u.l.upper = tswap32(*(uint32_t *)ptr); |
| 692 |
u.l.lower = tswap32(*(uint32_t *)ptr); |
| 693 |
env->fregs[i] = u.d; |
| 694 |
} |
| 695 |
/* FP control regs (not implemented). */
|
| 696 |
ptr += 3 * 4; |
| 697 |
} |
| 698 |
#elif defined (TARGET_MIPS)
|
| 699 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 700 |
{
|
| 701 |
int i;
|
| 702 |
uint8_t *ptr; |
| 703 |
|
| 704 |
ptr = mem_buf; |
| 705 |
for (i = 0; i < 32; i++) |
| 706 |
{
|
| 707 |
*(target_ulong *)ptr = tswapl(env->active_tc.gpr[i]); |
| 708 |
ptr += sizeof(target_ulong);
|
| 709 |
} |
| 710 |
|
| 711 |
*(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Status); |
| 712 |
ptr += sizeof(target_ulong);
|
| 713 |
|
| 714 |
*(target_ulong *)ptr = tswapl(env->active_tc.LO[0]);
|
| 715 |
ptr += sizeof(target_ulong);
|
| 716 |
|
| 717 |
*(target_ulong *)ptr = tswapl(env->active_tc.HI[0]);
|
| 718 |
ptr += sizeof(target_ulong);
|
| 719 |
|
| 720 |
*(target_ulong *)ptr = tswapl(env->CP0_BadVAddr); |
| 721 |
ptr += sizeof(target_ulong);
|
| 722 |
|
| 723 |
*(target_ulong *)ptr = (int32_t)tswap32(env->CP0_Cause); |
| 724 |
ptr += sizeof(target_ulong);
|
| 725 |
|
| 726 |
*(target_ulong *)ptr = tswapl(env->active_tc.PC); |
| 727 |
ptr += sizeof(target_ulong);
|
| 728 |
|
| 729 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
| 730 |
{
|
| 731 |
for (i = 0; i < 32; i++) |
| 732 |
{
|
| 733 |
if (env->CP0_Status & (1 << CP0St_FR)) |
| 734 |
*(target_ulong *)ptr = tswapl(env->fpu->fpr[i].d); |
| 735 |
else
|
| 736 |
*(target_ulong *)ptr = tswap32(env->fpu->fpr[i].w[FP_ENDIAN_IDX]); |
| 737 |
ptr += sizeof(target_ulong);
|
| 738 |
} |
| 739 |
|
| 740 |
*(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr31); |
| 741 |
ptr += sizeof(target_ulong);
|
| 742 |
|
| 743 |
*(target_ulong *)ptr = (int32_t)tswap32(env->fpu->fcr0); |
| 744 |
ptr += sizeof(target_ulong);
|
| 745 |
} |
| 746 |
|
| 747 |
/* "fp", pseudo frame pointer. Not yet implemented in gdb. */
|
| 748 |
*(target_ulong *)ptr = 0;
|
| 749 |
ptr += sizeof(target_ulong);
|
| 750 |
|
| 751 |
/* Registers for embedded use, we just pad them. */
|
| 752 |
for (i = 0; i < 16; i++) |
| 753 |
{
|
| 754 |
*(target_ulong *)ptr = 0;
|
| 755 |
ptr += sizeof(target_ulong);
|
| 756 |
} |
| 757 |
|
| 758 |
/* Processor ID. */
|
| 759 |
*(target_ulong *)ptr = (int32_t)tswap32(env->CP0_PRid); |
| 760 |
ptr += sizeof(target_ulong);
|
| 761 |
|
| 762 |
return ptr - mem_buf;
|
| 763 |
} |
| 764 |
|
| 765 |
/* convert MIPS rounding mode in FCR31 to IEEE library */
|
| 766 |
static unsigned int ieee_rm[] = |
| 767 |
{
|
| 768 |
float_round_nearest_even, |
| 769 |
float_round_to_zero, |
| 770 |
float_round_up, |
| 771 |
float_round_down |
| 772 |
}; |
| 773 |
#define RESTORE_ROUNDING_MODE \
|
| 774 |
set_float_rounding_mode(ieee_rm[env->fpu->fcr31 & 3], &env->fpu->fp_status)
|
| 775 |
|
| 776 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 777 |
{
|
| 778 |
int i;
|
| 779 |
uint8_t *ptr; |
| 780 |
|
| 781 |
ptr = mem_buf; |
| 782 |
for (i = 0; i < 32; i++) |
| 783 |
{
|
| 784 |
env->active_tc.gpr[i] = tswapl(*(target_ulong *)ptr); |
| 785 |
ptr += sizeof(target_ulong);
|
| 786 |
} |
| 787 |
|
| 788 |
env->CP0_Status = tswapl(*(target_ulong *)ptr); |
| 789 |
ptr += sizeof(target_ulong);
|
| 790 |
|
| 791 |
env->active_tc.LO[0] = tswapl(*(target_ulong *)ptr);
|
| 792 |
ptr += sizeof(target_ulong);
|
| 793 |
|
| 794 |
env->active_tc.HI[0] = tswapl(*(target_ulong *)ptr);
|
| 795 |
ptr += sizeof(target_ulong);
|
| 796 |
|
| 797 |
env->CP0_BadVAddr = tswapl(*(target_ulong *)ptr); |
| 798 |
ptr += sizeof(target_ulong);
|
| 799 |
|
| 800 |
env->CP0_Cause = tswapl(*(target_ulong *)ptr); |
| 801 |
ptr += sizeof(target_ulong);
|
| 802 |
|
| 803 |
env->active_tc.PC = tswapl(*(target_ulong *)ptr); |
| 804 |
ptr += sizeof(target_ulong);
|
| 805 |
|
| 806 |
if (env->CP0_Config1 & (1 << CP0C1_FP)) |
| 807 |
{
|
| 808 |
for (i = 0; i < 32; i++) |
| 809 |
{
|
| 810 |
if (env->CP0_Status & (1 << CP0St_FR)) |
| 811 |
env->fpu->fpr[i].d = tswapl(*(target_ulong *)ptr); |
| 812 |
else
|
| 813 |
env->fpu->fpr[i].w[FP_ENDIAN_IDX] = tswapl(*(target_ulong *)ptr); |
| 814 |
ptr += sizeof(target_ulong);
|
| 815 |
} |
| 816 |
|
| 817 |
env->fpu->fcr31 = tswapl(*(target_ulong *)ptr) & 0xFF83FFFF;
|
| 818 |
ptr += sizeof(target_ulong);
|
| 819 |
|
| 820 |
/* The remaining registers are assumed to be read-only. */
|
| 821 |
|
| 822 |
/* set rounding mode */
|
| 823 |
RESTORE_ROUNDING_MODE; |
| 824 |
|
| 825 |
#ifndef CONFIG_SOFTFLOAT
|
| 826 |
/* no floating point exception for native float */
|
| 827 |
SET_FP_ENABLE(env->fcr31, 0);
|
| 828 |
#endif
|
| 829 |
} |
| 830 |
} |
| 831 |
#elif defined (TARGET_SH4)
|
| 832 |
|
| 833 |
/* Hint: Use "set architecture sh4" in GDB to see fpu registers */
|
| 834 |
|
| 835 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 836 |
{
|
| 837 |
uint32_t *ptr = (uint32_t *)mem_buf; |
| 838 |
int i;
|
| 839 |
|
| 840 |
#define SAVE(x) *ptr++=tswapl(x)
|
| 841 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
| 842 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]); |
| 843 |
} else {
|
| 844 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i]); |
| 845 |
} |
| 846 |
for (i = 8; i < 16; i++) SAVE(env->gregs[i]); |
| 847 |
SAVE (env->pc); |
| 848 |
SAVE (env->pr); |
| 849 |
SAVE (env->gbr); |
| 850 |
SAVE (env->vbr); |
| 851 |
SAVE (env->mach); |
| 852 |
SAVE (env->macl); |
| 853 |
SAVE (env->sr); |
| 854 |
SAVE (env->fpul); |
| 855 |
SAVE (env->fpscr); |
| 856 |
for (i = 0; i < 16; i++) |
| 857 |
SAVE(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]); |
| 858 |
SAVE (env->ssr); |
| 859 |
SAVE (env->spc); |
| 860 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i]); |
| 861 |
for (i = 0; i < 8; i++) SAVE(env->gregs[i + 16]); |
| 862 |
return ((uint8_t *)ptr - mem_buf);
|
| 863 |
} |
| 864 |
|
| 865 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 866 |
{
|
| 867 |
uint32_t *ptr = (uint32_t *)mem_buf; |
| 868 |
int i;
|
| 869 |
|
| 870 |
#define LOAD(x) (x)=*ptr++;
|
| 871 |
if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
|
| 872 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]); |
| 873 |
} else {
|
| 874 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i]); |
| 875 |
} |
| 876 |
for (i = 8; i < 16; i++) LOAD(env->gregs[i]); |
| 877 |
LOAD (env->pc); |
| 878 |
LOAD (env->pr); |
| 879 |
LOAD (env->gbr); |
| 880 |
LOAD (env->vbr); |
| 881 |
LOAD (env->mach); |
| 882 |
LOAD (env->macl); |
| 883 |
LOAD (env->sr); |
| 884 |
LOAD (env->fpul); |
| 885 |
LOAD (env->fpscr); |
| 886 |
for (i = 0; i < 16; i++) |
| 887 |
LOAD(env->fregs[i + ((env->fpscr & FPSCR_FR) ? 16 : 0)]); |
| 888 |
LOAD (env->ssr); |
| 889 |
LOAD (env->spc); |
| 890 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i]); |
| 891 |
for (i = 0; i < 8; i++) LOAD(env->gregs[i + 16]); |
| 892 |
} |
| 893 |
#elif defined (TARGET_CRIS)
|
| 894 |
|
| 895 |
static int cris_save_32 (unsigned char *d, uint32_t value) |
| 896 |
{
|
| 897 |
*d++ = (value); |
| 898 |
*d++ = (value >>= 8);
|
| 899 |
*d++ = (value >>= 8);
|
| 900 |
*d++ = (value >>= 8);
|
| 901 |
return 4; |
| 902 |
} |
| 903 |
static int cris_save_16 (unsigned char *d, uint32_t value) |
| 904 |
{
|
| 905 |
*d++ = (value); |
| 906 |
*d++ = (value >>= 8);
|
| 907 |
return 2; |
| 908 |
} |
| 909 |
static int cris_save_8 (unsigned char *d, uint32_t value) |
| 910 |
{
|
| 911 |
*d++ = (value); |
| 912 |
return 1; |
| 913 |
} |
| 914 |
|
| 915 |
/* FIXME: this will bug on archs not supporting unaligned word accesses. */
|
| 916 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 917 |
{
|
| 918 |
uint8_t *ptr = mem_buf; |
| 919 |
uint8_t srs; |
| 920 |
int i;
|
| 921 |
|
| 922 |
for (i = 0; i < 16; i++) |
| 923 |
ptr += cris_save_32 (ptr, env->regs[i]); |
| 924 |
|
| 925 |
srs = env->pregs[PR_SRS]; |
| 926 |
|
| 927 |
ptr += cris_save_8 (ptr, env->pregs[0]);
|
| 928 |
ptr += cris_save_8 (ptr, env->pregs[1]);
|
| 929 |
ptr += cris_save_32 (ptr, env->pregs[2]);
|
| 930 |
ptr += cris_save_8 (ptr, srs); |
| 931 |
ptr += cris_save_16 (ptr, env->pregs[4]);
|
| 932 |
|
| 933 |
for (i = 5; i < 16; i++) |
| 934 |
ptr += cris_save_32 (ptr, env->pregs[i]); |
| 935 |
|
| 936 |
ptr += cris_save_32 (ptr, env->pc); |
| 937 |
|
| 938 |
for (i = 0; i < 16; i++) |
| 939 |
ptr += cris_save_32 (ptr, env->sregs[srs][i]); |
| 940 |
|
| 941 |
return ((uint8_t *)ptr - mem_buf);
|
| 942 |
} |
| 943 |
|
| 944 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 945 |
{
|
| 946 |
uint32_t *ptr = (uint32_t *)mem_buf; |
| 947 |
int i;
|
| 948 |
|
| 949 |
#define LOAD(x) (x)=*ptr++;
|
| 950 |
for (i = 0; i < 16; i++) LOAD(env->regs[i]); |
| 951 |
LOAD (env->pc); |
| 952 |
} |
| 953 |
#else
|
| 954 |
static int cpu_gdb_read_registers(CPUState *env, uint8_t *mem_buf) |
| 955 |
{
|
| 956 |
return 0; |
| 957 |
} |
| 958 |
|
| 959 |
static void cpu_gdb_write_registers(CPUState *env, uint8_t *mem_buf, int size) |
| 960 |
{
|
| 961 |
} |
| 962 |
|
| 963 |
#endif
|
| 964 |
|
| 965 |
static int gdb_handle_packet(GDBState *s, CPUState *env, const char *line_buf) |
| 966 |
{
|
| 967 |
const char *p; |
| 968 |
int ch, reg_size, type;
|
| 969 |
char buf[4096]; |
| 970 |
uint8_t mem_buf[4096];
|
| 971 |
uint32_t *registers; |
| 972 |
target_ulong addr, len; |
| 973 |
|
| 974 |
#ifdef DEBUG_GDB
|
| 975 |
printf("command='%s'\n", line_buf);
|
| 976 |
#endif
|
| 977 |
p = line_buf; |
| 978 |
ch = *p++; |
| 979 |
switch(ch) {
|
| 980 |
case '?': |
| 981 |
/* TODO: Make this return the correct value for user-mode. */
|
| 982 |
snprintf(buf, sizeof(buf), "S%02x", SIGTRAP); |
| 983 |
put_packet(s, buf); |
| 984 |
/* Remove all the breakpoints when this query is issued,
|
| 985 |
* because gdb is doing and initial connect and the state
|
| 986 |
* should be cleaned up.
|
| 987 |
*/
|
| 988 |
cpu_breakpoint_remove_all(env); |
| 989 |
cpu_watchpoint_remove_all(env); |
| 990 |
break;
|
| 991 |
case 'c': |
| 992 |
if (*p != '\0') { |
| 993 |
addr = strtoull(p, (char **)&p, 16); |
| 994 |
#if defined(TARGET_I386)
|
| 995 |
env->eip = addr; |
| 996 |
#elif defined (TARGET_PPC)
|
| 997 |
env->nip = addr; |
| 998 |
#elif defined (TARGET_SPARC)
|
| 999 |
env->pc = addr; |
| 1000 |
env->npc = addr + 4;
|
| 1001 |
#elif defined (TARGET_ARM)
|
| 1002 |
env->regs[15] = addr;
|
| 1003 |
#elif defined (TARGET_SH4)
|
| 1004 |
env->pc = addr; |
| 1005 |
#elif defined (TARGET_MIPS)
|
| 1006 |
env->active_tc.PC = addr; |
| 1007 |
#elif defined (TARGET_CRIS)
|
| 1008 |
env->pc = addr; |
| 1009 |
#endif
|
| 1010 |
} |
| 1011 |
gdb_continue(s); |
| 1012 |
return RS_IDLE;
|
| 1013 |
case 'C': |
| 1014 |
s->signal = strtoul(p, (char **)&p, 16); |
| 1015 |
gdb_continue(s); |
| 1016 |
return RS_IDLE;
|
| 1017 |
case 'k': |
| 1018 |
/* Kill the target */
|
| 1019 |
fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
|
| 1020 |
exit(0);
|
| 1021 |
case 'D': |
| 1022 |
/* Detach packet */
|
| 1023 |
cpu_breakpoint_remove_all(env); |
| 1024 |
cpu_watchpoint_remove_all(env); |
| 1025 |
gdb_continue(s); |
| 1026 |
put_packet(s, "OK");
|
| 1027 |
break;
|
| 1028 |
case 's': |
| 1029 |
if (*p != '\0') { |
| 1030 |
addr = strtoull(p, (char **)&p, 16); |
| 1031 |
#if defined(TARGET_I386)
|
| 1032 |
env->eip = addr; |
| 1033 |
#elif defined (TARGET_PPC)
|
| 1034 |
env->nip = addr; |
| 1035 |
#elif defined (TARGET_SPARC)
|
| 1036 |
env->pc = addr; |
| 1037 |
env->npc = addr + 4;
|
| 1038 |
#elif defined (TARGET_ARM)
|
| 1039 |
env->regs[15] = addr;
|
| 1040 |
#elif defined (TARGET_SH4)
|
| 1041 |
env->pc = addr; |
| 1042 |
#elif defined (TARGET_MIPS)
|
| 1043 |
env->active_tc.PC = addr; |
| 1044 |
#elif defined (TARGET_CRIS)
|
| 1045 |
env->pc = addr; |
| 1046 |
#endif
|
| 1047 |
} |
| 1048 |
cpu_single_step(env, sstep_flags); |
| 1049 |
gdb_continue(s); |
| 1050 |
return RS_IDLE;
|
| 1051 |
case 'F': |
| 1052 |
{
|
| 1053 |
target_ulong ret; |
| 1054 |
target_ulong err; |
| 1055 |
|
| 1056 |
ret = strtoull(p, (char **)&p, 16); |
| 1057 |
if (*p == ',') { |
| 1058 |
p++; |
| 1059 |
err = strtoull(p, (char **)&p, 16); |
| 1060 |
} else {
|
| 1061 |
err = 0;
|
| 1062 |
} |
| 1063 |
if (*p == ',') |
| 1064 |
p++; |
| 1065 |
type = *p; |
| 1066 |
if (gdb_current_syscall_cb)
|
| 1067 |
gdb_current_syscall_cb(s->env, ret, err); |
| 1068 |
if (type == 'C') { |
| 1069 |
put_packet(s, "T02");
|
| 1070 |
} else {
|
| 1071 |
gdb_continue(s); |
| 1072 |
} |
| 1073 |
} |
| 1074 |
break;
|
| 1075 |
case 'g': |
| 1076 |
reg_size = cpu_gdb_read_registers(env, mem_buf); |
| 1077 |
memtohex(buf, mem_buf, reg_size); |
| 1078 |
put_packet(s, buf); |
| 1079 |
break;
|
| 1080 |
case 'G': |
| 1081 |
registers = (void *)mem_buf;
|
| 1082 |
len = strlen(p) / 2;
|
| 1083 |
hextomem((uint8_t *)registers, p, len); |
| 1084 |
cpu_gdb_write_registers(env, mem_buf, len); |
| 1085 |
put_packet(s, "OK");
|
| 1086 |
break;
|
| 1087 |
case 'm': |
| 1088 |
addr = strtoull(p, (char **)&p, 16); |
| 1089 |
if (*p == ',') |
| 1090 |
p++; |
| 1091 |
len = strtoull(p, NULL, 16); |
| 1092 |
if (cpu_memory_rw_debug(env, addr, mem_buf, len, 0) != 0) { |
| 1093 |
put_packet (s, "E14");
|
| 1094 |
} else {
|
| 1095 |
memtohex(buf, mem_buf, len); |
| 1096 |
put_packet(s, buf); |
| 1097 |
} |
| 1098 |
break;
|
| 1099 |
case 'M': |
| 1100 |
addr = strtoull(p, (char **)&p, 16); |
| 1101 |
if (*p == ',') |
| 1102 |
p++; |
| 1103 |
len = strtoull(p, (char **)&p, 16); |
| 1104 |
if (*p == ':') |
| 1105 |
p++; |
| 1106 |
hextomem(mem_buf, p, len); |
| 1107 |
if (cpu_memory_rw_debug(env, addr, mem_buf, len, 1) != 0) |
| 1108 |
put_packet(s, "E14");
|
| 1109 |
else
|
| 1110 |
put_packet(s, "OK");
|
| 1111 |
break;
|
| 1112 |
case 'Z': |
| 1113 |
type = strtoul(p, (char **)&p, 16); |
| 1114 |
if (*p == ',') |
| 1115 |
p++; |
| 1116 |
addr = strtoull(p, (char **)&p, 16); |
| 1117 |
if (*p == ',') |
| 1118 |
p++; |
| 1119 |
len = strtoull(p, (char **)&p, 16); |
| 1120 |
switch (type) {
|
| 1121 |
case 0: |
| 1122 |
case 1: |
| 1123 |
if (cpu_breakpoint_insert(env, addr) < 0) |
| 1124 |
goto breakpoint_error;
|
| 1125 |
put_packet(s, "OK");
|
| 1126 |
break;
|
| 1127 |
#ifndef CONFIG_USER_ONLY
|
| 1128 |
case 2: |
| 1129 |
type = PAGE_WRITE; |
| 1130 |
goto insert_watchpoint;
|
| 1131 |
case 3: |
| 1132 |
type = PAGE_READ; |
| 1133 |
goto insert_watchpoint;
|
| 1134 |
case 4: |
| 1135 |
type = PAGE_READ | PAGE_WRITE; |
| 1136 |
insert_watchpoint:
|
| 1137 |
if (cpu_watchpoint_insert(env, addr, type) < 0) |
| 1138 |
goto breakpoint_error;
|
| 1139 |
put_packet(s, "OK");
|
| 1140 |
break;
|
| 1141 |
#endif
|
| 1142 |
default:
|
| 1143 |
put_packet(s, "");
|
| 1144 |
break;
|
| 1145 |
} |
| 1146 |
break;
|
| 1147 |
breakpoint_error:
|
| 1148 |
put_packet(s, "E22");
|
| 1149 |
break;
|
| 1150 |
|
| 1151 |
case 'z': |
| 1152 |
type = strtoul(p, (char **)&p, 16); |
| 1153 |
if (*p == ',') |
| 1154 |
p++; |
| 1155 |
addr = strtoull(p, (char **)&p, 16); |
| 1156 |
if (*p == ',') |
| 1157 |
p++; |
| 1158 |
len = strtoull(p, (char **)&p, 16); |
| 1159 |
if (type == 0 || type == 1) { |
| 1160 |
cpu_breakpoint_remove(env, addr); |
| 1161 |
put_packet(s, "OK");
|
| 1162 |
#ifndef CONFIG_USER_ONLY
|
| 1163 |
} else if (type >= 2 || type <= 4) { |
| 1164 |
cpu_watchpoint_remove(env, addr); |
| 1165 |
put_packet(s, "OK");
|
| 1166 |
#endif
|
| 1167 |
} else {
|
| 1168 |
put_packet(s, "");
|
| 1169 |
} |
| 1170 |
break;
|
| 1171 |
case 'q': |
| 1172 |
case 'Q': |
| 1173 |
/* parse any 'q' packets here */
|
| 1174 |
if (!strcmp(p,"qemu.sstepbits")) { |
| 1175 |
/* Query Breakpoint bit definitions */
|
| 1176 |
snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x", |
| 1177 |
SSTEP_ENABLE, |
| 1178 |
SSTEP_NOIRQ, |
| 1179 |
SSTEP_NOTIMER); |
| 1180 |
put_packet(s, buf); |
| 1181 |
break;
|
| 1182 |
} else if (strncmp(p,"qemu.sstep",10) == 0) { |
| 1183 |
/* Display or change the sstep_flags */
|
| 1184 |
p += 10;
|
| 1185 |
if (*p != '=') { |
| 1186 |
/* Display current setting */
|
| 1187 |
snprintf(buf, sizeof(buf), "0x%x", sstep_flags); |
| 1188 |
put_packet(s, buf); |
| 1189 |
break;
|
| 1190 |
} |
| 1191 |
p++; |
| 1192 |
type = strtoul(p, (char **)&p, 16); |
| 1193 |
sstep_flags = type; |
| 1194 |
put_packet(s, "OK");
|
| 1195 |
break;
|
| 1196 |
} |
| 1197 |
#ifdef CONFIG_LINUX_USER
|
| 1198 |
else if (strncmp(p, "Offsets", 7) == 0) { |
| 1199 |
TaskState *ts = env->opaque; |
| 1200 |
|
| 1201 |
snprintf(buf, sizeof(buf),
|
| 1202 |
"Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx |
| 1203 |
";Bss=" TARGET_ABI_FMT_lx,
|
| 1204 |
ts->info->code_offset, |
| 1205 |
ts->info->data_offset, |
| 1206 |
ts->info->data_offset); |
| 1207 |
put_packet(s, buf); |
| 1208 |
break;
|
| 1209 |
} |
| 1210 |
#endif
|
| 1211 |
/* Fall through. */
|
| 1212 |
default:
|
| 1213 |
/* put empty packet */
|
| 1214 |
buf[0] = '\0'; |
| 1215 |
put_packet(s, buf); |
| 1216 |
break;
|
| 1217 |
} |
| 1218 |
return RS_IDLE;
|
| 1219 |
} |
| 1220 |
|
| 1221 |
extern void tb_flush(CPUState *env); |
| 1222 |
|
| 1223 |
#ifndef CONFIG_USER_ONLY
|
| 1224 |
static void gdb_vm_stopped(void *opaque, int reason) |
| 1225 |
{
|
| 1226 |
GDBState *s = opaque; |
| 1227 |
char buf[256]; |
| 1228 |
int ret;
|
| 1229 |
|
| 1230 |
if (s->state == RS_SYSCALL)
|
| 1231 |
return;
|
| 1232 |
|
| 1233 |
/* disable single step if it was enable */
|
| 1234 |
cpu_single_step(s->env, 0);
|
| 1235 |
|
| 1236 |
if (reason == EXCP_DEBUG) {
|
| 1237 |
if (s->env->watchpoint_hit) {
|
| 1238 |
snprintf(buf, sizeof(buf), "T%02xwatch:" TARGET_FMT_lx ";", |
| 1239 |
SIGTRAP, |
| 1240 |
s->env->watchpoint[s->env->watchpoint_hit - 1].vaddr);
|
| 1241 |
put_packet(s, buf); |
| 1242 |
s->env->watchpoint_hit = 0;
|
| 1243 |
return;
|
| 1244 |
} |
| 1245 |
tb_flush(s->env); |
| 1246 |
ret = SIGTRAP; |
| 1247 |
} else if (reason == EXCP_INTERRUPT) { |
| 1248 |
ret = SIGINT; |
| 1249 |
} else {
|
| 1250 |
ret = 0;
|
| 1251 |
} |
| 1252 |
snprintf(buf, sizeof(buf), "S%02x", ret); |
| 1253 |
put_packet(s, buf); |
| 1254 |
} |
| 1255 |
#endif
|
| 1256 |
|
| 1257 |
/* Send a gdb syscall request.
|
| 1258 |
This accepts limited printf-style format specifiers, specifically:
|
| 1259 |
%x - target_ulong argument printed in hex.
|
| 1260 |
%lx - 64-bit argument printed in hex.
|
| 1261 |
%s - string pointer (target_ulong) and length (int) pair. */
|
| 1262 |
void gdb_do_syscall(gdb_syscall_complete_cb cb, char *fmt, ...) |
| 1263 |
{
|
| 1264 |
va_list va; |
| 1265 |
char buf[256]; |
| 1266 |
char *p;
|
| 1267 |
target_ulong addr; |
| 1268 |
uint64_t i64; |
| 1269 |
GDBState *s; |
| 1270 |
|
| 1271 |
s = gdb_syscall_state; |
| 1272 |
if (!s)
|
| 1273 |
return;
|
| 1274 |
gdb_current_syscall_cb = cb; |
| 1275 |
s->state = RS_SYSCALL; |
| 1276 |
#ifndef CONFIG_USER_ONLY
|
| 1277 |
vm_stop(EXCP_DEBUG); |
| 1278 |
#endif
|
| 1279 |
s->state = RS_IDLE; |
| 1280 |
va_start(va, fmt); |
| 1281 |
p = buf; |
| 1282 |
*(p++) = 'F';
|
| 1283 |
while (*fmt) {
|
| 1284 |
if (*fmt == '%') { |
| 1285 |
fmt++; |
| 1286 |
switch (*fmt++) {
|
| 1287 |
case 'x': |
| 1288 |
addr = va_arg(va, target_ulong); |
| 1289 |
p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
|
| 1290 |
break;
|
| 1291 |
case 'l': |
| 1292 |
if (*(fmt++) != 'x') |
| 1293 |
goto bad_format;
|
| 1294 |
i64 = va_arg(va, uint64_t); |
| 1295 |
p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64); |
| 1296 |
break;
|
| 1297 |
case 's': |
| 1298 |
addr = va_arg(va, target_ulong); |
| 1299 |
p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x", |
| 1300 |
addr, va_arg(va, int));
|
| 1301 |
break;
|
| 1302 |
default:
|
| 1303 |
bad_format:
|
| 1304 |
fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
|
| 1305 |
fmt - 1);
|
| 1306 |
break;
|
| 1307 |
} |
| 1308 |
} else {
|
| 1309 |
*(p++) = *(fmt++); |
| 1310 |
} |
| 1311 |
} |
| 1312 |
*p = 0;
|
| 1313 |
va_end(va); |
| 1314 |
put_packet(s, buf); |
| 1315 |
#ifdef CONFIG_USER_ONLY
|
| 1316 |
gdb_handlesig(s->env, 0);
|
| 1317 |
#else
|
| 1318 |
cpu_interrupt(s->env, CPU_INTERRUPT_EXIT); |
| 1319 |
#endif
|
| 1320 |
} |
| 1321 |
|
| 1322 |
static void gdb_read_byte(GDBState *s, int ch) |
| 1323 |
{
|
| 1324 |
CPUState *env = s->env; |
| 1325 |
int i, csum;
|
| 1326 |
uint8_t reply; |
| 1327 |
|
| 1328 |
#ifndef CONFIG_USER_ONLY
|
| 1329 |
if (s->last_packet_len) {
|
| 1330 |
/* Waiting for a response to the last packet. If we see the start
|
| 1331 |
of a new command then abandon the previous response. */
|
| 1332 |
if (ch == '-') { |
| 1333 |
#ifdef DEBUG_GDB
|
| 1334 |
printf("Got NACK, retransmitting\n");
|
| 1335 |
#endif
|
| 1336 |
put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len); |
| 1337 |
} |
| 1338 |
#ifdef DEBUG_GDB
|
| 1339 |
else if (ch == '+') |
| 1340 |
printf("Got ACK\n");
|
| 1341 |
else
|
| 1342 |
printf("Got '%c' when expecting ACK/NACK\n", ch);
|
| 1343 |
#endif
|
| 1344 |
if (ch == '+' || ch == '$') |
| 1345 |
s->last_packet_len = 0;
|
| 1346 |
if (ch != '$') |
| 1347 |
return;
|
| 1348 |
} |
| 1349 |
if (vm_running) {
|
| 1350 |
/* when the CPU is running, we cannot do anything except stop
|
| 1351 |
it when receiving a char */
|
| 1352 |
vm_stop(EXCP_INTERRUPT); |
| 1353 |
} else
|
| 1354 |
#endif
|
| 1355 |
{
|
| 1356 |
switch(s->state) {
|
| 1357 |
case RS_IDLE:
|
| 1358 |
if (ch == '$') { |
| 1359 |
s->line_buf_index = 0;
|
| 1360 |
s->state = RS_GETLINE; |
| 1361 |
} |
| 1362 |
break;
|
| 1363 |
case RS_GETLINE:
|
| 1364 |
if (ch == '#') { |
| 1365 |
s->state = RS_CHKSUM1; |
| 1366 |
} else if (s->line_buf_index >= sizeof(s->line_buf) - 1) { |
| 1367 |
s->state = RS_IDLE; |
| 1368 |
} else {
|
| 1369 |
s->line_buf[s->line_buf_index++] = ch; |
| 1370 |
} |
| 1371 |
break;
|
| 1372 |
case RS_CHKSUM1:
|
| 1373 |
s->line_buf[s->line_buf_index] = '\0';
|
| 1374 |
s->line_csum = fromhex(ch) << 4;
|
| 1375 |
s->state = RS_CHKSUM2; |
| 1376 |
break;
|
| 1377 |
case RS_CHKSUM2:
|
| 1378 |
s->line_csum |= fromhex(ch); |
| 1379 |
csum = 0;
|
| 1380 |
for(i = 0; i < s->line_buf_index; i++) { |
| 1381 |
csum += s->line_buf[i]; |
| 1382 |
} |
| 1383 |
if (s->line_csum != (csum & 0xff)) { |
| 1384 |
reply = '-';
|
| 1385 |
put_buffer(s, &reply, 1);
|
| 1386 |
s->state = RS_IDLE; |
| 1387 |
} else {
|
| 1388 |
reply = '+';
|
| 1389 |
put_buffer(s, &reply, 1);
|
| 1390 |
s->state = gdb_handle_packet(s, env, s->line_buf); |
| 1391 |
} |
| 1392 |
break;
|
| 1393 |
default:
|
| 1394 |
abort(); |
| 1395 |
} |
| 1396 |
} |
| 1397 |
} |
| 1398 |
|
| 1399 |
#ifdef CONFIG_USER_ONLY
|
| 1400 |
int
|
| 1401 |
gdb_handlesig (CPUState *env, int sig)
|
| 1402 |
{
|
| 1403 |
GDBState *s; |
| 1404 |
char buf[256]; |
| 1405 |
int n;
|
| 1406 |
|
| 1407 |
s = &gdbserver_state; |
| 1408 |
if (gdbserver_fd < 0 || s->fd < 0) |
| 1409 |
return sig;
|
| 1410 |
|
| 1411 |
/* disable single step if it was enabled */
|
| 1412 |
cpu_single_step(env, 0);
|
| 1413 |
tb_flush(env); |
| 1414 |
|
| 1415 |
if (sig != 0) |
| 1416 |
{
|
| 1417 |
snprintf(buf, sizeof(buf), "S%02x", sig); |
| 1418 |
put_packet(s, buf); |
| 1419 |
} |
| 1420 |
/* put_packet() might have detected that the peer terminated the
|
| 1421 |
connection. */
|
| 1422 |
if (s->fd < 0) |
| 1423 |
return sig;
|
| 1424 |
|
| 1425 |
sig = 0;
|
| 1426 |
s->state = RS_IDLE; |
| 1427 |
s->running_state = 0;
|
| 1428 |
while (s->running_state == 0) { |
| 1429 |
n = read (s->fd, buf, 256);
|
| 1430 |
if (n > 0) |
| 1431 |
{
|
| 1432 |
int i;
|
| 1433 |
|
| 1434 |
for (i = 0; i < n; i++) |
| 1435 |
gdb_read_byte (s, buf[i]); |
| 1436 |
} |
| 1437 |
else if (n == 0 || errno != EAGAIN) |
| 1438 |
{
|
| 1439 |
/* XXX: Connection closed. Should probably wait for annother
|
| 1440 |
connection before continuing. */
|
| 1441 |
return sig;
|
| 1442 |
} |
| 1443 |
} |
| 1444 |
sig = s->signal; |
| 1445 |
s->signal = 0;
|
| 1446 |
return sig;
|
| 1447 |
} |
| 1448 |
|
| 1449 |
/* Tell the remote gdb that the process has exited. */
|
| 1450 |
void gdb_exit(CPUState *env, int code) |
| 1451 |
{
|
| 1452 |
GDBState *s; |
| 1453 |
char buf[4]; |
| 1454 |
|
| 1455 |
s = &gdbserver_state; |
| 1456 |
if (gdbserver_fd < 0 || s->fd < 0) |
| 1457 |
return;
|
| 1458 |
|
| 1459 |
snprintf(buf, sizeof(buf), "W%02x", code); |
| 1460 |
put_packet(s, buf); |
| 1461 |
} |
| 1462 |
|
| 1463 |
|
| 1464 |
static void gdb_accept(void *opaque) |
| 1465 |
{
|
| 1466 |
GDBState *s; |
| 1467 |
struct sockaddr_in sockaddr;
|
| 1468 |
socklen_t len; |
| 1469 |
int val, fd;
|
| 1470 |
|
| 1471 |
for(;;) {
|
| 1472 |
len = sizeof(sockaddr);
|
| 1473 |
fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
|
| 1474 |
if (fd < 0 && errno != EINTR) { |
| 1475 |
perror("accept");
|
| 1476 |
return;
|
| 1477 |
} else if (fd >= 0) { |
| 1478 |
break;
|
| 1479 |
} |
| 1480 |
} |
| 1481 |
|
| 1482 |
/* set short latency */
|
| 1483 |
val = 1;
|
| 1484 |
setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val)); |
| 1485 |
|
| 1486 |
s = &gdbserver_state; |
| 1487 |
memset (s, 0, sizeof (GDBState)); |
| 1488 |
s->env = first_cpu; /* XXX: allow to change CPU */
|
| 1489 |
s->fd = fd; |
| 1490 |
|
| 1491 |
gdb_syscall_state = s; |
| 1492 |
|
| 1493 |
fcntl(fd, F_SETFL, O_NONBLOCK); |
| 1494 |
} |
| 1495 |
|
| 1496 |
static int gdbserver_open(int port) |
| 1497 |
{
|
| 1498 |
struct sockaddr_in sockaddr;
|
| 1499 |
int fd, val, ret;
|
| 1500 |
|
| 1501 |
fd = socket(PF_INET, SOCK_STREAM, 0);
|
| 1502 |
if (fd < 0) { |
| 1503 |
perror("socket");
|
| 1504 |
return -1; |
| 1505 |
} |
| 1506 |
|
| 1507 |
/* allow fast reuse */
|
| 1508 |
val = 1;
|
| 1509 |
setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val)); |
| 1510 |
|
| 1511 |
sockaddr.sin_family = AF_INET; |
| 1512 |
sockaddr.sin_port = htons(port); |
| 1513 |
sockaddr.sin_addr.s_addr = 0;
|
| 1514 |
ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr)); |
| 1515 |
if (ret < 0) { |
| 1516 |
perror("bind");
|
| 1517 |
return -1; |
| 1518 |
} |
| 1519 |
ret = listen(fd, 0);
|
| 1520 |
if (ret < 0) { |
| 1521 |
perror("listen");
|
| 1522 |
return -1; |
| 1523 |
} |
| 1524 |
return fd;
|
| 1525 |
} |
| 1526 |
|
| 1527 |
int gdbserver_start(int port) |
| 1528 |
{
|
| 1529 |
gdbserver_fd = gdbserver_open(port); |
| 1530 |
if (gdbserver_fd < 0) |
| 1531 |
return -1; |
| 1532 |
/* accept connections */
|
| 1533 |
gdb_accept (NULL);
|
| 1534 |
return 0; |
| 1535 |
} |
| 1536 |
#else
|
| 1537 |
static int gdb_chr_can_receive(void *opaque) |
| 1538 |
{
|
| 1539 |
return 1; |
| 1540 |
} |
| 1541 |
|
| 1542 |
static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size) |
| 1543 |
{
|
| 1544 |
GDBState *s = opaque; |
| 1545 |
int i;
|
| 1546 |
|
| 1547 |
for (i = 0; i < size; i++) { |
| 1548 |
gdb_read_byte(s, buf[i]); |
| 1549 |
} |
| 1550 |
} |
| 1551 |
|
| 1552 |
static void gdb_chr_event(void *opaque, int event) |
| 1553 |
{
|
| 1554 |
switch (event) {
|
| 1555 |
case CHR_EVENT_RESET:
|
| 1556 |
vm_stop(EXCP_INTERRUPT); |
| 1557 |
gdb_syscall_state = opaque; |
| 1558 |
break;
|
| 1559 |
default:
|
| 1560 |
break;
|
| 1561 |
} |
| 1562 |
} |
| 1563 |
|
| 1564 |
int gdbserver_start(const char *port) |
| 1565 |
{
|
| 1566 |
GDBState *s; |
| 1567 |
char gdbstub_port_name[128]; |
| 1568 |
int port_num;
|
| 1569 |
char *p;
|
| 1570 |
CharDriverState *chr; |
| 1571 |
|
| 1572 |
if (!port || !*port)
|
| 1573 |
return -1; |
| 1574 |
|
| 1575 |
port_num = strtol(port, &p, 10);
|
| 1576 |
if (*p == 0) { |
| 1577 |
/* A numeric value is interpreted as a port number. */
|
| 1578 |
snprintf(gdbstub_port_name, sizeof(gdbstub_port_name),
|
| 1579 |
"tcp::%d,nowait,nodelay,server", port_num);
|
| 1580 |
port = gdbstub_port_name; |
| 1581 |
} |
| 1582 |
|
| 1583 |
chr = qemu_chr_open(port); |
| 1584 |
if (!chr)
|
| 1585 |
return -1; |
| 1586 |
|
| 1587 |
s = qemu_mallocz(sizeof(GDBState));
|
| 1588 |
if (!s) {
|
| 1589 |
return -1; |
| 1590 |
} |
| 1591 |
s->env = first_cpu; /* XXX: allow to change CPU */
|
| 1592 |
s->chr = chr; |
| 1593 |
qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive, |
| 1594 |
gdb_chr_event, s); |
| 1595 |
qemu_add_vm_stop_handler(gdb_vm_stopped, s); |
| 1596 |
return 0; |
| 1597 |
} |
| 1598 |
#endif
|