Revision 363be49c
| b/target-ppc/cpu.h | ||
|---|---|---|
| 514 | 514 |
/* Default PowerPC will be 604/970 */ |
| 515 | 515 |
#define PPC_INSNS_PPC32 PPC_INSNS_604 |
| 516 | 516 |
#define PPC_FLAGS_PPC32 PPC_FLAGS_604 |
| 517 |
#if 1 |
|
| 518 | 517 |
#define PPC_INSNS_PPC64 PPC_INSNS_970 |
| 519 | 518 |
#define PPC_FLAGS_PPC64 PPC_FLAGS_970 |
| 520 |
#endif |
|
| 521 | 519 |
#define PPC_INSNS_DEFAULT PPC_INSNS_604 |
| 522 | 520 |
#define PPC_FLAGS_DEFAULT PPC_FLAGS_604 |
| 523 | 521 |
typedef struct ppc_def_t ppc_def_t; |
| ... | ... | |
| 562 | 560 |
#define MSR_SF 63 /* Sixty-four-bit mode hflags */ |
| 563 | 561 |
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ |
| 564 | 562 |
#define MSR_HV 60 /* hypervisor state hflags */ |
| 565 |
#define MSR_UCLE 26 /* User-mode cache lock enable on e500 */ |
|
| 563 |
#define MSR_CM 31 /* Computation mode for BookE hflags */ |
|
| 564 |
#define MSR_ICM 30 /* Interrupt computation mode for BookE */ |
|
| 565 |
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ |
|
| 566 | 566 |
#define MSR_VR 25 /* altivec available hflags */ |
| 567 |
#define MSR_SPE 25 /* SPE enable on e500 hflags */
|
|
| 567 |
#define MSR_SPE 25 /* SPE enable for BookE hflags */
|
|
| 568 | 568 |
#define MSR_AP 23 /* Access privilege state on 602 hflags */ |
| 569 | 569 |
#define MSR_SA 22 /* Supervisor access mode on 602 hflags */ |
| 570 | 570 |
#define MSR_KEY 19 /* key bit on 603e */ |
| ... | ... | |
| 600 | 600 |
#define msr_sf env->msr[MSR_SF] |
| 601 | 601 |
#define msr_isf env->msr[MSR_ISF] |
| 602 | 602 |
#define msr_hv env->msr[MSR_HV] |
| 603 |
#define msr_cm env->msr[MSR_CM] |
|
| 604 |
#define msr_icm env->msr[MSR_ICM] |
|
| 603 | 605 |
#define msr_ucle env->msr[MSR_UCLE] |
| 604 | 606 |
#define msr_vr env->msr[MSR_VR] |
| 605 | 607 |
#define msr_spe env->msr[MSR_SPE] |
| ... | ... | |
| 724 | 726 |
int nb_ways; /* Number of ways in the TLB set */ |
| 725 | 727 |
int last_way; /* Last used way used to allocate TLB in a LRU way */ |
| 726 | 728 |
int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */ |
| 729 |
int nb_pids; /* Number of available PID registers */ |
|
| 727 | 730 |
ppc_tlb_t *tlb; /* TLB is optional. Allocate them only if needed */ |
| 728 | 731 |
/* Callbacks for specific checks on some implementations */ |
| 729 | 732 |
int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot, |
| ... | ... | |
| 874 | 877 |
#define SPR_SRR1 (0x01B) |
| 875 | 878 |
#define SPR_BOOKE_PID (0x030) |
| 876 | 879 |
#define SPR_BOOKE_DECAR (0x036) |
| 877 |
#define SPR_CSRR0 (0x03A)
|
|
| 878 |
#define SPR_CSRR1 (0x03B)
|
|
| 880 |
#define SPR_BOOKE_CSRR0 (0x03A)
|
|
| 881 |
#define SPR_BOOKE_CSRR1 (0x03B)
|
|
| 879 | 882 |
#define SPR_BOOKE_DEAR (0x03D) |
| 880 | 883 |
#define SPR_BOOKE_ESR (0x03E) |
| 881 |
#define SPR_BOOKE_EVPR (0x03F)
|
|
| 884 |
#define SPR_BOOKE_IVPR (0x03F)
|
|
| 882 | 885 |
#define SPR_8xx_EIE (0x050) |
| 883 | 886 |
#define SPR_8xx_EID (0x051) |
| 884 | 887 |
#define SPR_8xx_NRE (0x052) |
| ... | ... | |
| 900 | 903 |
#define SPR_58x_BAR (0x09F) |
| 901 | 904 |
#define SPR_VRSAVE (0x100) |
| 902 | 905 |
#define SPR_USPRG0 (0x100) |
| 906 |
#define SPR_USPRG1 (0x101) |
|
| 907 |
#define SPR_USPRG2 (0x102) |
|
| 908 |
#define SPR_USPRG3 (0x103) |
|
| 903 | 909 |
#define SPR_USPRG4 (0x104) |
| 904 | 910 |
#define SPR_USPRG5 (0x105) |
| 905 | 911 |
#define SPR_USPRG6 (0x106) |
| ... | ... | |
| 973 | 979 |
#define SPR_BOOKE_ATBL (0x20E) |
| 974 | 980 |
#define SPR_BOOKE_ATBU (0x20F) |
| 975 | 981 |
#define SPR_IBAT0U (0x210) |
| 976 |
#define SPR_E500_IVOR32 (0x210)
|
|
| 982 |
#define SPR_BOOKE_IVOR32 (0x210)
|
|
| 977 | 983 |
#define SPR_IBAT0L (0x211) |
| 978 |
#define SPR_E500_IVOR33 (0x211)
|
|
| 984 |
#define SPR_BOOKE_IVOR33 (0x211)
|
|
| 979 | 985 |
#define SPR_IBAT1U (0x212) |
| 980 |
#define SPR_E500_IVOR34 (0x212)
|
|
| 986 |
#define SPR_BOOKE_IVOR34 (0x212)
|
|
| 981 | 987 |
#define SPR_IBAT1L (0x213) |
| 982 |
#define SPR_E500_IVOR35 (0x213)
|
|
| 988 |
#define SPR_BOOKE_IVOR35 (0x213)
|
|
| 983 | 989 |
#define SPR_IBAT2U (0x214) |
| 990 |
#define SPR_BOOKE_IVOR36 (0x214) |
|
| 984 | 991 |
#define SPR_IBAT2L (0x215) |
| 985 | 992 |
#define SPR_E500_L1CFG0 (0x215) |
| 993 |
#define SPR_BOOKE_IVOR37 (0x215) |
|
| 986 | 994 |
#define SPR_IBAT3U (0x216) |
| 987 | 995 |
#define SPR_E500_L1CFG1 (0x216) |
| 988 | 996 |
#define SPR_IBAT3L (0x217) |
| ... | ... | |
| 1005 | 1013 |
#define SPR_DBAT4U (0x238) |
| 1006 | 1014 |
#define SPR_DBAT4L (0x239) |
| 1007 | 1015 |
#define SPR_DBAT5U (0x23A) |
| 1008 |
#define SPR_E500_MCSRR0 (0x23A)
|
|
| 1016 |
#define SPR_BOOKE_MCSRR0 (0x23A)
|
|
| 1009 | 1017 |
#define SPR_DBAT5L (0x23B) |
| 1010 |
#define SPR_E500_MCSRR1 (0x23B)
|
|
| 1018 |
#define SPR_BOOKE_MCSRR1 (0x23B)
|
|
| 1011 | 1019 |
#define SPR_DBAT6U (0x23C) |
| 1012 |
#define SPR_E500_MCSR (0x23C)
|
|
| 1020 |
#define SPR_BOOKE_MCSR (0x23C)
|
|
| 1013 | 1021 |
#define SPR_DBAT6L (0x23D) |
| 1014 | 1022 |
#define SPR_E500_MCAR (0x23D) |
| 1015 | 1023 |
#define SPR_DBAT7U (0x23E) |
| 1024 |
#define SPR_BOOKE_DSRR0 (0x23E) |
|
| 1016 | 1025 |
#define SPR_DBAT7L (0x23F) |
| 1017 |
#define SPR_E500_MAS0 (0x270) |
|
| 1018 |
#define SPR_E500_MAS1 (0x271) |
|
| 1019 |
#define SPR_E500_MAS2 (0x272) |
|
| 1020 |
#define SPR_E500_MAS3 (0x273) |
|
| 1021 |
#define SPR_E500_MAS4 (0x274) |
|
| 1022 |
#define SPR_E500_MAS6 (0x276) |
|
| 1023 |
#define SPR_E500_PID1 (0x279) |
|
| 1024 |
#define SPR_E500_PID2 (0x27A) |
|
| 1025 |
#define SPR_E500_TLB0CFG (0x2B0) |
|
| 1026 |
#define SPR_E500_TLB1CFG (0x2B1) |
|
| 1026 |
#define SPR_BOOKE_DSRR1 (0x23F) |
|
| 1027 |
#define SPR_BOOKE_SPRG8 (0x25C) |
|
| 1028 |
#define SPR_BOOKE_SPRG9 (0x25D) |
|
| 1029 |
#define SPR_BOOKE_MAS0 (0x270) |
|
| 1030 |
#define SPR_BOOKE_MAS1 (0x271) |
|
| 1031 |
#define SPR_BOOKE_MAS2 (0x272) |
|
| 1032 |
#define SPR_BOOKE_MAS3 (0x273) |
|
| 1033 |
#define SPR_BOOKE_MAS4 (0x274) |
|
| 1034 |
#define SPR_BOOKE_MAS6 (0x276) |
|
| 1035 |
#define SPR_BOOKE_PID1 (0x279) |
|
| 1036 |
#define SPR_BOOKE_PID2 (0x27A) |
|
| 1037 |
#define SPR_BOOKE_TLB0CFG (0x2B0) |
|
| 1038 |
#define SPR_BOOKE_TLB1CFG (0x2B1) |
|
| 1039 |
#define SPR_BOOKE_TLB2CFG (0x2B2) |
|
| 1040 |
#define SPR_BOOKE_TLB3CFG (0x2B3) |
|
| 1041 |
#define SPR_BOOKE_EPR (0x2BE) |
|
| 1027 | 1042 |
#define SPR_440_INV0 (0x370) |
| 1028 | 1043 |
#define SPR_440_INV1 (0x371) |
| 1029 | 1044 |
#define SPR_440_INV2 (0x372) |
| ... | ... | |
| 1043 | 1058 |
#define SPR_440_DVLIM (0x398) |
| 1044 | 1059 |
#define SPR_440_IVLIM (0x399) |
| 1045 | 1060 |
#define SPR_440_RSTCFG (0x39B) |
| 1046 |
#define SPR_440_DCBTRL (0x39C)
|
|
| 1047 |
#define SPR_440_DCBTRH (0x39D)
|
|
| 1048 |
#define SPR_440_ICBTRL (0x39E)
|
|
| 1049 |
#define SPR_440_ICBTRH (0x39F)
|
|
| 1061 |
#define SPR_BOOKE_DCBTRL (0x39C)
|
|
| 1062 |
#define SPR_BOOKE_DCBTRH (0x39D)
|
|
| 1063 |
#define SPR_BOOKE_ICBTRL (0x39E)
|
|
| 1064 |
#define SPR_BOOKE_ICBTRH (0x39F)
|
|
| 1050 | 1065 |
#define SPR_UMMCR0 (0x3A8) |
| 1051 | 1066 |
#define SPR_UPMC1 (0x3A9) |
| 1052 | 1067 |
#define SPR_UPMC2 (0x3AA) |
| ... | ... | |
| 1056 | 1071 |
#define SPR_UPMC4 (0x3AE) |
| 1057 | 1072 |
#define SPR_USDA (0x3AF) |
| 1058 | 1073 |
#define SPR_40x_ZPR (0x3B0) |
| 1059 |
#define SPR_E500_MAS7 (0x3B0)
|
|
| 1074 |
#define SPR_BOOKE_MAS7 (0x3B0)
|
|
| 1060 | 1075 |
#define SPR_40x_PID (0x3B1) |
| 1061 | 1076 |
#define SPR_440_MMUCR (0x3B2) |
| 1062 | 1077 |
#define SPR_4xx_CCR0 (0x3B3) |
| 1078 |
#define SPR_BOOKE_EPLC (0x3B3) |
|
| 1063 | 1079 |
#define SPR_405_IAC3 (0x3B4) |
| 1080 |
#define SPR_BOOKE_EPSC (0x3B4) |
|
| 1064 | 1081 |
#define SPR_405_IAC4 (0x3B5) |
| 1065 | 1082 |
#define SPR_405_DVC1 (0x3B6) |
| 1066 | 1083 |
#define SPR_405_DVC2 (0x3B7) |
| ... | ... | |
| 1083 | 1100 |
#define SPR_DCMP (0x3D1) |
| 1084 | 1101 |
#define SPR_HASH1 (0x3D2) |
| 1085 | 1102 |
#define SPR_HASH2 (0x3D3) |
| 1086 |
#define SPR_4xx_ICDBDR (0x3D3)
|
|
| 1103 |
#define SPR_BOOKE_ICBDR (0x3D3)
|
|
| 1087 | 1104 |
#define SPR_IMISS (0x3D4) |
| 1088 | 1105 |
#define SPR_40x_ESR (0x3D4) |
| 1089 | 1106 |
#define SPR_ICMP (0x3D5) |
| ... | ... | |
| 1114 | 1131 |
#define SPR_E500_L1CSR1 (0x3F3) |
| 1115 | 1132 |
#define SPR_440_DBDR (0x3F3) |
| 1116 | 1133 |
#define SPR_40x_IAC1 (0x3F4) |
| 1117 |
#define SPR_E500_MMUCSR0 (0x3F4)
|
|
| 1134 |
#define SPR_BOOKE_MMUCSR0 (0x3F4)
|
|
| 1118 | 1135 |
#define SPR_DABR (0x3F5) |
| 1119 | 1136 |
#define DABR_MASK (~(target_ulong)0x7) |
| 1120 | 1137 |
#define SPR_E500_BUCSR (0x3F5) |
| ... | ... | |
| 1122 | 1139 |
#define SPR_601_HID5 (0x3F5) |
| 1123 | 1140 |
#define SPR_40x_DAC1 (0x3F6) |
| 1124 | 1141 |
#define SPR_40x_DAC2 (0x3F7) |
| 1125 |
#define SPR_E500_MMUCFG (0x3F7)
|
|
| 1142 |
#define SPR_BOOKE_MMUCFG (0x3F7)
|
|
| 1126 | 1143 |
#define SPR_L2PM (0x3F8) |
| 1127 | 1144 |
#define SPR_750_HID2 (0x3F8) |
| 1128 | 1145 |
#define SPR_L2CR (0x3F9) |
| b/target-ppc/translate_init.c | ||
|---|---|---|
| 893 | 893 |
&spr_read_generic, SPR_NOACCESS, |
| 894 | 894 |
0x00000000); |
| 895 | 895 |
/* Exception processing */ |
| 896 |
spr_register(env, SPR_CSRR0, "CSRR0", |
|
| 896 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
|
| 897 | 897 |
SPR_NOACCESS, SPR_NOACCESS, |
| 898 | 898 |
&spr_read_generic, &spr_write_generic, |
| 899 | 899 |
0x00000000); |
| 900 |
spr_register(env, SPR_CSRR1, "CSRR1", |
|
| 900 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
|
|
| 901 | 901 |
SPR_NOACCESS, SPR_NOACCESS, |
| 902 | 902 |
&spr_read_generic, &spr_write_generic, |
| 903 | 903 |
0x00000000); |
| ... | ... | |
| 1060 | 1060 |
&spr_read_generic, &spr_write_pir, |
| 1061 | 1061 |
0x00000000); |
| 1062 | 1062 |
/* Interrupt processing */ |
| 1063 |
spr_register(env, SPR_CSRR0, "CSRR0", |
|
| 1063 |
spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
|
|
| 1064 | 1064 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1065 | 1065 |
&spr_read_generic, &spr_write_generic, |
| 1066 | 1066 |
0x00000000); |
| 1067 |
spr_register(env, SPR_CSRR1, "CSRR1", |
|
| 1067 |
spr_register(env, SPR_BOOKE_CSRR1, "CSRR1", |
|
| 1068 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1069 |
&spr_read_generic, &spr_write_generic, |
|
| 1070 |
0x00000000); |
|
| 1071 |
spr_register(env, SPR_BOOKE_DSRR0, "DSRR0", |
|
| 1072 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1073 |
&spr_read_generic, &spr_write_generic, |
|
| 1074 |
0x00000000); |
|
| 1075 |
spr_register(env, SPR_BOOKE_DSRR1, "DSRR1", |
|
| 1076 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1077 |
&spr_read_generic, &spr_write_generic, |
|
| 1078 |
0x00000000); |
|
| 1079 |
spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0", |
|
| 1080 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1081 |
&spr_read_generic, &spr_write_generic, |
|
| 1082 |
0x00000000); |
|
| 1083 |
spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1", |
|
| 1068 | 1084 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1069 | 1085 |
&spr_read_generic, &spr_write_generic, |
| 1070 | 1086 |
0x00000000); |
| ... | ... | |
| 1137 | 1153 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1138 | 1154 |
&spr_read_generic, &spr_write_generic, |
| 1139 | 1155 |
0x00000000); |
| 1140 |
spr_register(env, SPR_BOOKE_EVPR, "EVPR", |
|
| 1156 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR", |
|
| 1157 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1158 |
&spr_read_generic, &spr_write_generic, |
|
| 1159 |
0x00000000); |
|
| 1160 |
/* Exception vectors */ |
|
| 1161 |
spr_register(env, SPR_BOOKE_IVPR, "IVPR", |
|
| 1141 | 1162 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1142 | 1163 |
&spr_read_generic, &spr_write_generic, |
| 1143 | 1164 |
0x00000000); |
| ... | ... | |
| 1205 | 1226 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1206 | 1227 |
&spr_read_generic, &spr_write_generic, |
| 1207 | 1228 |
0x00000000); |
| 1229 |
spr_register(env, SPR_BOOKE_IVOR32, "IVOR32", |
|
| 1230 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1231 |
&spr_read_generic, &spr_write_generic, |
|
| 1232 |
0x00000000); |
|
| 1233 |
spr_register(env, SPR_BOOKE_IVOR33, "IVOR33", |
|
| 1234 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1235 |
&spr_read_generic, &spr_write_generic, |
|
| 1236 |
0x00000000); |
|
| 1237 |
spr_register(env, SPR_BOOKE_IVOR34, "IVOR34", |
|
| 1238 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1239 |
&spr_read_generic, &spr_write_generic, |
|
| 1240 |
0x00000000); |
|
| 1241 |
spr_register(env, SPR_BOOKE_IVOR35, "IVOR35", |
|
| 1242 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1243 |
&spr_read_generic, &spr_write_generic, |
|
| 1244 |
0x00000000); |
|
| 1245 |
spr_register(env, SPR_BOOKE_IVOR36, "IVOR36", |
|
| 1246 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1247 |
&spr_read_generic, &spr_write_generic, |
|
| 1248 |
0x00000000); |
|
| 1249 |
spr_register(env, SPR_BOOKE_IVOR37, "IVOR37", |
|
| 1250 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1251 |
&spr_read_generic, &spr_write_generic, |
|
| 1252 |
0x00000000); |
|
| 1208 | 1253 |
spr_register(env, SPR_BOOKE_PID, "PID", |
| 1209 | 1254 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1210 | 1255 |
&spr_read_generic, &spr_write_generic, |
| ... | ... | |
| 1265 | 1310 |
0x00000000); |
| 1266 | 1311 |
} |
| 1267 | 1312 |
|
| 1313 |
/* FSL storage control registers */ |
|
| 1314 |
static void gen_spr_BookE_FSL (CPUPPCState *env) |
|
| 1315 |
{
|
|
| 1316 |
/* TLB assist registers */ |
|
| 1317 |
spr_register(env, SPR_BOOKE_MAS0, "MAS0", |
|
| 1318 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1319 |
&spr_read_generic, &spr_write_generic, |
|
| 1320 |
0x00000000); |
|
| 1321 |
spr_register(env, SPR_BOOKE_MAS1, "MAS2", |
|
| 1322 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1323 |
&spr_read_generic, &spr_write_generic, |
|
| 1324 |
0x00000000); |
|
| 1325 |
spr_register(env, SPR_BOOKE_MAS2, "MAS3", |
|
| 1326 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1327 |
&spr_read_generic, &spr_write_generic, |
|
| 1328 |
0x00000000); |
|
| 1329 |
spr_register(env, SPR_BOOKE_MAS3, "MAS4", |
|
| 1330 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1331 |
&spr_read_generic, &spr_write_generic, |
|
| 1332 |
0x00000000); |
|
| 1333 |
spr_register(env, SPR_BOOKE_MAS4, "MAS5", |
|
| 1334 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1335 |
&spr_read_generic, &spr_write_generic, |
|
| 1336 |
0x00000000); |
|
| 1337 |
spr_register(env, SPR_BOOKE_MAS6, "MAS6", |
|
| 1338 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1339 |
&spr_read_generic, &spr_write_generic, |
|
| 1340 |
0x00000000); |
|
| 1341 |
spr_register(env, SPR_BOOKE_MAS7, "MAS7", |
|
| 1342 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1343 |
&spr_read_generic, &spr_write_generic, |
|
| 1344 |
0x00000000); |
|
| 1345 |
if (env->nb_pids > 1) {
|
|
| 1346 |
spr_register(env, SPR_BOOKE_PID1, "PID1", |
|
| 1347 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1348 |
&spr_read_generic, &spr_write_generic, |
|
| 1349 |
0x00000000); |
|
| 1350 |
} |
|
| 1351 |
if (env->nb_pids > 2) {
|
|
| 1352 |
spr_register(env, SPR_BOOKE_PID2, "PID2", |
|
| 1353 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1354 |
&spr_read_generic, &spr_write_generic, |
|
| 1355 |
0x00000000); |
|
| 1356 |
} |
|
| 1357 |
spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG", |
|
| 1358 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1359 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1360 |
0x00000000); /* TOFIX */ |
|
| 1361 |
spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0", |
|
| 1362 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1363 |
&spr_read_generic, &spr_write_generic, |
|
| 1364 |
0x00000000); /* TOFIX */ |
|
| 1365 |
switch (env->nb_ways) {
|
|
| 1366 |
case 4: |
|
| 1367 |
spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG", |
|
| 1368 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1369 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1370 |
0x00000000); /* TOFIX */ |
|
| 1371 |
/* Fallthru */ |
|
| 1372 |
case 3: |
|
| 1373 |
spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG", |
|
| 1374 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1375 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1376 |
0x00000000); /* TOFIX */ |
|
| 1377 |
/* Fallthru */ |
|
| 1378 |
case 2: |
|
| 1379 |
spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG", |
|
| 1380 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1381 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1382 |
0x00000000); /* TOFIX */ |
|
| 1383 |
/* Fallthru */ |
|
| 1384 |
case 1: |
|
| 1385 |
spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG", |
|
| 1386 |
SPR_NOACCESS, SPR_NOACCESS, |
|
| 1387 |
&spr_read_generic, SPR_NOACCESS, |
|
| 1388 |
0x00000000); /* TOFIX */ |
|
| 1389 |
/* Fallthru */ |
|
| 1390 |
case 0: |
|
| 1391 |
default: |
|
| 1392 |
break; |
|
| 1393 |
} |
|
| 1394 |
} |
|
| 1395 |
|
|
| 1268 | 1396 |
/* SPR specific to PowerPC 440 implementation */ |
| 1269 | 1397 |
static void gen_spr_440 (CPUPPCState *env) |
| 1270 | 1398 |
{
|
| ... | ... | |
| 1361 | 1489 |
0x00000000); |
| 1362 | 1490 |
/* Cache debug */ |
| 1363 | 1491 |
/* XXX : not implemented */ |
| 1364 |
spr_register(env, SPR_440_DCBTRH, "DCBTRH",
|
|
| 1492 |
spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
|
|
| 1365 | 1493 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1366 | 1494 |
&spr_read_generic, SPR_NOACCESS, |
| 1367 | 1495 |
0x00000000); |
| 1368 | 1496 |
/* XXX : not implemented */ |
| 1369 |
spr_register(env, SPR_440_DCBTRL, "DCBTRL",
|
|
| 1497 |
spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
|
|
| 1370 | 1498 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1371 | 1499 |
&spr_read_generic, SPR_NOACCESS, |
| 1372 | 1500 |
0x00000000); |
| 1373 | 1501 |
/* XXX : not implemented */ |
| 1374 |
spr_register(env, SPR_4xx_ICDBDR, "ICDBDR",
|
|
| 1502 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
|
| 1375 | 1503 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1376 | 1504 |
&spr_read_generic, SPR_NOACCESS, |
| 1377 | 1505 |
0x00000000); |
| 1378 | 1506 |
/* XXX : not implemented */ |
| 1379 |
spr_register(env, SPR_440_ICBTRH, "ICBTRH",
|
|
| 1507 |
spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
|
|
| 1380 | 1508 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1381 | 1509 |
&spr_read_generic, SPR_NOACCESS, |
| 1382 | 1510 |
0x00000000); |
| 1383 | 1511 |
/* XXX : not implemented */ |
| 1384 |
spr_register(env, SPR_440_ICBTRL, "ICBTRL",
|
|
| 1512 |
spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
|
|
| 1385 | 1513 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1386 | 1514 |
&spr_read_generic, SPR_NOACCESS, |
| 1387 | 1515 |
0x00000000); |
| ... | ... | |
| 1426 | 1554 |
&spr_read_generic, &spr_write_generic, |
| 1427 | 1555 |
0x00000000); |
| 1428 | 1556 |
/* XXX : not implemented */ |
| 1429 |
spr_register(env, SPR_4xx_ICDBDR, "ICDBDR",
|
|
| 1557 |
spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
|
|
| 1430 | 1558 |
SPR_NOACCESS, SPR_NOACCESS, |
| 1431 | 1559 |
&spr_read_generic, SPR_NOACCESS, |
| 1432 | 1560 |
0x00000000); |
| ... | ... | |
| 1861 | 1989 |
/* Time base */ |
| 1862 | 1990 |
gen_tbl(env); |
| 1863 | 1991 |
gen_spr_BookE(env); |
| 1992 |
gen_spr_BookE_FSL(env); |
|
| 1864 | 1993 |
env->nb_BATs = 0; |
| 1865 | 1994 |
env->nb_tlb = 64; |
| 1866 | 1995 |
env->nb_ways = 1; |
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