Archipelago » qemu

/* Default PowerPC will be 604/970 */

#define PPC_INSNS_PPC32 PPC_INSNS_604

#define PPC_FLAGS_PPC32 PPC_FLAGS_604

#define PPC_INSNS_PPC64 PPC_INSNS_970

#define PPC_FLAGS_PPC64 PPC_FLAGS_970

#define PPC_INSNS_DEFAULT PPC_INSNS_604

#define PPC_FLAGS_DEFAULT PPC_FLAGS_604

typedef struct ppc_def_t ppc_def_t;

#define MSR_SF   63 /* Sixty-four-bit mode                            hflags */

#define MSR_ISF  61 /* Sixty-four-bit interrupt mode on 630                  */

#define MSR_HV   60 /* hypervisor state                               hflags */

#define MSR_VR   25 /* altivec available                              hflags */

#define MSR_AP   23 /* Access privilege state on 602                  hflags */

#define MSR_SA   22 /* Supervisor access mode on 602                  hflags */

#define MSR_KEY  19 /* key bit on 603e                                       */

#define msr_sf   env->msr[MSR_SF]

#define msr_isf  env->msr[MSR_ISF]

#define msr_hv   env->msr[MSR_HV]

#define msr_ucle env->msr[MSR_UCLE]

#define msr_vr   env->msr[MSR_VR]

#define msr_spe  env->msr[MSR_SPE]

    int nb_ways;     /* Number of ways in the TLB set                        */

    int last_way;    /* Last used way used to allocate TLB in a LRU way      */

    int id_tlbs;     /* If 1, MMU has separated TLBs for instructions & data */

    ppc_tlb_t *tlb;  /* TLB is optional. Allocate them only if needed        */

    /* Callbacks for specific checks on some implementations */

    int (*tlb_check_more)(CPUPPCState *env, struct ppc_tlb_t *tlb, int *prot,

#define SPR_SRR1         (0x01B)

#define SPR_BOOKE_PID    (0x030)

#define SPR_BOOKE_DECAR  (0x036)

#define SPR_BOOKE_DEAR   (0x03D)

#define SPR_BOOKE_ESR    (0x03E)

#define SPR_8xx_EIE      (0x050)

#define SPR_8xx_EID      (0x051)

#define SPR_8xx_NRE      (0x052)

#define SPR_58x_BAR      (0x09F)

#define SPR_VRSAVE       (0x100)

#define SPR_USPRG0       (0x100)

#define SPR_USPRG4       (0x104)

#define SPR_USPRG5       (0x105)

#define SPR_USPRG6       (0x106)

#define SPR_BOOKE_ATBL   (0x20E)

#define SPR_BOOKE_ATBU   (0x20F)

#define SPR_IBAT0U       (0x210)

#define SPR_IBAT0L       (0x211)

#define SPR_IBAT1U       (0x212)

#define SPR_IBAT1L       (0x213)

#define SPR_IBAT2U       (0x214)

#define SPR_IBAT2L       (0x215)

#define SPR_E500_L1CFG0  (0x215)

#define SPR_IBAT3U       (0x216)

#define SPR_E500_L1CFG1  (0x216)

#define SPR_IBAT3L       (0x217)

#define SPR_DBAT4U       (0x238)

#define SPR_DBAT4L       (0x239)

#define SPR_DBAT5U       (0x23A)

#define SPR_DBAT5L       (0x23B)

#define SPR_DBAT6U       (0x23C)

#define SPR_DBAT6L       (0x23D)

#define SPR_E500_MCAR    (0x23D)

#define SPR_DBAT7U       (0x23E)

#define SPR_DBAT7L       (0x23F)

#define SPR_440_INV0     (0x370)

#define SPR_440_INV1     (0x371)

#define SPR_440_INV2     (0x372)

#define SPR_440_DVLIM    (0x398)

#define SPR_440_IVLIM    (0x399)

#define SPR_440_RSTCFG   (0x39B)

#define SPR_UMMCR0       (0x3A8)

#define SPR_UPMC1        (0x3A9)

#define SPR_UPMC2        (0x3AA)

#define SPR_UPMC4        (0x3AE)

#define SPR_USDA         (0x3AF)

#define SPR_40x_ZPR      (0x3B0)

#define SPR_40x_PID      (0x3B1)

#define SPR_440_MMUCR    (0x3B2)

#define SPR_4xx_CCR0     (0x3B3)

#define SPR_405_IAC3     (0x3B4)

#define SPR_405_IAC4     (0x3B5)

#define SPR_405_DVC1     (0x3B6)

#define SPR_405_DVC2     (0x3B7)

#define SPR_DCMP         (0x3D1)

#define SPR_HASH1        (0x3D2)

#define SPR_HASH2        (0x3D3)

#define SPR_IMISS        (0x3D4)

#define SPR_40x_ESR      (0x3D4)

#define SPR_ICMP         (0x3D5)

#define SPR_E500_L1CSR1  (0x3F3)

#define SPR_440_DBDR     (0x3F3)

#define SPR_40x_IAC1     (0x3F4)

#define SPR_DABR         (0x3F5)

#define DABR_MASK (~(target_ulong)0x7)

#define SPR_E500_BUCSR   (0x3F5)

#define SPR_601_HID5     (0x3F5)

#define SPR_40x_DAC1     (0x3F6)

#define SPR_40x_DAC2     (0x3F7)

#define SPR_L2PM         (0x3F8)

#define SPR_750_HID2     (0x3F8)

#define SPR_L2CR         (0x3F9)