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1
/*
2
 *  PowerPC CPU initialization for qemu.
3
 * 
4
 *  Copyright (c) 2003-2007 Jocelyn Mayer
5
 *
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 * This library is free software; you can redistribute it and/or
7
 * modify it under the terms of the GNU Lesser General Public
8
 * License as published by the Free Software Foundation; either
9
 * version 2 of the License, or (at your option) any later version.
10
 *
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 * This library is distributed in the hope that it will be useful,
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 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14
 * Lesser General Public License for more details.
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 *
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 * You should have received a copy of the GNU Lesser General Public
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 * License along with this library; if not, write to the Free Software
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 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
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 */
20

    
21
/* A lot of PowerPC definition have been included here.
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 * Most of them are not usable for now but have been kept
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 * inside "#if defined(TODO) ... #endif" statements to make tests easier.
24
 */
25

    
26
//#define PPC_DUMP_CPU
27
//#define PPC_DEBUG_SPR
28

    
29
struct ppc_def_t {
30
    const unsigned char *name;
31
    uint32_t pvr;
32
    uint32_t pvr_mask;
33
    uint64_t insns_flags;
34
    uint32_t flags;
35
    uint64_t msr_mask;
36
};
37

    
38
/* Generic callbacks:
39
 * do nothing but store/retrieve spr value
40
 */
41
static void spr_read_generic (void *opaque, int sprn)
42
{
43
    gen_op_load_spr(sprn);
44
}
45

    
46
static void spr_write_generic (void *opaque, int sprn)
47
{
48
    gen_op_store_spr(sprn);
49
}
50

    
51
/* SPR common to all PowerPC */
52
/* XER */
53
static void spr_read_xer (void *opaque, int sprn)
54
{
55
    gen_op_load_xer();
56
}
57

    
58
static void spr_write_xer (void *opaque, int sprn)
59
{
60
    gen_op_store_xer();
61
}
62

    
63
/* LR */
64
static void spr_read_lr (void *opaque, int sprn)
65
{
66
    gen_op_load_lr();
67
}
68

    
69
static void spr_write_lr (void *opaque, int sprn)
70
{
71
    gen_op_store_lr();
72
}
73

    
74
/* CTR */
75
static void spr_read_ctr (void *opaque, int sprn)
76
{
77
    gen_op_load_ctr();
78
}
79

    
80
static void spr_write_ctr (void *opaque, int sprn)
81
{
82
    gen_op_store_ctr();
83
}
84

    
85
/* User read access to SPR */
86
/* USPRx */
87
/* UMMCRx */
88
/* UPMCx */
89
/* USIA */
90
/* UDECR */
91
static void spr_read_ureg (void *opaque, int sprn)
92
{
93
    gen_op_load_spr(sprn + 0x10);
94
}
95

    
96
/* SPR common to all non-embedded PowerPC */
97
/* DECR */
98
#if !defined(CONFIG_USER_ONLY)
99
static void spr_read_decr (void *opaque, int sprn)
100
{
101
    gen_op_load_decr();
102
}
103

    
104
static void spr_write_decr (void *opaque, int sprn)
105
{
106
    gen_op_store_decr();
107
}
108
#endif
109

    
110
/* SPR common to all non-embedded PowerPC, except 601 */
111
/* Time base */
112
static void spr_read_tbl (void *opaque, int sprn)
113
{
114
    gen_op_load_tbl();
115
}
116

    
117
static void spr_read_tbu (void *opaque, int sprn)
118
{
119
    gen_op_load_tbu();
120
}
121

    
122
#if !defined(CONFIG_USER_ONLY)
123
static void spr_write_tbl (void *opaque, int sprn)
124
{
125
    gen_op_store_tbl();
126
}
127

    
128
static void spr_write_tbu (void *opaque, int sprn)
129
{
130
    gen_op_store_tbu();
131
}
132
#endif
133

    
134
#if !defined(CONFIG_USER_ONLY)
135
/* IBAT0U...IBAT0U */
136
/* IBAT0L...IBAT7L */
137
static void spr_read_ibat (void *opaque, int sprn)
138
{
139
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
140
}
141

    
142
static void spr_read_ibat_h (void *opaque, int sprn)
143
{
144
    gen_op_load_ibat(sprn & 1, (sprn - SPR_IBAT4U) / 2);
145
}
146

    
147
static void spr_write_ibatu (void *opaque, int sprn)
148
{
149
    DisasContext *ctx = opaque;
150

    
151
    gen_op_store_ibatu((sprn - SPR_IBAT0U) / 2);
152
    RET_STOP(ctx);
153
}
154

    
155
static void spr_write_ibatu_h (void *opaque, int sprn)
156
{
157
    DisasContext *ctx = opaque;
158

    
159
    gen_op_store_ibatu((sprn - SPR_IBAT4U) / 2);
160
    RET_STOP(ctx);
161
}
162

    
163
static void spr_write_ibatl (void *opaque, int sprn)
164
{
165
    DisasContext *ctx = opaque;
166

    
167
    gen_op_store_ibatl((sprn - SPR_IBAT0L) / 2);
168
    RET_STOP(ctx);
169
}
170

    
171
static void spr_write_ibatl_h (void *opaque, int sprn)
172
{
173
    DisasContext *ctx = opaque;
174

    
175
    gen_op_store_ibatl((sprn - SPR_IBAT4L) / 2);
176
    RET_STOP(ctx);
177
}
178

    
179
/* DBAT0U...DBAT7U */
180
/* DBAT0L...DBAT7L */
181
static void spr_read_dbat (void *opaque, int sprn)
182
{
183
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT0U) / 2);
184
}
185

    
186
static void spr_read_dbat_h (void *opaque, int sprn)
187
{
188
    gen_op_load_dbat(sprn & 1, (sprn - SPR_DBAT4U) / 2);
189
}
190

    
191
static void spr_write_dbatu (void *opaque, int sprn)
192
{
193
    DisasContext *ctx = opaque;
194

    
195
    gen_op_store_dbatu((sprn - SPR_DBAT0U) / 2);
196
    RET_STOP(ctx);
197
}
198

    
199
static void spr_write_dbatu_h (void *opaque, int sprn)
200
{
201
    DisasContext *ctx = opaque;
202

    
203
    gen_op_store_dbatu((sprn - SPR_DBAT4U) / 2);
204
    RET_STOP(ctx);
205
}
206

    
207
static void spr_write_dbatl (void *opaque, int sprn)
208
{
209
    DisasContext *ctx = opaque;
210

    
211
    gen_op_store_dbatl((sprn - SPR_DBAT0L) / 2);
212
    RET_STOP(ctx);
213
}
214

    
215
static void spr_write_dbatl_h (void *opaque, int sprn)
216
{
217
    DisasContext *ctx = opaque;
218

    
219
    gen_op_store_dbatl((sprn - SPR_DBAT4L) / 2);
220
    RET_STOP(ctx);
221
}
222

    
223
/* SDR1 */
224
static void spr_read_sdr1 (void *opaque, int sprn)
225
{
226
    gen_op_load_sdr1();
227
}
228

    
229
static void spr_write_sdr1 (void *opaque, int sprn)
230
{
231
    DisasContext *ctx = opaque;
232

    
233
    gen_op_store_sdr1();
234
    RET_STOP(ctx);
235
}
236

    
237
/* 64 bits PowerPC specific SPRs */
238
/* ASR */
239
#if defined(TARGET_PPC64)
240
static void spr_read_asr (void *opaque, int sprn)
241
{
242
    gen_op_load_asr();
243
}
244

    
245
static void spr_write_asr (void *opaque, int sprn)
246
{
247
    DisasContext *ctx = opaque;
248

    
249
    gen_op_store_asr();
250
    RET_STOP(ctx);
251
}
252
#endif
253
#endif /* !defined(CONFIG_USER_ONLY) */
254

    
255
/* PowerPC 601 specific registers */
256
/* RTC */
257
static void spr_read_601_rtcl (void *opaque, int sprn)
258
{
259
    gen_op_load_601_rtcl();
260
}
261

    
262
static void spr_read_601_rtcu (void *opaque, int sprn)
263
{
264
    gen_op_load_601_rtcu();
265
}
266

    
267
#if !defined(CONFIG_USER_ONLY)
268
static void spr_write_601_rtcu (void *opaque, int sprn)
269
{
270
    gen_op_store_601_rtcu();
271
}
272

    
273
static void spr_write_601_rtcl (void *opaque, int sprn)
274
{
275
    gen_op_store_601_rtcl();
276
}
277
#endif
278

    
279
/* Unified bats */
280
#if !defined(CONFIG_USER_ONLY)
281
static void spr_read_601_ubat (void *opaque, int sprn)
282
{
283
    gen_op_load_601_bat(sprn & 1, (sprn - SPR_IBAT0U) / 2);
284
}
285

    
286
static void spr_write_601_ubatu (void *opaque, int sprn)
287
{
288
    DisasContext *ctx = opaque;
289

    
290
    gen_op_store_601_batu((sprn - SPR_IBAT0U) / 2);
291
    RET_STOP(ctx);
292
}
293

    
294
static void spr_write_601_ubatl (void *opaque, int sprn)
295
{
296
    DisasContext *ctx = opaque;
297

    
298
    gen_op_store_601_batl((sprn - SPR_IBAT0L) / 2);
299
    RET_STOP(ctx);
300
}
301
#endif
302

    
303
/* PowerPC 40x specific registers */
304
#if !defined(CONFIG_USER_ONLY)
305
static void spr_read_40x_pit (void *opaque, int sprn)
306
{
307
    gen_op_load_40x_pit();
308
}
309

    
310
static void spr_write_40x_pit (void *opaque, int sprn)
311
{
312
    gen_op_store_40x_pit();
313
}
314

    
315
static void spr_write_booke_tcr (void *opaque, int sprn)
316
{
317
    gen_op_store_booke_tcr();
318
}
319

    
320
static void spr_write_booke_tsr (void *opaque, int sprn)
321
{
322
    gen_op_store_booke_tsr();
323
}
324
#endif
325

    
326
/* PowerPC 403 specific registers */
327
/* PBL1 / PBU1 / PBL2 / PBU2 */
328
#if !defined(CONFIG_USER_ONLY)
329
static void spr_read_403_pbr (void *opaque, int sprn)
330
{
331
    gen_op_load_403_pb(sprn - SPR_403_PBL1);
332
}
333

    
334
static void spr_write_403_pbr (void *opaque, int sprn)
335
{
336
    DisasContext *ctx = opaque;
337

    
338
    gen_op_store_403_pb(sprn - SPR_403_PBL1);
339
    RET_STOP(ctx);
340
}
341

    
342
static void spr_write_pir (void *opaque, int sprn)
343
{
344
    gen_op_store_pir();
345
}
346
#endif
347

    
348
#if defined(CONFIG_USER_ONLY)
349
#define spr_register(env, num, name, uea_read, uea_write,                     \
350
                     oea_read, oea_write, initial_value)                      \
351
do {                                                                          \
352
     _spr_register(env, num, name, uea_read, uea_write, initial_value);       \
353
} while (0)
354
static inline void _spr_register (CPUPPCState *env, int num,
355
                                  const unsigned char *name,
356
                                  void (*uea_read)(void *opaque, int sprn),
357
                                  void (*uea_write)(void *opaque, int sprn),
358
                                  target_ulong initial_value)
359
#else
360
static inline void spr_register (CPUPPCState *env, int num,
361
                                 const unsigned char *name,
362
                                 void (*uea_read)(void *opaque, int sprn),
363
                                 void (*uea_write)(void *opaque, int sprn),
364
                                 void (*oea_read)(void *opaque, int sprn),
365
                                 void (*oea_write)(void *opaque, int sprn),
366
                                 target_ulong initial_value)
367
#endif
368
{
369
    ppc_spr_t *spr;
370

    
371
    spr = &env->spr_cb[num];
372
    if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
373
#if !defined(CONFIG_USER_ONLY)
374
        spr->oea_read != NULL || spr->oea_write != NULL ||
375
#endif
376
        spr->uea_read != NULL || spr->uea_write != NULL) {
377
        printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
378
        exit(1);
379
    }
380
#if defined(PPC_DEBUG_SPR)
381
    printf("*** register spr %d (%03x) %s val " ADDRX "\n", num, num, name,
382
           initial_value);
383
#endif
384
    spr->name = name;
385
    spr->uea_read = uea_read;
386
    spr->uea_write = uea_write;
387
#if !defined(CONFIG_USER_ONLY)
388
    spr->oea_read = oea_read;
389
    spr->oea_write = oea_write;
390
#endif
391
    env->spr[num] = initial_value;
392
}
393

    
394
/* Generic PowerPC SPRs */
395
static void gen_spr_generic (CPUPPCState *env)
396
{
397
    /* Integer processing */
398
    spr_register(env, SPR_XER, "XER",
399
                 &spr_read_xer, &spr_write_xer,
400
                 &spr_read_xer, &spr_write_xer,
401
                 0x00000000);
402
    /* Branch contol */
403
    spr_register(env, SPR_LR, "LR",
404
                 &spr_read_lr, &spr_write_lr,
405
                 &spr_read_lr, &spr_write_lr,
406
                 0x00000000);
407
    spr_register(env, SPR_CTR, "CTR",
408
                 &spr_read_ctr, &spr_write_ctr,
409
                 &spr_read_ctr, &spr_write_ctr,
410
                 0x00000000);
411
    /* Interrupt processing */
412
    spr_register(env, SPR_SRR0, "SRR0",
413
                 SPR_NOACCESS, SPR_NOACCESS,
414
                 &spr_read_generic, &spr_write_generic,
415
                 0x00000000);
416
    spr_register(env, SPR_SRR1, "SRR1",
417
                 SPR_NOACCESS, SPR_NOACCESS,
418
                 &spr_read_generic, &spr_write_generic,
419
                 0x00000000);
420
    /* Processor control */
421
    spr_register(env, SPR_SPRG0, "SPRG0",
422
                 SPR_NOACCESS, SPR_NOACCESS,
423
                 &spr_read_generic, &spr_write_generic,
424
                 0x00000000);
425
    spr_register(env, SPR_SPRG1, "SPRG1",
426
                 SPR_NOACCESS, SPR_NOACCESS,
427
                 &spr_read_generic, &spr_write_generic,
428
                 0x00000000);
429
    spr_register(env, SPR_SPRG2, "SPRG2",
430
                 SPR_NOACCESS, SPR_NOACCESS,
431
                 &spr_read_generic, &spr_write_generic,
432
                 0x00000000);
433
    spr_register(env, SPR_SPRG3, "SPRG3",
434
                 SPR_NOACCESS, SPR_NOACCESS,
435
                 &spr_read_generic, &spr_write_generic,
436
                 0x00000000);
437
}
438

    
439
/* SPR common to all non-embedded PowerPC, including 601 */
440
static void gen_spr_ne_601 (CPUPPCState *env)
441
{
442
    /* Exception processing */
443
    spr_register(env, SPR_DSISR, "DSISR",
444
                 SPR_NOACCESS, SPR_NOACCESS,
445
                 &spr_read_generic, &spr_write_generic,
446
                 0x00000000);
447
    spr_register(env, SPR_DAR, "DAR",
448
                 SPR_NOACCESS, SPR_NOACCESS,
449
                 &spr_read_generic, &spr_write_generic,
450
                 0x00000000);
451
    /* Timer */
452
    spr_register(env, SPR_DECR, "DECR",
453
                 SPR_NOACCESS, SPR_NOACCESS,
454
                 &spr_read_decr, &spr_write_decr,
455
                 0x00000000);
456
    /* Memory management */
457
    spr_register(env, SPR_SDR1, "SDR1",
458
                 SPR_NOACCESS, SPR_NOACCESS,
459
                 &spr_read_sdr1, &spr_write_sdr1,
460
                 0x00000000);
461
}
462

    
463
/* BATs 0-3 */
464
static void gen_low_BATs (CPUPPCState *env)
465
{
466
    spr_register(env, SPR_IBAT0U, "IBAT0U",
467
                 SPR_NOACCESS, SPR_NOACCESS,
468
                 &spr_read_ibat, &spr_write_ibatu,
469
                 0x00000000);
470
    spr_register(env, SPR_IBAT0L, "IBAT0L",
471
                 SPR_NOACCESS, SPR_NOACCESS,
472
                 &spr_read_ibat, &spr_write_ibatl,
473
                 0x00000000);
474
    spr_register(env, SPR_IBAT1U, "IBAT1U",
475
                 SPR_NOACCESS, SPR_NOACCESS,
476
                 &spr_read_ibat, &spr_write_ibatu,
477
                 0x00000000);
478
    spr_register(env, SPR_IBAT1L, "IBAT1L",
479
                 SPR_NOACCESS, SPR_NOACCESS,
480
                 &spr_read_ibat, &spr_write_ibatl,
481
                 0x00000000);
482
    spr_register(env, SPR_IBAT2U, "IBAT2U",
483
                 SPR_NOACCESS, SPR_NOACCESS,
484
                 &spr_read_ibat, &spr_write_ibatu,
485
                 0x00000000);
486
    spr_register(env, SPR_IBAT2L, "IBAT2L",
487
                 SPR_NOACCESS, SPR_NOACCESS,
488
                 &spr_read_ibat, &spr_write_ibatl,
489
                 0x00000000);
490
    spr_register(env, SPR_IBAT3U, "IBAT3U",
491
                 SPR_NOACCESS, SPR_NOACCESS,
492
                 &spr_read_ibat, &spr_write_ibatu,
493
                 0x00000000);
494
    spr_register(env, SPR_IBAT3L, "IBAT3L",
495
                 SPR_NOACCESS, SPR_NOACCESS,
496
                 &spr_read_ibat, &spr_write_ibatl,
497
                 0x00000000);
498
    spr_register(env, SPR_DBAT0U, "DBAT0U",
499
                 SPR_NOACCESS, SPR_NOACCESS,
500
                 &spr_read_dbat, &spr_write_dbatu,
501
                 0x00000000);
502
    spr_register(env, SPR_DBAT0L, "DBAT0L",
503
                 SPR_NOACCESS, SPR_NOACCESS,
504
                 &spr_read_dbat, &spr_write_dbatl,
505
                 0x00000000);
506
    spr_register(env, SPR_DBAT1U, "DBAT1U",
507
                 SPR_NOACCESS, SPR_NOACCESS,
508
                 &spr_read_dbat, &spr_write_dbatu,
509
                 0x00000000);
510
    spr_register(env, SPR_DBAT1L, "DBAT1L",
511
                 SPR_NOACCESS, SPR_NOACCESS,
512
                 &spr_read_dbat, &spr_write_dbatl,
513
                 0x00000000);
514
    spr_register(env, SPR_DBAT2U, "DBAT2U",
515
                 SPR_NOACCESS, SPR_NOACCESS,
516
                 &spr_read_dbat, &spr_write_dbatu,
517
                 0x00000000);
518
    spr_register(env, SPR_DBAT2L, "DBAT2L",
519
                 SPR_NOACCESS, SPR_NOACCESS,
520
                 &spr_read_dbat, &spr_write_dbatl,
521
                 0x00000000);
522
    spr_register(env, SPR_DBAT3U, "DBAT3U",
523
                 SPR_NOACCESS, SPR_NOACCESS,
524
                 &spr_read_dbat, &spr_write_dbatu,
525
                 0x00000000);
526
    spr_register(env, SPR_DBAT3L, "DBAT3L",
527
                 SPR_NOACCESS, SPR_NOACCESS,
528
                 &spr_read_dbat, &spr_write_dbatl,
529
                 0x00000000);
530
    env->nb_BATs = 4;
531
}
532

    
533
/* BATs 4-7 */
534
static void gen_high_BATs (CPUPPCState *env)
535
{
536
    spr_register(env, SPR_IBAT4U, "IBAT4U",
537
                 SPR_NOACCESS, SPR_NOACCESS,
538
                 &spr_read_ibat_h, &spr_write_ibatu_h,
539
                 0x00000000);
540
    spr_register(env, SPR_IBAT4L, "IBAT4L",
541
                 SPR_NOACCESS, SPR_NOACCESS,
542
                 &spr_read_ibat_h, &spr_write_ibatl_h,
543
                 0x00000000);
544
    spr_register(env, SPR_IBAT5U, "IBAT5U",
545
                 SPR_NOACCESS, SPR_NOACCESS,
546
                 &spr_read_ibat_h, &spr_write_ibatu_h,
547
                 0x00000000);
548
    spr_register(env, SPR_IBAT5L, "IBAT5L",
549
                 SPR_NOACCESS, SPR_NOACCESS,
550
                 &spr_read_ibat_h, &spr_write_ibatl_h,
551
                 0x00000000);
552
    spr_register(env, SPR_IBAT6U, "IBAT6U",
553
                 SPR_NOACCESS, SPR_NOACCESS,
554
                 &spr_read_ibat_h, &spr_write_ibatu_h,
555
                 0x00000000);
556
    spr_register(env, SPR_IBAT6L, "IBAT6L",
557
                 SPR_NOACCESS, SPR_NOACCESS,
558
                 &spr_read_ibat_h, &spr_write_ibatl_h,
559
                 0x00000000);
560
    spr_register(env, SPR_IBAT7U, "IBAT7U",
561
                 SPR_NOACCESS, SPR_NOACCESS,
562
                 &spr_read_ibat_h, &spr_write_ibatu_h,
563
                 0x00000000);
564
    spr_register(env, SPR_IBAT7L, "IBAT7L",
565
                 SPR_NOACCESS, SPR_NOACCESS,
566
                 &spr_read_ibat_h, &spr_write_ibatl_h,
567
                 0x00000000);
568
    spr_register(env, SPR_DBAT4U, "DBAT4U",
569
                 SPR_NOACCESS, SPR_NOACCESS,
570
                 &spr_read_dbat_h, &spr_write_dbatu_h,
571
                 0x00000000);
572
    spr_register(env, SPR_DBAT4L, "DBAT4L",
573
                 SPR_NOACCESS, SPR_NOACCESS,
574
                 &spr_read_dbat_h, &spr_write_dbatl_h,
575
                 0x00000000);
576
    spr_register(env, SPR_DBAT5U, "DBAT5U",
577
                 SPR_NOACCESS, SPR_NOACCESS,
578
                 &spr_read_dbat_h, &spr_write_dbatu_h,
579
                 0x00000000);
580
    spr_register(env, SPR_DBAT5L, "DBAT5L",
581
                 SPR_NOACCESS, SPR_NOACCESS,
582
                 &spr_read_dbat_h, &spr_write_dbatl_h,
583
                 0x00000000);
584
    spr_register(env, SPR_DBAT6U, "DBAT6U",
585
                 SPR_NOACCESS, SPR_NOACCESS,
586
                 &spr_read_dbat_h, &spr_write_dbatu_h,
587
                 0x00000000);
588
    spr_register(env, SPR_DBAT6L, "DBAT6L",
589
                 SPR_NOACCESS, SPR_NOACCESS,
590
                 &spr_read_dbat_h, &spr_write_dbatl_h,
591
                 0x00000000);
592
    spr_register(env, SPR_DBAT7U, "DBAT7U",
593
                 SPR_NOACCESS, SPR_NOACCESS,
594
                 &spr_read_dbat_h, &spr_write_dbatu_h,
595
                 0x00000000);
596
    spr_register(env, SPR_DBAT7L, "DBAT7L",
597
                 SPR_NOACCESS, SPR_NOACCESS,
598
                 &spr_read_dbat_h, &spr_write_dbatl_h,
599
                 0x00000000);
600
    env->nb_BATs = 8;
601
}
602

    
603
/* Generic PowerPC time base */
604
static void gen_tbl (CPUPPCState *env)
605
{
606
    spr_register(env, SPR_VTBL,  "TBL",
607
                 &spr_read_tbl, SPR_NOACCESS,
608
                 &spr_read_tbl, SPR_NOACCESS,
609
                 0x00000000);
610
    spr_register(env, SPR_TBL,   "TBL",
611
                 SPR_NOACCESS, SPR_NOACCESS,
612
                 SPR_NOACCESS, &spr_write_tbl,
613
                 0x00000000);
614
    spr_register(env, SPR_VTBU,  "TBU",
615
                 &spr_read_tbu, SPR_NOACCESS,
616
                 &spr_read_tbu, SPR_NOACCESS,
617
                 0x00000000);
618
    spr_register(env, SPR_TBU,   "TBU",
619
                 SPR_NOACCESS, SPR_NOACCESS,
620
                 SPR_NOACCESS, &spr_write_tbu,
621
                 0x00000000);
622
}
623

    
624
/* Softare table search registers */
625
static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
626
{
627
    env->nb_tlb = nb_tlbs;
628
    env->nb_ways = nb_ways;
629
    env->id_tlbs = 1;
630
    spr_register(env, SPR_DMISS, "DMISS",
631
                 SPR_NOACCESS, SPR_NOACCESS,
632
                 &spr_read_generic, SPR_NOACCESS,
633
                 0x00000000);
634
    spr_register(env, SPR_DCMP, "DCMP",
635
                 SPR_NOACCESS, SPR_NOACCESS,
636
                 &spr_read_generic, SPR_NOACCESS,
637
                 0x00000000);
638
    spr_register(env, SPR_HASH1, "HASH1",
639
                 SPR_NOACCESS, SPR_NOACCESS,
640
                 &spr_read_generic, SPR_NOACCESS,
641
                 0x00000000);
642
    spr_register(env, SPR_HASH2, "HASH2",
643
                 SPR_NOACCESS, SPR_NOACCESS,
644
                 &spr_read_generic, SPR_NOACCESS,
645
                 0x00000000);
646
    spr_register(env, SPR_IMISS, "IMISS",
647
                 SPR_NOACCESS, SPR_NOACCESS,
648
                 &spr_read_generic, SPR_NOACCESS,
649
                 0x00000000);
650
    spr_register(env, SPR_ICMP, "ICMP",
651
                 SPR_NOACCESS, SPR_NOACCESS,
652
                 &spr_read_generic, SPR_NOACCESS,
653
                 0x00000000);
654
    spr_register(env, SPR_RPA, "RPA",
655
                 SPR_NOACCESS, SPR_NOACCESS,
656
                 &spr_read_generic, &spr_write_generic,
657
                 0x00000000);
658
}
659

    
660
/* SPR common to MPC755 and G2 */
661
static void gen_spr_G2_755 (CPUPPCState *env)
662
{
663
    /* SGPRs */
664
    spr_register(env, SPR_SPRG4, "SPRG4",
665
                 SPR_NOACCESS, SPR_NOACCESS,
666
                 &spr_read_generic, &spr_write_generic,
667
                 0x00000000);
668
    spr_register(env, SPR_SPRG5, "SPRG5",
669
                 SPR_NOACCESS, SPR_NOACCESS,
670
                 &spr_read_generic, &spr_write_generic,
671
                 0x00000000);
672
    spr_register(env, SPR_SPRG6, "SPRG6",
673
                 SPR_NOACCESS, SPR_NOACCESS,
674
                 &spr_read_generic, &spr_write_generic,
675
                 0x00000000);
676
    spr_register(env, SPR_SPRG7, "SPRG7",
677
                 SPR_NOACCESS, SPR_NOACCESS,
678
                 &spr_read_generic, &spr_write_generic,
679
                 0x00000000);
680
    /* External access control */
681
    /* XXX : not implemented */
682
    spr_register(env, SPR_EAR, "EAR",
683
                 SPR_NOACCESS, SPR_NOACCESS,
684
                 &spr_read_generic, &spr_write_generic,
685
                 0x00000000);
686
}
687

    
688
/* SPR common to all 7xx PowerPC implementations */
689
static void gen_spr_7xx (CPUPPCState *env)
690
{
691
    /* Breakpoints */
692
    /* XXX : not implemented */
693
    spr_register(env, SPR_DABR, "DABR",
694
                 SPR_NOACCESS, SPR_NOACCESS,
695
                 &spr_read_generic, &spr_write_generic,
696
                 0x00000000);
697
    /* XXX : not implemented */
698
    spr_register(env, SPR_IABR, "IABR",
699
                 SPR_NOACCESS, SPR_NOACCESS,
700
                 &spr_read_generic, &spr_write_generic,
701
                 0x00000000);
702
    /* Cache management */
703
    /* XXX : not implemented */
704
    spr_register(env, SPR_ICTC, "ICTC",
705
                 SPR_NOACCESS, SPR_NOACCESS,
706
                 &spr_read_generic, &spr_write_generic,
707
                 0x00000000);
708
    /* XXX : not implemented */
709
    spr_register(env, SPR_L2CR, "L2CR",
710
                 SPR_NOACCESS, SPR_NOACCESS,
711
                 &spr_read_generic, &spr_write_generic,
712
                 0x00000000);
713
    /* Performance monitors */
714
    /* XXX : not implemented */
715
    spr_register(env, SPR_MMCR0, "MMCR0",
716
                 SPR_NOACCESS, SPR_NOACCESS,
717
                 &spr_read_generic, &spr_write_generic,
718
                 0x00000000);
719
    /* XXX : not implemented */
720
    spr_register(env, SPR_MMCR1, "MMCR1",
721
                 SPR_NOACCESS, SPR_NOACCESS,
722
                 &spr_read_generic, &spr_write_generic,
723
                 0x00000000);
724
    /* XXX : not implemented */
725
    spr_register(env, SPR_PMC1, "PMC1",
726
                 SPR_NOACCESS, SPR_NOACCESS,
727
                 &spr_read_generic, &spr_write_generic,
728
                 0x00000000);
729
    /* XXX : not implemented */
730
    spr_register(env, SPR_PMC2, "PMC2",
731
                 SPR_NOACCESS, SPR_NOACCESS,
732
                 &spr_read_generic, &spr_write_generic,
733
                 0x00000000);
734
    /* XXX : not implemented */
735
    spr_register(env, SPR_PMC3, "PMC3",
736
                 SPR_NOACCESS, SPR_NOACCESS,
737
                 &spr_read_generic, &spr_write_generic,
738
                 0x00000000);
739
    /* XXX : not implemented */
740
    spr_register(env, SPR_PMC4, "PMC4",
741
                 SPR_NOACCESS, SPR_NOACCESS,
742
                 &spr_read_generic, &spr_write_generic,
743
                 0x00000000);
744
    /* XXX : not implemented */
745
    spr_register(env, SPR_SIA, "SIA",
746
                 SPR_NOACCESS, SPR_NOACCESS,
747
                 &spr_read_generic, SPR_NOACCESS,
748
                 0x00000000);
749
    spr_register(env, SPR_UMMCR0, "UMMCR0",
750
                 &spr_read_ureg, SPR_NOACCESS,
751
                 &spr_read_ureg, SPR_NOACCESS,
752
                 0x00000000);
753
    spr_register(env, SPR_UMMCR1, "UMMCR1",
754
                 &spr_read_ureg, SPR_NOACCESS,
755
                 &spr_read_ureg, SPR_NOACCESS,
756
                 0x00000000);
757
    spr_register(env, SPR_UPMC1, "UPMC1",
758
                 &spr_read_ureg, SPR_NOACCESS,
759
                 &spr_read_ureg, SPR_NOACCESS,
760
                 0x00000000);
761
    spr_register(env, SPR_UPMC2, "UPMC2",
762
                 &spr_read_ureg, SPR_NOACCESS,
763
                 &spr_read_ureg, SPR_NOACCESS,
764
                 0x00000000);
765
    spr_register(env, SPR_UPMC3, "UPMC3",
766
                 &spr_read_ureg, SPR_NOACCESS,
767
                 &spr_read_ureg, SPR_NOACCESS,
768
                 0x00000000);
769
    spr_register(env, SPR_UPMC4, "UPMC4",
770
                 &spr_read_ureg, SPR_NOACCESS,
771
                 &spr_read_ureg, SPR_NOACCESS,
772
                 0x00000000);
773
    spr_register(env, SPR_USIA, "USIA",
774
                 &spr_read_ureg, SPR_NOACCESS,
775
                 &spr_read_ureg, SPR_NOACCESS,
776
                 0x00000000);
777
    /* Thermal management */
778
    /* XXX : not implemented */
779
    spr_register(env, SPR_THRM1, "THRM1",
780
                 SPR_NOACCESS, SPR_NOACCESS,
781
                 &spr_read_generic, &spr_write_generic,
782
                 0x00000000);
783
    /* XXX : not implemented */
784
    spr_register(env, SPR_THRM2, "THRM2",
785
                 SPR_NOACCESS, SPR_NOACCESS,
786
                 &spr_read_generic, &spr_write_generic,
787
                 0x00000000);
788
    /* XXX : not implemented */
789
    spr_register(env, SPR_THRM3, "THRM3",
790
                 SPR_NOACCESS, SPR_NOACCESS,
791
                 &spr_read_generic, &spr_write_generic,
792
                 0x00000000);
793
    /* External access control */
794
    /* XXX : not implemented */
795
    spr_register(env, SPR_EAR, "EAR",
796
                 SPR_NOACCESS, SPR_NOACCESS,
797
                 &spr_read_generic, &spr_write_generic,
798
                 0x00000000);
799
}
800

    
801
/* SPR specific to PowerPC 604 implementation */
802
static void gen_spr_604 (CPUPPCState *env)
803
{
804
    /* Processor identification */
805
    spr_register(env, SPR_PIR, "PIR",
806
                 SPR_NOACCESS, SPR_NOACCESS,
807
                 &spr_read_generic, &spr_write_pir,
808
                 0x00000000);
809
    /* Breakpoints */
810
    /* XXX : not implemented */
811
    spr_register(env, SPR_IABR, "IABR",
812
                 SPR_NOACCESS, SPR_NOACCESS,
813
                 &spr_read_generic, &spr_write_generic,
814
                 0x00000000);
815
    /* XXX : not implemented */
816
    spr_register(env, SPR_DABR, "DABR",
817
                 SPR_NOACCESS, SPR_NOACCESS,
818
                 &spr_read_generic, &spr_write_generic,
819
                 0x00000000);
820
    /* Performance counters */
821
    /* XXX : not implemented */
822
    spr_register(env, SPR_MMCR0, "MMCR0",
823
                 SPR_NOACCESS, SPR_NOACCESS,
824
                 &spr_read_generic, &spr_write_generic,
825
                 0x00000000);
826
    /* XXX : not implemented */
827
    spr_register(env, SPR_MMCR1, "MMCR1",
828
                 SPR_NOACCESS, SPR_NOACCESS,
829
                 &spr_read_generic, &spr_write_generic,
830
                 0x00000000);
831
    /* XXX : not implemented */
832
    spr_register(env, SPR_PMC1, "PMC1",
833
                 SPR_NOACCESS, SPR_NOACCESS,
834
                 &spr_read_generic, &spr_write_generic,
835
                 0x00000000);
836
    /* XXX : not implemented */
837
    spr_register(env, SPR_PMC2, "PMC2",
838
                 SPR_NOACCESS, SPR_NOACCESS,
839
                 &spr_read_generic, &spr_write_generic,
840
                 0x00000000);
841
    /* XXX : not implemented */
842
    spr_register(env, SPR_PMC3, "PMC3",
843
                 SPR_NOACCESS, SPR_NOACCESS,
844
                 &spr_read_generic, &spr_write_generic,
845
                 0x00000000);
846
    /* XXX : not implemented */
847
    spr_register(env, SPR_PMC4, "PMC4",
848
                 SPR_NOACCESS, SPR_NOACCESS,
849
                 &spr_read_generic, &spr_write_generic,
850
                 0x00000000);
851
    /* XXX : not implemented */
852
    spr_register(env, SPR_SIA, "SIA",
853
                 SPR_NOACCESS, SPR_NOACCESS,
854
                 &spr_read_generic, SPR_NOACCESS,
855
                 0x00000000);
856
    /* XXX : not implemented */
857
    spr_register(env, SPR_SDA, "SDA",
858
                 SPR_NOACCESS, SPR_NOACCESS,
859
                 &spr_read_generic, SPR_NOACCESS,
860
                 0x00000000);
861
    /* External access control */
862
    /* XXX : not implemented */
863
    spr_register(env, SPR_EAR, "EAR",
864
                 SPR_NOACCESS, SPR_NOACCESS,
865
                 &spr_read_generic, &spr_write_generic,
866
                 0x00000000);
867
}
868

    
869
/* SPR specific to PowerPC 603 implementation */
870
static void gen_spr_603 (CPUPPCState *env)
871
{
872
    /* External access control */
873
    /* XXX : not implemented */
874
    spr_register(env, SPR_EAR, "EAR",
875
                 SPR_NOACCESS, SPR_NOACCESS,
876
                 &spr_read_generic, &spr_write_generic,
877
                 0x00000000);
878
}
879

    
880
/* SPR specific to PowerPC G2 implementation */
881
static void gen_spr_G2 (CPUPPCState *env)
882
{
883
    /* Memory base address */
884
    /* MBAR */
885
    spr_register(env, SPR_MBAR, "MBAR",
886
                 SPR_NOACCESS, SPR_NOACCESS,
887
                 &spr_read_generic, &spr_write_generic,
888
                 0x00000000);
889
    /* System version register */
890
    /* SVR */
891
    spr_register(env, SPR_SVR, "SVR",
892
                 SPR_NOACCESS, SPR_NOACCESS,
893
                 &spr_read_generic, SPR_NOACCESS,
894
                 0x00000000);
895
    /* Exception processing */
896
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
897
                 SPR_NOACCESS, SPR_NOACCESS,
898
                 &spr_read_generic, &spr_write_generic,
899
                 0x00000000);
900
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
901
                 SPR_NOACCESS, SPR_NOACCESS,
902
                 &spr_read_generic, &spr_write_generic,
903
                 0x00000000);
904
    /* Breakpoints */
905
    /* XXX : not implemented */
906
    spr_register(env, SPR_DABR, "DABR",
907
                 SPR_NOACCESS, SPR_NOACCESS,
908
                 &spr_read_generic, &spr_write_generic,
909
                 0x00000000);
910
    /* XXX : not implemented */
911
    spr_register(env, SPR_DABR2, "DABR2",
912
                 SPR_NOACCESS, SPR_NOACCESS,
913
                 &spr_read_generic, &spr_write_generic,
914
                 0x00000000);
915
    /* XXX : not implemented */
916
    spr_register(env, SPR_IABR, "IABR",
917
                 SPR_NOACCESS, SPR_NOACCESS,
918
                 &spr_read_generic, &spr_write_generic,
919
                 0x00000000);
920
    /* XXX : not implemented */
921
    spr_register(env, SPR_IABR2, "IABR2",
922
                 SPR_NOACCESS, SPR_NOACCESS,
923
                 &spr_read_generic, &spr_write_generic,
924
                 0x00000000);
925
    /* XXX : not implemented */
926
    spr_register(env, SPR_IBCR, "IBCR",
927
                 SPR_NOACCESS, SPR_NOACCESS,
928
                 &spr_read_generic, &spr_write_generic,
929
                 0x00000000);
930
    /* XXX : not implemented */
931
    spr_register(env, SPR_DBCR, "DBCR",
932
                 SPR_NOACCESS, SPR_NOACCESS,
933
                 &spr_read_generic, &spr_write_generic,
934
                 0x00000000);
935
}
936

    
937
/* SPR specific to PowerPC 602 implementation */
938
static void gen_spr_602 (CPUPPCState *env)
939
{
940
    /* ESA registers */
941
    /* XXX : not implemented */
942
    spr_register(env, SPR_SER, "SER",
943
                 SPR_NOACCESS, SPR_NOACCESS,
944
                 &spr_read_generic, &spr_write_generic,
945
                 0x00000000);
946
    /* XXX : not implemented */
947
    spr_register(env, SPR_SEBR, "SEBR",
948
                 SPR_NOACCESS, SPR_NOACCESS,
949
                 &spr_read_generic, &spr_write_generic,
950
                 0x00000000);
951
    /* XXX : not implemented */
952
    spr_register(env, SPR_ESASR, "ESASR",
953
                 SPR_NOACCESS, SPR_NOACCESS,
954
                 &spr_read_generic, &spr_write_generic,
955
                 0x00000000);
956
    /* Floating point status */
957
    /* XXX : not implemented */
958
    spr_register(env, SPR_SP, "SP",
959
                 SPR_NOACCESS, SPR_NOACCESS,
960
                 &spr_read_generic, &spr_write_generic,
961
                 0x00000000);
962
    /* XXX : not implemented */
963
    spr_register(env, SPR_LT, "LT",
964
                 SPR_NOACCESS, SPR_NOACCESS,
965
                 &spr_read_generic, &spr_write_generic,
966
                 0x00000000);
967
    /* Watchdog timer */
968
    /* XXX : not implemented */
969
    spr_register(env, SPR_TCR, "TCR",
970
                 SPR_NOACCESS, SPR_NOACCESS,
971
                 &spr_read_generic, &spr_write_generic,
972
                 0x00000000);
973
    /* Interrupt base */
974
    spr_register(env, SPR_IBR, "IBR",
975
                 SPR_NOACCESS, SPR_NOACCESS,
976
                 &spr_read_generic, &spr_write_generic,
977
                 0x00000000);
978
}
979

    
980
/* SPR specific to PowerPC 601 implementation */
981
static void gen_spr_601 (CPUPPCState *env)
982
{
983
    /* Multiplication/division register */
984
    /* MQ */
985
    spr_register(env, SPR_MQ, "MQ",
986
                 &spr_read_generic, &spr_write_generic,
987
                 &spr_read_generic, &spr_write_generic,
988
                 0x00000000);
989
    /* RTC registers */
990
    spr_register(env, SPR_601_RTCU, "RTCU",
991
                 SPR_NOACCESS, SPR_NOACCESS,
992
                 SPR_NOACCESS, &spr_write_601_rtcu,
993
                 0x00000000);
994
    spr_register(env, SPR_601_VRTCU, "RTCU",
995
                 &spr_read_601_rtcu, SPR_NOACCESS,
996
                 &spr_read_601_rtcu, SPR_NOACCESS,
997
                 0x00000000);
998
    spr_register(env, SPR_601_RTCL, "RTCL",
999
                 SPR_NOACCESS, SPR_NOACCESS,
1000
                 SPR_NOACCESS, &spr_write_601_rtcl,
1001
                 0x00000000);
1002
    spr_register(env, SPR_601_VRTCL, "RTCL",
1003
                 &spr_read_601_rtcl, SPR_NOACCESS,
1004
                 &spr_read_601_rtcl, SPR_NOACCESS,
1005
                 0x00000000);
1006
    /* Timer */
1007
#if 0 /* ? */
1008
    spr_register(env, SPR_601_UDECR, "UDECR",
1009
                 &spr_read_decr, SPR_NOACCESS,
1010
                 &spr_read_decr, SPR_NOACCESS,
1011
                 0x00000000);
1012
#endif
1013
    /* External access control */
1014
    /* XXX : not implemented */
1015
    spr_register(env, SPR_EAR, "EAR",
1016
                 SPR_NOACCESS, SPR_NOACCESS,
1017
                 &spr_read_generic, &spr_write_generic,
1018
                 0x00000000);
1019
    /* Memory management */
1020
    spr_register(env, SPR_IBAT0U, "IBAT0U",
1021
                 SPR_NOACCESS, SPR_NOACCESS,
1022
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1023
                 0x00000000);
1024
    spr_register(env, SPR_IBAT0L, "IBAT0L",
1025
                 SPR_NOACCESS, SPR_NOACCESS,
1026
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1027
                 0x00000000);
1028
    spr_register(env, SPR_IBAT1U, "IBAT1U",
1029
                 SPR_NOACCESS, SPR_NOACCESS,
1030
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1031
                 0x00000000);
1032
    spr_register(env, SPR_IBAT1L, "IBAT1L",
1033
                 SPR_NOACCESS, SPR_NOACCESS,
1034
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1035
                 0x00000000);
1036
    spr_register(env, SPR_IBAT2U, "IBAT2U",
1037
                 SPR_NOACCESS, SPR_NOACCESS,
1038
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1039
                 0x00000000);
1040
    spr_register(env, SPR_IBAT2L, "IBAT2L",
1041
                 SPR_NOACCESS, SPR_NOACCESS,
1042
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1043
                 0x00000000);
1044
    spr_register(env, SPR_IBAT3U, "IBAT3U",
1045
                 SPR_NOACCESS, SPR_NOACCESS,
1046
                 &spr_read_601_ubat, &spr_write_601_ubatu,
1047
                 0x00000000);
1048
    spr_register(env, SPR_IBAT3L, "IBAT3L",
1049
                 SPR_NOACCESS, SPR_NOACCESS,
1050
                 &spr_read_601_ubat, &spr_write_601_ubatl,
1051
                 0x00000000);
1052
}
1053

    
1054
/* PowerPC BookE SPR */
1055
static void gen_spr_BookE (CPUPPCState *env)
1056
{
1057
    /* Processor identification */
1058
    spr_register(env, SPR_BOOKE_PIR, "PIR",
1059
                 SPR_NOACCESS, SPR_NOACCESS,
1060
                 &spr_read_generic, &spr_write_pir,
1061
                 0x00000000);
1062
    /* Interrupt processing */
1063
    spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1064
                 SPR_NOACCESS, SPR_NOACCESS,
1065
                 &spr_read_generic, &spr_write_generic,
1066
                 0x00000000);
1067
    spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1068
                 SPR_NOACCESS, SPR_NOACCESS,
1069
                 &spr_read_generic, &spr_write_generic,
1070
                 0x00000000);
1071
    spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
1072
                 SPR_NOACCESS, SPR_NOACCESS,
1073
                 &spr_read_generic, &spr_write_generic,
1074
                 0x00000000);
1075
    spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
1076
                 SPR_NOACCESS, SPR_NOACCESS,
1077
                 &spr_read_generic, &spr_write_generic,
1078
                 0x00000000);
1079
    spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
1080
                 SPR_NOACCESS, SPR_NOACCESS,
1081
                 &spr_read_generic, &spr_write_generic,
1082
                 0x00000000);
1083
    spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
1084
                 SPR_NOACCESS, SPR_NOACCESS,
1085
                 &spr_read_generic, &spr_write_generic,
1086
                 0x00000000);
1087
    /* Debug */
1088
    /* XXX : not implemented */
1089
    spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1090
                 SPR_NOACCESS, SPR_NOACCESS,
1091
                 &spr_read_generic, &spr_write_generic,
1092
                 0x00000000);
1093
    /* XXX : not implemented */
1094
    spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1095
                 SPR_NOACCESS, SPR_NOACCESS,
1096
                 &spr_read_generic, &spr_write_generic,
1097
                 0x00000000);
1098
    /* XXX : not implemented */
1099
    spr_register(env, SPR_BOOKE_IAC3, "IAC3",
1100
                 SPR_NOACCESS, SPR_NOACCESS,
1101
                 &spr_read_generic, &spr_write_generic,
1102
                 0x00000000);
1103
    /* XXX : not implemented */
1104
    spr_register(env, SPR_BOOKE_IAC4, "IAC4",
1105
                 SPR_NOACCESS, SPR_NOACCESS,
1106
                 &spr_read_generic, &spr_write_generic,
1107
                 0x00000000);
1108
    /* XXX : not implemented */
1109
    spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1110
                 SPR_NOACCESS, SPR_NOACCESS,
1111
                 &spr_read_generic, &spr_write_generic,
1112
                 0x00000000);
1113
    /* XXX : not implemented */
1114
    spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1115
                 SPR_NOACCESS, SPR_NOACCESS,
1116
                 &spr_read_generic, &spr_write_generic,
1117
                 0x00000000);
1118
    /* XXX : not implemented */
1119
    spr_register(env, SPR_BOOKE_DVC1, "DVC1",
1120
                 SPR_NOACCESS, SPR_NOACCESS,
1121
                 &spr_read_generic, &spr_write_generic,
1122
                 0x00000000);
1123
    /* XXX : not implemented */
1124
    spr_register(env, SPR_BOOKE_DVC2, "DVC2",
1125
                 SPR_NOACCESS, SPR_NOACCESS,
1126
                 &spr_read_generic, &spr_write_generic,
1127
                 0x00000000);
1128
    /* XXX : not implemented */
1129
    spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1130
                 SPR_NOACCESS, SPR_NOACCESS,
1131
                 &spr_read_generic, &spr_write_generic,
1132
                 0x00000000);
1133
    /* XXX : not implemented */
1134
    spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1135
                 SPR_NOACCESS, SPR_NOACCESS,
1136
                 &spr_read_generic, &spr_write_generic,
1137
                 0x00000000);
1138
    /* XXX : not implemented */
1139
    spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1140
                 SPR_NOACCESS, SPR_NOACCESS,
1141
                 &spr_read_generic, &spr_write_generic,
1142
                 0x00000000);
1143
    /* XXX : not implemented */
1144
    spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1145
                 SPR_NOACCESS, SPR_NOACCESS,
1146
                 &spr_read_generic, &spr_write_generic,
1147
                 0x00000000);
1148
    spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1149
                 SPR_NOACCESS, SPR_NOACCESS,
1150
                 &spr_read_generic, &spr_write_generic,
1151
                 0x00000000);
1152
    spr_register(env, SPR_BOOKE_ESR, "ESR",
1153
                 SPR_NOACCESS, SPR_NOACCESS,
1154
                 &spr_read_generic, &spr_write_generic,
1155
                 0x00000000);
1156
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1157
                 SPR_NOACCESS, SPR_NOACCESS,
1158
                 &spr_read_generic, &spr_write_generic,
1159
                 0x00000000);
1160
    /* Exception vectors */
1161
    spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1162
                 SPR_NOACCESS, SPR_NOACCESS,
1163
                 &spr_read_generic, &spr_write_generic,
1164
                 0x00000000);
1165
    spr_register(env, SPR_BOOKE_IVOR0, "IVOR0",
1166
                 SPR_NOACCESS, SPR_NOACCESS,
1167
                 &spr_read_generic, &spr_write_generic,
1168
                 0x00000000);
1169
    spr_register(env, SPR_BOOKE_IVOR1, "IVOR1",
1170
                 SPR_NOACCESS, SPR_NOACCESS,
1171
                 &spr_read_generic, &spr_write_generic,
1172
                 0x00000000);
1173
    spr_register(env, SPR_BOOKE_IVOR2, "IVOR2",
1174
                 SPR_NOACCESS, SPR_NOACCESS,
1175
                 &spr_read_generic, &spr_write_generic,
1176
                 0x00000000);
1177
    spr_register(env, SPR_BOOKE_IVOR3, "IVOR3",
1178
                 SPR_NOACCESS, SPR_NOACCESS,
1179
                 &spr_read_generic, &spr_write_generic,
1180
                 0x00000000);
1181
    spr_register(env, SPR_BOOKE_IVOR4, "IVOR4",
1182
                 SPR_NOACCESS, SPR_NOACCESS,
1183
                 &spr_read_generic, &spr_write_generic,
1184
                 0x00000000);
1185
    spr_register(env, SPR_BOOKE_IVOR5, "IVOR5",
1186
                 SPR_NOACCESS, SPR_NOACCESS,
1187
                 &spr_read_generic, &spr_write_generic,
1188
                 0x00000000);
1189
    spr_register(env, SPR_BOOKE_IVOR6, "IVOR6",
1190
                 SPR_NOACCESS, SPR_NOACCESS,
1191
                 &spr_read_generic, &spr_write_generic,
1192
                 0x00000000);
1193
    spr_register(env, SPR_BOOKE_IVOR7, "IVOR7",
1194
                 SPR_NOACCESS, SPR_NOACCESS,
1195
                 &spr_read_generic, &spr_write_generic,
1196
                 0x00000000);
1197
    spr_register(env, SPR_BOOKE_IVOR8, "IVOR8",
1198
                 SPR_NOACCESS, SPR_NOACCESS,
1199
                 &spr_read_generic, &spr_write_generic,
1200
                 0x00000000);
1201
    spr_register(env, SPR_BOOKE_IVOR9, "IVOR9",
1202
                 SPR_NOACCESS, SPR_NOACCESS,
1203
                 &spr_read_generic, &spr_write_generic,
1204
                 0x00000000);
1205
    spr_register(env, SPR_BOOKE_IVOR10, "IVOR10",
1206
                 SPR_NOACCESS, SPR_NOACCESS,
1207
                 &spr_read_generic, &spr_write_generic,
1208
                 0x00000000);
1209
    spr_register(env, SPR_BOOKE_IVOR11, "IVOR11",
1210
                 SPR_NOACCESS, SPR_NOACCESS,
1211
                 &spr_read_generic, &spr_write_generic,
1212
                 0x00000000);
1213
    spr_register(env, SPR_BOOKE_IVOR12, "IVOR12",
1214
                 SPR_NOACCESS, SPR_NOACCESS,
1215
                 &spr_read_generic, &spr_write_generic,
1216
                 0x00000000);
1217
    spr_register(env, SPR_BOOKE_IVOR13, "IVOR13",
1218
                 SPR_NOACCESS, SPR_NOACCESS,
1219
                 &spr_read_generic, &spr_write_generic,
1220
                 0x00000000);
1221
    spr_register(env, SPR_BOOKE_IVOR14, "IVOR14",
1222
                 SPR_NOACCESS, SPR_NOACCESS,
1223
                 &spr_read_generic, &spr_write_generic,
1224
                 0x00000000);
1225
    spr_register(env, SPR_BOOKE_IVOR15, "IVOR15",
1226
                 SPR_NOACCESS, SPR_NOACCESS,
1227
                 &spr_read_generic, &spr_write_generic,
1228
                 0x00000000);
1229
    spr_register(env, SPR_BOOKE_IVOR32, "IVOR32",
1230
                 SPR_NOACCESS, SPR_NOACCESS,
1231
                 &spr_read_generic, &spr_write_generic,
1232
                 0x00000000);
1233
    spr_register(env, SPR_BOOKE_IVOR33, "IVOR33",
1234
                 SPR_NOACCESS, SPR_NOACCESS,
1235
                 &spr_read_generic, &spr_write_generic,
1236
                 0x00000000);
1237
    spr_register(env, SPR_BOOKE_IVOR34, "IVOR34",
1238
                 SPR_NOACCESS, SPR_NOACCESS,
1239
                 &spr_read_generic, &spr_write_generic,
1240
                 0x00000000);
1241
    spr_register(env, SPR_BOOKE_IVOR35, "IVOR35",
1242
                 SPR_NOACCESS, SPR_NOACCESS,
1243
                 &spr_read_generic, &spr_write_generic,
1244
                 0x00000000);
1245
    spr_register(env, SPR_BOOKE_IVOR36, "IVOR36",
1246
                 SPR_NOACCESS, SPR_NOACCESS,
1247
                 &spr_read_generic, &spr_write_generic,
1248
                 0x00000000);
1249
    spr_register(env, SPR_BOOKE_IVOR37, "IVOR37",
1250
                 SPR_NOACCESS, SPR_NOACCESS,
1251
                 &spr_read_generic, &spr_write_generic,
1252
                 0x00000000);
1253
    spr_register(env, SPR_BOOKE_PID, "PID",
1254
                 SPR_NOACCESS, SPR_NOACCESS,
1255
                 &spr_read_generic, &spr_write_generic,
1256
                 0x00000000);
1257
    spr_register(env, SPR_BOOKE_TCR, "TCR",
1258
                 SPR_NOACCESS, SPR_NOACCESS,
1259
                 &spr_read_generic, &spr_write_booke_tcr,
1260
                 0x00000000);
1261
    spr_register(env, SPR_BOOKE_TSR, "TSR",
1262
                 SPR_NOACCESS, SPR_NOACCESS,
1263
                 &spr_read_generic, &spr_write_booke_tsr,
1264
                 0x00000000);
1265
    /* Timer */
1266
    spr_register(env, SPR_DECR, "DECR",
1267
                 SPR_NOACCESS, SPR_NOACCESS,
1268
                 &spr_read_decr, &spr_write_decr,
1269
                 0x00000000);
1270
    spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1271
                 SPR_NOACCESS, SPR_NOACCESS,
1272
                 SPR_NOACCESS, &spr_write_generic,
1273
                 0x00000000);
1274
    /* SPRGs */
1275
    spr_register(env, SPR_USPRG0, "USPRG0",
1276
                 &spr_read_generic, &spr_write_generic,
1277
                 &spr_read_generic, &spr_write_generic,
1278
                 0x00000000);
1279
    spr_register(env, SPR_SPRG4, "SPRG4",
1280
                 SPR_NOACCESS, SPR_NOACCESS,
1281
                 &spr_read_generic, &spr_write_generic,
1282
                 0x00000000);
1283
    spr_register(env, SPR_USPRG4, "USPRG4",
1284
                 &spr_read_ureg, SPR_NOACCESS,
1285
                 &spr_read_ureg, SPR_NOACCESS,
1286
                 0x00000000);
1287
    spr_register(env, SPR_SPRG5, "SPRG5",
1288
                 SPR_NOACCESS, SPR_NOACCESS,
1289
                 &spr_read_generic, &spr_write_generic,
1290
                 0x00000000);
1291
    spr_register(env, SPR_USPRG5, "USPRG5",
1292
                 &spr_read_ureg, SPR_NOACCESS,
1293
                 &spr_read_ureg, SPR_NOACCESS,
1294
                 0x00000000);
1295
    spr_register(env, SPR_SPRG6, "SPRG6",
1296
                 SPR_NOACCESS, SPR_NOACCESS,
1297
                 &spr_read_generic, &spr_write_generic,
1298
                 0x00000000);
1299
    spr_register(env, SPR_USPRG6, "USPRG6",
1300
                 &spr_read_ureg, SPR_NOACCESS,
1301
                 &spr_read_ureg, SPR_NOACCESS,
1302
                 0x00000000);
1303
    spr_register(env, SPR_SPRG7, "SPRG7",
1304
                 SPR_NOACCESS, SPR_NOACCESS,
1305
                 &spr_read_generic, &spr_write_generic,
1306
                 0x00000000);
1307
    spr_register(env, SPR_USPRG7, "USPRG7",
1308
                 &spr_read_ureg, SPR_NOACCESS,
1309
                 &spr_read_ureg, SPR_NOACCESS,
1310
                 0x00000000);
1311
}
1312

    
1313
/* FSL storage control registers */
1314
static void gen_spr_BookE_FSL (CPUPPCState *env)
1315
{
1316
    /* TLB assist registers */
1317
    spr_register(env, SPR_BOOKE_MAS0, "MAS0",
1318
                 SPR_NOACCESS, SPR_NOACCESS,
1319
                 &spr_read_generic, &spr_write_generic,
1320
                 0x00000000);
1321
    spr_register(env, SPR_BOOKE_MAS1, "MAS2",
1322
                 SPR_NOACCESS, SPR_NOACCESS,
1323
                 &spr_read_generic, &spr_write_generic,
1324
                 0x00000000);
1325
    spr_register(env, SPR_BOOKE_MAS2, "MAS3",
1326
                 SPR_NOACCESS, SPR_NOACCESS,
1327
                 &spr_read_generic, &spr_write_generic,
1328
                 0x00000000);
1329
    spr_register(env, SPR_BOOKE_MAS3, "MAS4",
1330
                 SPR_NOACCESS, SPR_NOACCESS,
1331
                 &spr_read_generic, &spr_write_generic,
1332
                 0x00000000);
1333
    spr_register(env, SPR_BOOKE_MAS4, "MAS5",
1334
                 SPR_NOACCESS, SPR_NOACCESS,
1335
                 &spr_read_generic, &spr_write_generic,
1336
                 0x00000000);
1337
    spr_register(env, SPR_BOOKE_MAS6, "MAS6",
1338
                 SPR_NOACCESS, SPR_NOACCESS,
1339
                 &spr_read_generic, &spr_write_generic,
1340
                 0x00000000);
1341
    spr_register(env, SPR_BOOKE_MAS7, "MAS7",
1342
                 SPR_NOACCESS, SPR_NOACCESS,
1343
                 &spr_read_generic, &spr_write_generic,
1344
                 0x00000000);
1345
    if (env->nb_pids > 1) {
1346
        spr_register(env, SPR_BOOKE_PID1, "PID1",
1347
                     SPR_NOACCESS, SPR_NOACCESS,
1348
                     &spr_read_generic, &spr_write_generic,
1349
                     0x00000000);
1350
    }
1351
    if (env->nb_pids > 2) {
1352
        spr_register(env, SPR_BOOKE_PID2, "PID2",
1353
                     SPR_NOACCESS, SPR_NOACCESS,
1354
                     &spr_read_generic, &spr_write_generic,
1355
                     0x00000000);
1356
    }
1357
    spr_register(env, SPR_BOOKE_MMUCFG, "MMUCFG",
1358
                 SPR_NOACCESS, SPR_NOACCESS,
1359
                 &spr_read_generic, SPR_NOACCESS,
1360
                 0x00000000); /* TOFIX */
1361
    spr_register(env, SPR_BOOKE_MMUCSR0, "MMUCSR0",
1362
                 SPR_NOACCESS, SPR_NOACCESS,
1363
                 &spr_read_generic, &spr_write_generic,
1364
                 0x00000000); /* TOFIX */
1365
    switch (env->nb_ways) {
1366
    case 4:
1367
        spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1368
                     SPR_NOACCESS, SPR_NOACCESS,
1369
                     &spr_read_generic, SPR_NOACCESS,
1370
                     0x00000000); /* TOFIX */
1371
        /* Fallthru */
1372
    case 3:
1373
        spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1374
                     SPR_NOACCESS, SPR_NOACCESS,
1375
                     &spr_read_generic, SPR_NOACCESS,
1376
                     0x00000000); /* TOFIX */
1377
        /* Fallthru */
1378
    case 2:
1379
        spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1380
                     SPR_NOACCESS, SPR_NOACCESS,
1381
                     &spr_read_generic, SPR_NOACCESS,
1382
                     0x00000000); /* TOFIX */
1383
        /* Fallthru */
1384
    case 1:
1385
        spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1386
                     SPR_NOACCESS, SPR_NOACCESS,
1387
                     &spr_read_generic, SPR_NOACCESS,
1388
                     0x00000000); /* TOFIX */
1389
        /* Fallthru */
1390
    case 0:
1391
    default:
1392
        break;
1393
    }
1394
}
1395

    
1396
/* SPR specific to PowerPC 440 implementation */
1397
static void gen_spr_440 (CPUPPCState *env)
1398
{
1399
    /* Cache control */
1400
    /* XXX : not implemented */
1401
    spr_register(env, SPR_440_DNV0, "DNV0",
1402
                 SPR_NOACCESS, SPR_NOACCESS,
1403
                 &spr_read_generic, &spr_write_generic,
1404
                 0x00000000);
1405
    /* XXX : not implemented */
1406
    spr_register(env, SPR_440_DNV1, "DNV1",
1407
                 SPR_NOACCESS, SPR_NOACCESS,
1408
                 &spr_read_generic, &spr_write_generic,
1409
                 0x00000000);
1410
    /* XXX : not implemented */
1411
    spr_register(env, SPR_440_DNV2, "DNV2",
1412
                 SPR_NOACCESS, SPR_NOACCESS,
1413
                 &spr_read_generic, &spr_write_generic,
1414
                 0x00000000);
1415
    /* XXX : not implemented */
1416
    spr_register(env, SPR_440_DNV3, "DNV3",
1417
                 SPR_NOACCESS, SPR_NOACCESS,
1418
                 &spr_read_generic, &spr_write_generic,
1419
                 0x00000000);
1420
    /* XXX : not implemented */
1421
    spr_register(env, SPR_440_DVT0, "DVT0",
1422
                 SPR_NOACCESS, SPR_NOACCESS,
1423
                 &spr_read_generic, &spr_write_generic,
1424
                 0x00000000);
1425
    /* XXX : not implemented */
1426
    spr_register(env, SPR_440_DVT1, "DVT1",
1427
                 SPR_NOACCESS, SPR_NOACCESS,
1428
                 &spr_read_generic, &spr_write_generic,
1429
                 0x00000000);
1430
    /* XXX : not implemented */
1431
    spr_register(env, SPR_440_DVT2, "DVT2",
1432
                 SPR_NOACCESS, SPR_NOACCESS,
1433
                 &spr_read_generic, &spr_write_generic,
1434
                 0x00000000);
1435
    /* XXX : not implemented */
1436
    spr_register(env, SPR_440_DVT3, "DVT3",
1437
                 SPR_NOACCESS, SPR_NOACCESS,
1438
                 &spr_read_generic, &spr_write_generic,
1439
                 0x00000000);
1440
    /* XXX : not implemented */
1441
    spr_register(env, SPR_440_DVLIM, "DVLIM",
1442
                 SPR_NOACCESS, SPR_NOACCESS,
1443
                 &spr_read_generic, &spr_write_generic,
1444
                 0x00000000);
1445
    /* XXX : not implemented */
1446
    spr_register(env, SPR_440_INV0, "INV0",
1447
                 SPR_NOACCESS, SPR_NOACCESS,
1448
                 &spr_read_generic, &spr_write_generic,
1449
                 0x00000000);
1450
    /* XXX : not implemented */
1451
    spr_register(env, SPR_440_INV1, "INV1",
1452
                 SPR_NOACCESS, SPR_NOACCESS,
1453
                 &spr_read_generic, &spr_write_generic,
1454
                 0x00000000);
1455
    /* XXX : not implemented */
1456
    spr_register(env, SPR_440_INV2, "INV2",
1457
                 SPR_NOACCESS, SPR_NOACCESS,
1458
                 &spr_read_generic, &spr_write_generic,
1459
                 0x00000000);
1460
    /* XXX : not implemented */
1461
    spr_register(env, SPR_440_INV3, "INV3",
1462
                 SPR_NOACCESS, SPR_NOACCESS,
1463
                 &spr_read_generic, &spr_write_generic,
1464
                 0x00000000);
1465
    /* XXX : not implemented */
1466
    spr_register(env, SPR_440_IVT0, "IVT0",
1467
                 SPR_NOACCESS, SPR_NOACCESS,
1468
                 &spr_read_generic, &spr_write_generic,
1469
                 0x00000000);
1470
    /* XXX : not implemented */
1471
    spr_register(env, SPR_440_IVT1, "IVT1",
1472
                 SPR_NOACCESS, SPR_NOACCESS,
1473
                 &spr_read_generic, &spr_write_generic,
1474
                 0x00000000);
1475
    /* XXX : not implemented */
1476
    spr_register(env, SPR_440_IVT2, "IVT2",
1477
                 SPR_NOACCESS, SPR_NOACCESS,
1478
                 &spr_read_generic, &spr_write_generic,
1479
                 0x00000000);
1480
    /* XXX : not implemented */
1481
    spr_register(env, SPR_440_IVT3, "IVT3",
1482
                 SPR_NOACCESS, SPR_NOACCESS,
1483
                 &spr_read_generic, &spr_write_generic,
1484
                 0x00000000);
1485
    /* XXX : not implemented */
1486
    spr_register(env, SPR_440_IVLIM, "IVLIM",
1487
                 SPR_NOACCESS, SPR_NOACCESS,
1488
                 &spr_read_generic, &spr_write_generic,
1489
                 0x00000000);
1490
    /* Cache debug */
1491
    /* XXX : not implemented */
1492
    spr_register(env, SPR_BOOKE_DCBTRH, "DCBTRH",
1493
                 SPR_NOACCESS, SPR_NOACCESS,
1494
                 &spr_read_generic, SPR_NOACCESS,
1495
                 0x00000000);
1496
    /* XXX : not implemented */
1497
    spr_register(env, SPR_BOOKE_DCBTRL, "DCBTRL",
1498
                 SPR_NOACCESS, SPR_NOACCESS,
1499
                 &spr_read_generic, SPR_NOACCESS,
1500
                 0x00000000);
1501
    /* XXX : not implemented */
1502
    spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1503
                 SPR_NOACCESS, SPR_NOACCESS,
1504
                 &spr_read_generic, SPR_NOACCESS,
1505
                 0x00000000);
1506
    /* XXX : not implemented */
1507
    spr_register(env, SPR_BOOKE_ICBTRH, "ICBTRH",
1508
                 SPR_NOACCESS, SPR_NOACCESS,
1509
                 &spr_read_generic, SPR_NOACCESS,
1510
                 0x00000000);
1511
    /* XXX : not implemented */
1512
    spr_register(env, SPR_BOOKE_ICBTRL, "ICBTRL",
1513
                 SPR_NOACCESS, SPR_NOACCESS,
1514
                 &spr_read_generic, SPR_NOACCESS,
1515
                 0x00000000);
1516
    /* XXX : not implemented */
1517
    spr_register(env, SPR_440_DBDR, "DBDR",
1518
                 SPR_NOACCESS, SPR_NOACCESS,
1519
                 &spr_read_generic, &spr_write_generic,
1520
                 0x00000000);
1521
    /* Processor control */
1522
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1523
                 SPR_NOACCESS, SPR_NOACCESS,
1524
                 &spr_read_generic, &spr_write_generic,
1525
                 0x00000000);
1526
    spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1527
                 SPR_NOACCESS, SPR_NOACCESS,
1528
                 &spr_read_generic, SPR_NOACCESS,
1529
                 0x00000000);
1530
    /* Storage control */
1531
    spr_register(env, SPR_440_MMUCR, "MMUCR",
1532
                 SPR_NOACCESS, SPR_NOACCESS,
1533
                 &spr_read_generic, &spr_write_generic,
1534
                 0x00000000);
1535
}
1536

    
1537
/* SPR shared between PowerPC 40x implementations */
1538
static void gen_spr_40x (CPUPPCState *env)
1539
{
1540
    /* Cache */
1541
    /* XXX : not implemented */
1542
    spr_register(env, SPR_40x_DCCR, "DCCR",
1543
                 SPR_NOACCESS, SPR_NOACCESS,
1544
                 &spr_read_generic, &spr_write_generic,
1545
                 0x00000000);
1546
    /* XXX : not implemented */
1547
    spr_register(env, SPR_40x_DCWR, "DCWR",
1548
                 SPR_NOACCESS, SPR_NOACCESS,
1549
                 &spr_read_generic, &spr_write_generic,
1550
                 0x00000000);
1551
    /* XXX : not implemented */
1552
    spr_register(env, SPR_40x_ICCR, "ICCR",
1553
                 SPR_NOACCESS, SPR_NOACCESS,
1554
                 &spr_read_generic, &spr_write_generic,
1555
                 0x00000000);
1556
    /* XXX : not implemented */
1557
    spr_register(env, SPR_BOOKE_ICBDR, "ICBDR",
1558
                 SPR_NOACCESS, SPR_NOACCESS,
1559
                 &spr_read_generic, SPR_NOACCESS,
1560
                 0x00000000);
1561
    /* Bus access control */
1562
    spr_register(env, SPR_40x_SGR, "SGR",
1563
                 SPR_NOACCESS, SPR_NOACCESS,
1564
                 &spr_read_generic, &spr_write_generic,
1565
                 0xFFFFFFFF);
1566
    spr_register(env, SPR_40x_ZPR, "ZPR",
1567
                 SPR_NOACCESS, SPR_NOACCESS,
1568
                 &spr_read_generic, &spr_write_generic,
1569
                 0x00000000);
1570
    /* MMU */
1571
    spr_register(env, SPR_40x_PID, "PID",
1572
                 SPR_NOACCESS, SPR_NOACCESS,
1573
                 &spr_read_generic, &spr_write_generic,
1574
                 0x00000000);
1575
    /* Exception */
1576
    spr_register(env, SPR_40x_DEAR, "DEAR",
1577
                 SPR_NOACCESS, SPR_NOACCESS,
1578
                 &spr_read_generic, &spr_write_generic,
1579
                 0x00000000);
1580
    spr_register(env, SPR_40x_ESR, "ESR",
1581
                 SPR_NOACCESS, SPR_NOACCESS,
1582
                 &spr_read_generic, &spr_write_generic,
1583
                 0x00000000);
1584
    spr_register(env, SPR_40x_EVPR, "EVPR",
1585
                 SPR_NOACCESS, SPR_NOACCESS,
1586
                 &spr_read_generic, &spr_write_generic,
1587
                 0x00000000);
1588
    spr_register(env, SPR_40x_SRR2, "SRR2",
1589
                 &spr_read_generic, &spr_write_generic,
1590
                 &spr_read_generic, &spr_write_generic,
1591
                 0x00000000);
1592
    spr_register(env, SPR_40x_SRR3, "SRR3",
1593
                 &spr_read_generic, &spr_write_generic,
1594
                 &spr_read_generic, &spr_write_generic,
1595
                 0x00000000);
1596
    /* Timers */
1597
    spr_register(env, SPR_40x_PIT, "PIT",
1598
                 SPR_NOACCESS, SPR_NOACCESS,
1599
                 &spr_read_40x_pit, &spr_write_40x_pit,
1600
                 0x00000000);
1601
    spr_register(env, SPR_40x_TCR, "TCR",
1602
                 SPR_NOACCESS, SPR_NOACCESS,
1603
                 &spr_read_generic, &spr_write_booke_tcr,
1604
                 0x00000000);
1605
    spr_register(env, SPR_40x_TSR, "TSR",
1606
                 SPR_NOACCESS, SPR_NOACCESS,
1607
                 &spr_read_generic, &spr_write_booke_tsr,
1608
                 0x00000000);
1609
    /* Debug interface */
1610
    /* XXX : not implemented */
1611
    spr_register(env, SPR_40x_DAC1, "DAC1",
1612
                 SPR_NOACCESS, SPR_NOACCESS,
1613
                 &spr_read_generic, &spr_write_generic,
1614
                 0x00000000);
1615
    spr_register(env, SPR_40x_DAC2, "DAC2",
1616
                 SPR_NOACCESS, SPR_NOACCESS,
1617
                 &spr_read_generic, &spr_write_generic,
1618
                 0x00000000);
1619
    /* XXX : not implemented */
1620
    spr_register(env, SPR_40x_DBCR0, "DBCR0",
1621
                 SPR_NOACCESS, SPR_NOACCESS,
1622
                 &spr_read_generic, &spr_write_generic,
1623
                 0x00000000);
1624
    /* XXX : not implemented */
1625
    spr_register(env, SPR_40x_DBSR, "DBSR",
1626
                 SPR_NOACCESS, SPR_NOACCESS,
1627
                 &spr_read_generic, &spr_write_generic,
1628
                 /* Last reset was system reset (system boot */
1629
                 0x00000300);
1630
    /* XXX : not implemented */
1631
    spr_register(env, SPR_40x_IAC1, "IAC1",
1632
                 SPR_NOACCESS, SPR_NOACCESS,
1633
                 &spr_read_generic, &spr_write_generic,
1634
                 0x00000000);
1635
    spr_register(env, SPR_40x_IAC2, "IAC2",
1636
                 SPR_NOACCESS, SPR_NOACCESS,
1637
                 &spr_read_generic, &spr_write_generic,
1638
                 0x00000000);
1639
}
1640

    
1641
/* SPR specific to PowerPC 405 implementation */
1642
static void gen_spr_405 (CPUPPCState *env)
1643
{
1644
    spr_register(env, SPR_4xx_CCR0, "CCR0",
1645
                 SPR_NOACCESS, SPR_NOACCESS,
1646
                 &spr_read_generic, &spr_write_generic,
1647
                 0x00700000);
1648
    /* Debug */
1649
    /* XXX : not implemented */
1650
    spr_register(env, SPR_405_DBCR1, "DBCR1",
1651
                 SPR_NOACCESS, SPR_NOACCESS,
1652
                 &spr_read_generic, &spr_write_generic,
1653
                 0x00000000);
1654
    /* XXX : not implemented */
1655
    spr_register(env, SPR_405_DVC1, "DVC1",
1656
                 SPR_NOACCESS, SPR_NOACCESS,
1657
                 &spr_read_generic, &spr_write_generic,
1658
                 0x00000000);
1659
    /* XXX : not implemented */
1660
    spr_register(env, SPR_405_DVC2, "DVC2",
1661
                 SPR_NOACCESS, SPR_NOACCESS,
1662
                 &spr_read_generic, &spr_write_generic,
1663
                 0x00000000);
1664
    /* XXX : not implemented */
1665
    spr_register(env, SPR_405_IAC3, "IAC3",
1666
                 SPR_NOACCESS, SPR_NOACCESS,
1667
                 &spr_read_generic, &spr_write_generic,
1668
                 0x00000000);
1669
    /* XXX : not implemented */
1670
    spr_register(env, SPR_405_IAC4, "IAC4",
1671
                 SPR_NOACCESS, SPR_NOACCESS,
1672
                 &spr_read_generic, &spr_write_generic,
1673
                 0x00000000);
1674
    /* Storage control */
1675
    /* XXX : not implemented */
1676
    spr_register(env, SPR_405_SLER, "SLER",
1677
                 SPR_NOACCESS, SPR_NOACCESS,
1678
                 &spr_read_generic, &spr_write_generic,
1679
                 0x00000000);
1680
    /* XXX : not implemented */
1681
    spr_register(env, SPR_405_SU0R, "SU0R",
1682
                 SPR_NOACCESS, SPR_NOACCESS,
1683
                 &spr_read_generic, &spr_write_generic,
1684
                 0x00000000);
1685
    /* SPRG */
1686
    spr_register(env, SPR_USPRG0, "USPRG0",
1687
                 &spr_read_ureg, SPR_NOACCESS,
1688
                 &spr_read_ureg, SPR_NOACCESS,
1689
                 0x00000000);
1690
    spr_register(env, SPR_SPRG4, "SPRG4",
1691
                 SPR_NOACCESS, SPR_NOACCESS,
1692
                 SPR_NOACCESS, &spr_write_generic,
1693
                 0x00000000);
1694
    spr_register(env, SPR_USPRG4, "USPRG4",
1695
                 &spr_read_ureg, SPR_NOACCESS,
1696
                 &spr_read_ureg, SPR_NOACCESS,
1697
                 0x00000000);
1698
    spr_register(env, SPR_SPRG5, "SPRG5",
1699
                 SPR_NOACCESS, SPR_NOACCESS,
1700
                 SPR_NOACCESS, &spr_write_generic,
1701
                 0x00000000);
1702
    spr_register(env, SPR_USPRG5, "USPRG5",
1703
                 &spr_read_ureg, SPR_NOACCESS,
1704
                 &spr_read_ureg, SPR_NOACCESS,
1705
                 0x00000000);
1706
    spr_register(env, SPR_SPRG6, "SPRG6",
1707
                 SPR_NOACCESS, SPR_NOACCESS,
1708
                 SPR_NOACCESS, &spr_write_generic,
1709
                 0x00000000);
1710
    spr_register(env, SPR_USPRG6, "USPRG6",
1711
                 &spr_read_ureg, SPR_NOACCESS,
1712
                 &spr_read_ureg, SPR_NOACCESS,
1713
                 0x00000000);
1714
    spr_register(env, SPR_SPRG7, "SPRG7",
1715
                 SPR_NOACCESS, SPR_NOACCESS,
1716
                 SPR_NOACCESS, &spr_write_generic,
1717
                 0x00000000);
1718
    spr_register(env, SPR_USPRG7, "USPRG7",
1719
                 &spr_read_ureg, SPR_NOACCESS,
1720
                 &spr_read_ureg, SPR_NOACCESS,
1721
                 0x00000000);
1722
    /* Debug */
1723
    /* XXX : not implemented */
1724
    spr_register(env, SPR_40x_DAC2, "DAC2",
1725
                 SPR_NOACCESS, SPR_NOACCESS,
1726
                 &spr_read_generic, &spr_write_generic,
1727
                 0x00000000);
1728
    /* XXX : not implemented */
1729
    spr_register(env, SPR_40x_IAC2, "IAC2",
1730
                 SPR_NOACCESS, SPR_NOACCESS,
1731
                 &spr_read_generic, &spr_write_generic,
1732
                 0x00000000);
1733
}
1734

    
1735
/* SPR shared between PowerPC 401 & 403 implementations */
1736
static void gen_spr_401_403 (CPUPPCState *env)
1737
{
1738
    /* Time base */
1739
    spr_register(env, SPR_403_VTBL,  "TBL",
1740
                 &spr_read_tbl, SPR_NOACCESS,
1741
                 &spr_read_tbl, SPR_NOACCESS,
1742
                 0x00000000);
1743
    spr_register(env, SPR_403_TBL,   "TBL",
1744
                 SPR_NOACCESS, SPR_NOACCESS,
1745
                 SPR_NOACCESS, &spr_write_tbl,
1746
                 0x00000000);
1747
    spr_register(env, SPR_403_VTBU,  "TBU",
1748
                 &spr_read_tbu, SPR_NOACCESS,
1749
                 &spr_read_tbu, SPR_NOACCESS,
1750
                 0x00000000);
1751
    spr_register(env, SPR_403_TBU,   "TBU",
1752
                 SPR_NOACCESS, SPR_NOACCESS,
1753
                 SPR_NOACCESS, &spr_write_tbu,
1754
                 0x00000000);
1755
    /* Debug */
1756
    /* XXX: not implemented */
1757
    spr_register(env, SPR_403_CDBCR, "CDBCR",
1758
                 SPR_NOACCESS, SPR_NOACCESS,
1759
                 &spr_read_generic, &spr_write_generic,
1760
                 0x00000000);
1761
}
1762

    
1763
/* SPR specific to PowerPC 403 implementation */
1764
static void gen_spr_403 (CPUPPCState *env)
1765
{
1766
    /* MMU */
1767
    spr_register(env, SPR_403_PBL1,  "PBL1",
1768
                 SPR_NOACCESS, SPR_NOACCESS,
1769
                 &spr_read_403_pbr, &spr_write_403_pbr,
1770
                 0x00000000);
1771
    spr_register(env, SPR_403_PBU1,  "PBU1",
1772
                 SPR_NOACCESS, SPR_NOACCESS,
1773
                 &spr_read_403_pbr, &spr_write_403_pbr,
1774
                 0x00000000);
1775
    spr_register(env, SPR_403_PBL2,  "PBL2",
1776
                 SPR_NOACCESS, SPR_NOACCESS,
1777
                 &spr_read_403_pbr, &spr_write_403_pbr,
1778
                 0x00000000);
1779
    spr_register(env, SPR_403_PBU2,  "PBU2",
1780
                 SPR_NOACCESS, SPR_NOACCESS,
1781
                 &spr_read_403_pbr, &spr_write_403_pbr,
1782
                 0x00000000);
1783
    /* Debug */
1784
    /* XXX : not implemented */
1785
    spr_register(env, SPR_40x_DAC2, "DAC2",
1786
                 SPR_NOACCESS, SPR_NOACCESS,
1787
                 &spr_read_generic, &spr_write_generic,
1788
                 0x00000000);
1789
    /* XXX : not implemented */
1790
    spr_register(env, SPR_40x_IAC2, "IAC2",
1791
                 SPR_NOACCESS, SPR_NOACCESS,
1792
                 &spr_read_generic, &spr_write_generic,
1793
                 0x00000000);
1794
}
1795

    
1796
/* SPR specific to PowerPC compression coprocessor extension */
1797
#if defined (TODO)
1798
static void gen_spr_compress (CPUPPCState *env)
1799
{
1800
    spr_register(env, SPR_401_SKR, "SKR",
1801
                 SPR_NOACCESS, SPR_NOACCESS,
1802
                 &spr_read_generic, &spr_write_generic,
1803
                 0x00000000);
1804
}
1805
#endif
1806

    
1807
// XXX: TODO (64 bits PowerPC SPRs)
1808
/*
1809
 * ASR => SPR 280 (64 bits)
1810
 * FPECR => SPR 1022 (?)
1811
 * VRSAVE => SPR 256 (Altivec)
1812
 * SCOMC => SPR 276 (64 bits ?)
1813
 * SCOMD => SPR 277 (64 bits ?)
1814
 * HSPRG0 => SPR 304 (hypervisor)
1815
 * HSPRG1 => SPR 305 (hypervisor)
1816
 * HDEC => SPR 310 (hypervisor)
1817
 * HIOR => SPR 311 (hypervisor)
1818
 * RMOR => SPR 312 (970)
1819
 * HRMOR => SPR 313 (hypervisor)
1820
 * HSRR0 => SPR 314 (hypervisor)
1821
 * HSRR1 => SPR 315 (hypervisor)
1822
 * LPCR => SPR 316 (970)
1823
 * LPIDR => SPR 317 (970)
1824
 * ... and more (thermal management, performance counters, ...)
1825
 */
1826

    
1827
static void init_ppc_proc (CPUPPCState *env, ppc_def_t *def)
1828
{
1829
    env->reserve = -1;
1830
    /* Default MMU definitions */
1831
    env->nb_BATs = -1;
1832
    env->nb_tlb = 0;
1833
    env->nb_ways = 0;
1834
    /* XXX: missing:
1835
     * 32 bits PowerPC:
1836
     * - MPC5xx(x)
1837
     * - MPC8xx(x)
1838
     * - RCPU (same as MPC5xx ?)
1839
     */
1840
    spr_register(env, SPR_PVR, "PVR",
1841
                 SPR_NOACCESS, SPR_NOACCESS,
1842
                 &spr_read_generic, SPR_NOACCESS,
1843
                 def->pvr);
1844
    printf("%s: PVR %08x mask %08x => %08x\n", __func__,
1845
           def->pvr, def->pvr_mask, def->pvr & def->pvr_mask);
1846
    switch (def->pvr & def->pvr_mask) {
1847
    /* Embedded PowerPC from IBM                           */
1848
    case CPU_PPC_401A1:   /* 401 A1 family                 */
1849
    case CPU_PPC_401B2:   /* 401 B2 family                 */
1850
    case CPU_PPC_401C2:   /* 401 C2 family                 */
1851
    case CPU_PPC_401D2:   /* 401 D2 family                 */
1852
    case CPU_PPC_401E2:   /* 401 E2 family                 */
1853
    case CPU_PPC_401F2:   /* 401 F2 family                 */
1854
    case CPU_PPC_401G2:   /* 401 G2 family                 */
1855
    case CPU_PPC_IOP480:  /* IOP 480 family                */
1856
    case CPU_PPC_COBRA:   /* IBM Processor for Network Resources */
1857
        gen_spr_generic(env);
1858
        gen_spr_40x(env);
1859
        gen_spr_401_403(env);
1860
#if defined (TODO)
1861
        /* XXX: optional ? */
1862
        gen_spr_compress(env);
1863
#endif
1864
        env->nb_BATs = 0;
1865
        env->nb_tlb = 64;
1866
        env->nb_ways = 1;
1867
        env->id_tlbs = 0;
1868
        break;
1869

    
1870
    case CPU_PPC_403GA:   /* 403 GA family                 */
1871
    case CPU_PPC_403GB:   /* 403 GB family                 */
1872
    case CPU_PPC_403GC:   /* 403 GC family                 */
1873
    case CPU_PPC_403GCX:  /* 403 GCX family                */
1874
        gen_spr_generic(env);
1875
        gen_spr_40x(env);
1876
        gen_spr_401_403(env);
1877
        gen_spr_403(env);
1878
        env->nb_BATs = 0;
1879
        env->nb_tlb = 64;
1880
        env->nb_ways = 1;
1881
        env->id_tlbs = 0;
1882
        break;
1883

    
1884
    case CPU_PPC_405CR:   /* 405 GP/CR family              */
1885
    case CPU_PPC_405EP:   /* 405 EP family                 */
1886
    case CPU_PPC_405GPR:  /* 405 GPR family                */
1887
    case CPU_PPC_405D2:   /* 405 D2 family                 */
1888
    case CPU_PPC_405D4:   /* 405 D4 family                 */
1889
        gen_spr_generic(env);
1890
        /* Time base */
1891
        gen_tbl(env);
1892
        gen_spr_40x(env);
1893
        gen_spr_405(env);
1894
        env->nb_BATs = 0;
1895
        env->nb_tlb = 64;
1896
        env->nb_ways = 1;
1897
        env->id_tlbs = 0;
1898
        break;
1899

    
1900
    case CPU_PPC_NPE405H: /* NPe405 H family               */
1901
    case CPU_PPC_NPE405H2:
1902
    case CPU_PPC_NPE405L: /* Npe405 L family               */
1903
        gen_spr_generic(env);
1904
        /* Time base */
1905
        gen_tbl(env);
1906
        gen_spr_40x(env);
1907
        gen_spr_405(env);
1908
        env->nb_BATs = 0;
1909
        env->nb_tlb = 64;
1910
        env->nb_ways = 1;
1911
        env->id_tlbs = 0;
1912
        break;
1913

    
1914
#if defined (TODO)
1915
    case CPU_PPC_STB01000:
1916
#endif
1917
#if defined (TODO)
1918
    case CPU_PPC_STB01010:
1919
#endif
1920
#if defined (TODO)
1921
    case CPU_PPC_STB0210:
1922
#endif
1923
    case CPU_PPC_STB03:   /* STB03 family                  */
1924
#if defined (TODO)
1925
    case CPU_PPC_STB043:  /* STB043 family                  */
1926
#endif
1927
#if defined (TODO)
1928
    case CPU_PPC_STB045:  /* STB045 family                  */
1929
#endif
1930
    case CPU_PPC_STB25:   /* STB25 family                  */
1931
#if defined (TODO)
1932
    case CPU_PPC_STB130:  /* STB130 family                 */
1933
#endif
1934
        gen_spr_generic(env);
1935
        /* Time base */
1936
        gen_tbl(env);
1937
        gen_spr_40x(env);
1938
        gen_spr_405(env);
1939
        env->nb_BATs = 0;
1940
        env->nb_tlb = 64;
1941
        env->nb_ways = 1;
1942
        env->id_tlbs = 0;
1943
        break;
1944

    
1945
    case CPU_PPC_440EP:   /* 440 EP family                 */
1946
    case CPU_PPC_440GP:   /* 440 GP family                 */
1947
    case CPU_PPC_440GX:   /* 440 GX family                 */
1948
    case CPU_PPC_440GXc:  /* 440 GXc family                */
1949
    case CPU_PPC_440GXf:  /* 440 GXf family                */
1950
    case CPU_PPC_440SP:   /* 440 SP family                 */
1951
    case CPU_PPC_440SP2:
1952
    case CPU_PPC_440SPE:  /* 440 SPE family                */
1953
        gen_spr_generic(env);
1954
        /* Time base */
1955
        gen_tbl(env);
1956
        gen_spr_BookE(env);
1957
        gen_spr_440(env);
1958
        env->nb_BATs = 0;
1959
        env->nb_tlb = 64;
1960
        env->nb_ways = 1;
1961
        env->id_tlbs = 0;
1962
        break;
1963

    
1964
    /* Embedded PowerPC from Freescale                     */
1965
#if defined (TODO)
1966
    case CPU_PPC_5xx:
1967
        break;
1968
#endif
1969
#if defined (TODO)
1970
    case CPU_PPC_8xx:     /* MPC821 / 823 / 850 / 860      */
1971
        break;
1972
#endif
1973
#if defined (TODO)
1974
    case CPU_PPC_82xx_HIP3:    /* MPC8240 / 8260                */
1975
    case CPU_PPC_82xx_HIP4:    /* MPC8240 / 8260                */
1976
        break;
1977
#endif
1978
#if defined (TODO)
1979
    case CPU_PPC_827x:    /* MPC 827x / 828x               */
1980
        break;
1981
#endif
1982

    
1983
    /* XXX: Use MPC8540 PVR to implement a test PowerPC BookE target */
1984
    case CPU_PPC_e500v110:
1985
    case CPU_PPC_e500v120:
1986
    case CPU_PPC_e500v210:
1987
    case CPU_PPC_e500v220:
1988
        gen_spr_generic(env);
1989
        /* Time base */
1990
        gen_tbl(env);
1991
        gen_spr_BookE(env);
1992
        gen_spr_BookE_FSL(env);
1993
        env->nb_BATs = 0;
1994
        env->nb_tlb = 64;
1995
        env->nb_ways = 1;
1996
        env->id_tlbs = 0;
1997
        break;
1998

    
1999
#if defined (TODO)
2000
    case CPU_PPC_e600:
2001
        break;
2002
#endif
2003

    
2004
    /* 32 bits PowerPC                                     */
2005
    case CPU_PPC_601:     /* PowerPC 601                   */
2006
        gen_spr_generic(env);
2007
        gen_spr_ne_601(env);
2008
        gen_spr_601(env);
2009
        /* Hardware implementation registers */
2010
        /* XXX : not implemented */
2011
        spr_register(env, SPR_HID0, "HID0",
2012
                     SPR_NOACCESS, SPR_NOACCESS,
2013
                     &spr_read_generic, &spr_write_generic,
2014
                     0x00000000);
2015
        /* XXX : not implemented */
2016
        spr_register(env, SPR_HID1, "HID1",
2017
                     SPR_NOACCESS, SPR_NOACCESS,
2018
                     &spr_read_generic, &spr_write_generic,
2019
                     0x00000000);
2020
        /* XXX : not implemented */
2021
        spr_register(env, SPR_601_HID2, "HID2",
2022
                     SPR_NOACCESS, SPR_NOACCESS,
2023
                     &spr_read_generic, &spr_write_generic,
2024
                     0x00000000);
2025
        /* XXX : not implemented */
2026
        spr_register(env, SPR_601_HID5, "HID5",
2027
                     SPR_NOACCESS, SPR_NOACCESS,
2028
                     &spr_read_generic, &spr_write_generic,
2029
                     0x00000000);
2030
        /* XXX : not implemented */
2031
#if 0 /* ? */
2032
        spr_register(env, SPR_601_HID15, "HID15",
2033
                     SPR_NOACCESS, SPR_NOACCESS,
2034
                     &spr_read_generic, &spr_write_generic,
2035
                     0x00000000);
2036
#endif
2037
        env->nb_tlb = 64;
2038
        env->nb_ways = 2;
2039
        env->id_tlbs = 0;
2040
        env->id_tlbs = 0;
2041
        break;
2042

    
2043
    case CPU_PPC_602:     /* PowerPC 602                   */
2044
        gen_spr_generic(env);
2045
        gen_spr_ne_601(env);
2046
        /* Memory management */
2047
        gen_low_BATs(env);
2048
        /* Time base */
2049
        gen_tbl(env);
2050
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2051
        gen_spr_602(env);
2052
        /* hardware implementation registers */
2053
        /* XXX : not implemented */
2054
        spr_register(env, SPR_HID0, "HID0",
2055
                     SPR_NOACCESS, SPR_NOACCESS,
2056
                     &spr_read_generic, &spr_write_generic,
2057
                     0x00000000);
2058
        /* XXX : not implemented */
2059
        spr_register(env, SPR_HID1, "HID1",
2060
                     SPR_NOACCESS, SPR_NOACCESS,
2061
                     &spr_read_generic, &spr_write_generic,
2062
                     0x00000000);
2063
        break;
2064

    
2065
    case CPU_PPC_603:     /* PowerPC 603                   */
2066
    case CPU_PPC_603E:    /* PowerPC 603e                  */
2067
    case CPU_PPC_603E7v:
2068
    case CPU_PPC_603E7v2:
2069
    case CPU_PPC_603P:    /* PowerPC 603p                  */
2070
    case CPU_PPC_603R:    /* PowerPC 603r                  */
2071
        gen_spr_generic(env);
2072
        gen_spr_ne_601(env);
2073
        /* Memory management */
2074
        gen_low_BATs(env);
2075
        /* Time base */
2076
        gen_tbl(env);
2077
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2078
        gen_spr_603(env);
2079
        /* hardware implementation registers */
2080
        /* XXX : not implemented */
2081
        spr_register(env, SPR_HID0, "HID0",
2082
                     SPR_NOACCESS, SPR_NOACCESS,
2083
                     &spr_read_generic, &spr_write_generic,
2084
                     0x00000000);
2085
        /* XXX : not implemented */
2086
        spr_register(env, SPR_HID1, "HID1",
2087
                     SPR_NOACCESS, SPR_NOACCESS,
2088
                     &spr_read_generic, &spr_write_generic,
2089
                     0x00000000);
2090
        break;
2091
        
2092
    case CPU_PPC_G2:      /* PowerPC G2 family             */
2093
    case CPU_PPC_G2H4:
2094
    case CPU_PPC_G2gp:
2095
    case CPU_PPC_G2ls:
2096
    case CPU_PPC_G2LE:    /* PowerPC G2LE family           */
2097
    case CPU_PPC_G2LEgp:
2098
    case CPU_PPC_G2LEls:
2099
        gen_spr_generic(env);
2100
        gen_spr_ne_601(env);
2101
        /* Memory management */
2102
        gen_low_BATs(env);
2103
        /* Time base */
2104
        gen_tbl(env);
2105
        /* Memory management */
2106
        gen_high_BATs(env);
2107
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2108
        gen_spr_G2_755(env);
2109
        gen_spr_G2(env);
2110
        /* Hardware implementation register */
2111
        /* XXX : not implemented */
2112
        spr_register(env, SPR_HID0, "HID0",
2113
                     SPR_NOACCESS, SPR_NOACCESS,
2114
                     &spr_read_generic, &spr_write_generic,
2115
                     0x00000000);
2116
        /* XXX : not implemented */
2117
        spr_register(env, SPR_HID1, "HID1",
2118
                     SPR_NOACCESS, SPR_NOACCESS,
2119
                     &spr_read_generic, &spr_write_generic,
2120
                     0x00000000);
2121
        /* XXX : not implemented */
2122
        spr_register(env, SPR_HID2, "HID2",
2123
                     SPR_NOACCESS, SPR_NOACCESS,
2124
                     &spr_read_generic, &spr_write_generic,
2125
                     0x00000000);
2126
        break;
2127

    
2128
    case CPU_PPC_604:     /* PowerPC 604                   */
2129
    case CPU_PPC_604E:    /* PowerPC 604e                  */
2130
    case CPU_PPC_604R:    /* PowerPC 604r                  */
2131
        gen_spr_generic(env);
2132
        gen_spr_ne_601(env);
2133
        /* Memory management */
2134
        gen_low_BATs(env);
2135
        /* Time base */
2136
        gen_tbl(env);
2137
        gen_spr_604(env);
2138
        /* Hardware implementation registers */
2139
        /* XXX : not implemented */
2140
        spr_register(env, SPR_HID0, "HID0",
2141
                     SPR_NOACCESS, SPR_NOACCESS,
2142
                     &spr_read_generic, &spr_write_generic,
2143
                     0x00000000);
2144
        /* XXX : not implemented */
2145
        spr_register(env, SPR_HID1, "HID1",
2146
                     SPR_NOACCESS, SPR_NOACCESS,
2147
                     &spr_read_generic, &spr_write_generic,
2148
                     0x00000000);
2149
        break;
2150

    
2151
    case CPU_PPC_74x:     /* PowerPC 740 / 750             */
2152
    case CPU_PPC_740E:
2153
    case CPU_PPC_750E:
2154
    case CPU_PPC_74xP:    /* PowerPC 740P / 750P           */
2155
    case CPU_PPC_750CXE21: /* IBM PowerPC 750cxe            */
2156
    case CPU_PPC_750CXE22:
2157
    case CPU_PPC_750CXE23:
2158
    case CPU_PPC_750CXE24:
2159
    case CPU_PPC_750CXE24b:
2160
    case CPU_PPC_750CXE31:
2161
    case CPU_PPC_750CXE31b:
2162
    case CPU_PPC_750CXR:
2163
        gen_spr_generic(env);
2164
        gen_spr_ne_601(env);
2165
        /* Memory management */
2166
        gen_low_BATs(env);
2167
        /* Time base */
2168
        gen_tbl(env);
2169
        gen_spr_7xx(env);
2170
        /* Hardware implementation registers */
2171
        /* XXX : not implemented */
2172
        spr_register(env, SPR_HID0, "HID0",
2173
                     SPR_NOACCESS, SPR_NOACCESS,
2174
                     &spr_read_generic, &spr_write_generic,
2175
                     0x00000000);
2176
        /* XXX : not implemented */
2177
        spr_register(env, SPR_HID1, "HID1",
2178
                     SPR_NOACCESS, SPR_NOACCESS,
2179
                     &spr_read_generic, &spr_write_generic,
2180
                     0x00000000);
2181
        break;
2182

    
2183
    case CPU_PPC_750FX10: /* IBM PowerPC 750 FX            */
2184
    case CPU_PPC_750FX20:
2185
    case CPU_PPC_750FX21:
2186
    case CPU_PPC_750FX22:
2187
    case CPU_PPC_750FX23:
2188
    case CPU_PPC_750GX10: /* IBM PowerPC 750 GX            */
2189
    case CPU_PPC_750GX11:
2190
    case CPU_PPC_750GX12:
2191
        gen_spr_generic(env);
2192
        gen_spr_ne_601(env);
2193
        /* Memory management */
2194
        gen_low_BATs(env);
2195
        /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
2196
        gen_high_BATs(env);
2197
        /* Time base */
2198
        gen_tbl(env);
2199
        gen_spr_7xx(env);
2200
        /* Hardware implementation registers */
2201
        /* XXX : not implemented */
2202
        spr_register(env, SPR_HID0, "HID0",
2203
                     SPR_NOACCESS, SPR_NOACCESS,
2204
                     &spr_read_generic, &spr_write_generic,
2205
                     0x00000000);
2206
        /* XXX : not implemented */
2207
        spr_register(env, SPR_HID1, "HID1",
2208
                     SPR_NOACCESS, SPR_NOACCESS,
2209
                     &spr_read_generic, &spr_write_generic,
2210
                     0x00000000);
2211
        /* XXX : not implemented */
2212
        spr_register(env, SPR_750_HID2, "HID2",
2213
                     SPR_NOACCESS, SPR_NOACCESS,
2214
                     &spr_read_generic, &spr_write_generic,
2215
                     0x00000000);
2216
        break;
2217

    
2218
    case CPU_PPC_755_10:  /* PowerPC 755                   */
2219
    case CPU_PPC_755_11:
2220
    case CPU_PPC_755_20:
2221
    case CPU_PPC_755D:
2222
    case CPU_PPC_755E:
2223
        gen_spr_generic(env);
2224
        gen_spr_ne_601(env);
2225
        /* Memory management */
2226
        gen_low_BATs(env);
2227
        /* Time base */
2228
        gen_tbl(env);
2229
        /* Memory management */
2230
        gen_high_BATs(env);
2231
        gen_6xx_7xx_soft_tlb(env, 64, 2);
2232
        gen_spr_G2_755(env);
2233
        /* L2 cache control */
2234
        /* XXX : not implemented */
2235
        spr_register(env, SPR_ICTC, "ICTC",
2236
                     SPR_NOACCESS, SPR_NOACCESS,
2237
                     &spr_read_generic, &spr_write_generic,
2238
                     0x00000000);
2239
        /* XXX : not implemented */
2240
        spr_register(env, SPR_L2PM, "L2PM",
2241
                     SPR_NOACCESS, SPR_NOACCESS,
2242
                     &spr_read_generic, &spr_write_generic,
2243
                     0x00000000);
2244
        /* Hardware implementation registers */
2245
        /* XXX : not implemented */
2246
        spr_register(env, SPR_HID0, "HID0",
2247
                     SPR_NOACCESS, SPR_NOACCESS,
2248
                     &spr_read_generic, &spr_write_generic,
2249
                     0x00000000);
2250
        /* XXX : not implemented */
2251
        spr_register(env, SPR_HID1, "HID1",
2252
                     SPR_NOACCESS, SPR_NOACCESS,
2253
                     &spr_read_generic, &spr_write_generic,
2254
                     0x00000000);
2255
        /* XXX : not implemented */
2256
        spr_register(env, SPR_HID2, "HID2",
2257
                     SPR_NOACCESS, SPR_NOACCESS,
2258
                     &spr_read_generic, &spr_write_generic,
2259
                     0x00000000);
2260
        break;
2261

    
2262
#if defined (TODO)
2263
    /* G4 family */
2264
    case CPU_PPC_7400:    /* PowerPC 7400                  */
2265
    case CPU_PPC_7410C:   /* PowerPC 7410                  */
2266
    case CPU_PPC_7410D:
2267
    case CPU_PPC_7410E:
2268
    case CPU_PPC_7441:    /* PowerPC 7441                  */
2269
    case CPU_PPC_7445:    /* PowerPC 7445                  */
2270
    case CPU_PPC_7447:    /* PowerPC 7447                  */
2271
    case CPU_PPC_7447A:   /* PowerPC 7447A                 */
2272
    case CPU_PPC_7448:    /* PowerPC 7448                  */
2273
    case CPU_PPC_7450:    /* PowerPC 7450                  */
2274
    case CPU_PPC_7450b:
2275
    case CPU_PPC_7451:    /* PowerPC 7451                  */
2276
    case CPU_PPC_7451G:
2277
    case CPU_PPC_7455:    /* PowerPC 7455                  */
2278
    case CPU_PPC_7455F:
2279
    case CPU_PPC_7455G:
2280
    case CPU_PPC_7457:    /* PowerPC 7457                  */
2281
    case CPU_PPC_7457C:
2282
    case CPU_PPC_7457A:   /* PowerPC 7457A                 */
2283
        break;
2284
#endif
2285

    
2286
    /* 64 bits PowerPC                                     */
2287
#if defined (TARGET_PPC64)
2288
#if defined (TODO)
2289
    case CPU_PPC_620:     /* PowerPC 620                   */
2290
    case CPU_PPC_630:     /* PowerPC 630 (Power 3)         */
2291
    case CPU_PPC_631:     /* PowerPC 631 (Power 3+)        */
2292
    case CPU_PPC_POWER4:  /* Power 4                       */
2293
    case CPU_PPC_POWER4P: /* Power 4+                      */
2294
    case CPU_PPC_POWER5:  /* Power 5                       */
2295
    case CPU_PPC_POWER5P: /* Power 5+                      */
2296
#endif
2297
    case CPU_PPC_970:     /* PowerPC 970                   */
2298
    case CPU_PPC_970FX10: /* PowerPC 970 FX                */
2299
    case CPU_PPC_970FX20:
2300
    case CPU_PPC_970FX21:
2301
    case CPU_PPC_970FX30:
2302
    case CPU_PPC_970FX31:
2303
    case CPU_PPC_970MP10: /* PowerPC 970 MP                */
2304
    case CPU_PPC_970MP11:
2305
#if defined (TODO)
2306
    case CPU_PPC_CELL10:  /* Cell family                   */
2307
    case CPU_PPC_CELL20:
2308
    case CPU_PPC_CELL30:
2309
    case CPU_PPC_CELL31:
2310
#endif
2311
#if defined (TODO)
2312
    case CPU_PPC_RS64:    /* Apache (RS64/A35)             */
2313
    case CPU_PPC_RS64II:  /* NorthStar (RS64-II/A50)       */
2314
    case CPU_PPC_RS64III: /* Pulsar (RS64-III)             */
2315
    case CPU_PPC_RS64IV:  /* IceStar/IStar/SStar (RS64-IV) */
2316
#endif
2317
        break;
2318
#endif /* defined (TARGET_PPC64) */
2319

    
2320
#if defined (TODO)
2321
        /* POWER                                               */
2322
    case CPU_POWER:       /* POWER                         */
2323
    case CPU_POWER2:      /* POWER2                        */
2324
        break;
2325
#endif
2326

    
2327
    default:
2328
        gen_spr_generic(env);
2329
        break;
2330
    }
2331
    if (env->nb_BATs == -1)
2332
        env->nb_BATs = 4;
2333
    /* Allocate TLBs buffer when needed */
2334
    if (env->nb_tlb != 0) {
2335
        int nb_tlb = env->nb_tlb;
2336
        if (env->id_tlbs != 0)
2337
            nb_tlb *= 2;
2338
        env->tlb = qemu_mallocz(nb_tlb * sizeof(ppc_tlb_t));
2339
        /* Pre-compute some useful values */
2340
        env->tlb_per_way = env->nb_tlb / env->nb_ways;
2341
    }
2342
}
2343

    
2344
#if defined(PPC_DUMP_CPU)
2345
static void dump_sprs (CPUPPCState *env)
2346
{
2347
    ppc_spr_t *spr;
2348
    uint32_t pvr = env->spr[SPR_PVR];
2349
    uint32_t sr, sw, ur, uw;
2350
    int i, j, n;
2351

    
2352
    printf("* SPRs for PVR=%08x\n", pvr);
2353
    for (i = 0; i < 32; i++) {
2354
        for (j = 0; j < 32; j++) {
2355
            n = (i << 5) | j;
2356
            spr = &env->spr_cb[n];
2357
#if !defined(CONFIG_USER_ONLY)
2358
            sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
2359
            sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
2360
#else
2361
            sw = 0;
2362
            sr = 0;
2363
#endif
2364
            uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
2365
            ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
2366
            if (sw || sr || uw || ur) {
2367
                printf("%4d (%03x) %8s s%c%c u%c%c\n",
2368
                       (i << 5) | j, (i << 5) | j, spr->name,
2369
                       sw ? 'w' : '-', sr ? 'r' : '-',
2370
                       uw ? 'w' : '-', ur ? 'r' : '-');
2371
            }
2372
        }
2373
    }
2374
    fflush(stdout);
2375
    fflush(stderr);
2376
}
2377
#endif
2378

    
2379
/*****************************************************************************/
2380
#include <stdlib.h>
2381
#include <string.h>
2382

    
2383
int fflush (FILE *stream);
2384

    
2385
/* Opcode types */
2386
enum {
2387
    PPC_DIRECT   = 0, /* Opcode routine        */
2388
    PPC_INDIRECT = 1, /* Indirect opcode table */
2389
};
2390

    
2391
static inline int is_indirect_opcode (void *handler)
2392
{
2393
    return ((unsigned long)handler & 0x03) == PPC_INDIRECT;
2394
}
2395

    
2396
static inline opc_handler_t **ind_table(void *handler)
2397
{
2398
    return (opc_handler_t **)((unsigned long)handler & ~3);
2399
}
2400

    
2401
/* Instruction table creation */
2402
/* Opcodes tables creation */
2403
static void fill_new_table (opc_handler_t **table, int len)
2404
{
2405
    int i;
2406

    
2407
    for (i = 0; i < len; i++)
2408
        table[i] = &invalid_handler;
2409
}
2410

    
2411
static int create_new_table (opc_handler_t **table, unsigned char idx)
2412
{
2413
    opc_handler_t **tmp;
2414

    
2415
    tmp = malloc(0x20 * sizeof(opc_handler_t));
2416
    if (tmp == NULL)
2417
        return -1;
2418
    fill_new_table(tmp, 0x20);
2419
    table[idx] = (opc_handler_t *)((unsigned long)tmp | PPC_INDIRECT);
2420

    
2421
    return 0;
2422
}
2423

    
2424
static int insert_in_table (opc_handler_t **table, unsigned char idx,
2425
                            opc_handler_t *handler)
2426
{
2427
    if (table[idx] != &invalid_handler)
2428
        return -1;
2429
    table[idx] = handler;
2430

    
2431
    return 0;
2432
}
2433

    
2434
static int register_direct_insn (opc_handler_t **ppc_opcodes,
2435
                                 unsigned char idx, opc_handler_t *handler)
2436
{
2437
    if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
2438
        printf("*** ERROR: opcode %02x already assigned in main "
2439
               "opcode table\n", idx);
2440
        return -1;
2441
    }
2442

    
2443
    return 0;
2444
}
2445

    
2446
static int register_ind_in_table (opc_handler_t **table,
2447
                                  unsigned char idx1, unsigned char idx2,
2448
                                  opc_handler_t *handler)
2449
{
2450
    if (table[idx1] == &invalid_handler) {
2451
        if (create_new_table(table, idx1) < 0) {
2452
            printf("*** ERROR: unable to create indirect table "
2453
                   "idx=%02x\n", idx1);
2454
            return -1;
2455
        }
2456
    } else {
2457
        if (!is_indirect_opcode(table[idx1])) {
2458
            printf("*** ERROR: idx %02x already assigned to a direct "
2459
                   "opcode\n", idx1);
2460
            return -1;
2461
        }
2462
    }
2463
    if (handler != NULL &&
2464
        insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
2465
        printf("*** ERROR: opcode %02x already assigned in "
2466
               "opcode table %02x\n", idx2, idx1);
2467
        return -1;
2468
    }
2469

    
2470
    return 0;
2471
}
2472

    
2473
static int register_ind_insn (opc_handler_t **ppc_opcodes,
2474
                              unsigned char idx1, unsigned char idx2,
2475
                              opc_handler_t *handler)
2476
{
2477
    int ret;
2478

    
2479
    ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
2480

    
2481
    return ret;
2482
}
2483

    
2484
static int register_dblind_insn (opc_handler_t **ppc_opcodes, 
2485
                                 unsigned char idx1, unsigned char idx2,
2486
                                 unsigned char idx3, opc_handler_t *handler)
2487
{
2488
    if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
2489
        printf("*** ERROR: unable to join indirect table idx "
2490
               "[%02x-%02x]\n", idx1, idx2);
2491
        return -1;
2492
    }
2493
    if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
2494
                              handler) < 0) {
2495
        printf("*** ERROR: unable to insert opcode "
2496
               "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
2497
        return -1;
2498
    }
2499

    
2500
    return 0;
2501
}
2502

    
2503
static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
2504
{
2505
    if (insn->opc2 != 0xFF) {
2506
        if (insn->opc3 != 0xFF) {
2507
            if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
2508
                                     insn->opc3, &insn->handler) < 0)
2509
                return -1;
2510
        } else {
2511
            if (register_ind_insn(ppc_opcodes, insn->opc1,
2512
                                  insn->opc2, &insn->handler) < 0)
2513
                return -1;
2514
        }
2515
    } else {
2516
        if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
2517
            return -1;
2518
    }
2519

    
2520
    return 0;
2521
}
2522

    
2523
static int test_opcode_table (opc_handler_t **table, int len)
2524
{
2525
    int i, count, tmp;
2526

    
2527
    for (i = 0, count = 0; i < len; i++) {
2528
        /* Consistency fixup */
2529
        if (table[i] == NULL)
2530
            table[i] = &invalid_handler;
2531
        if (table[i] != &invalid_handler) {
2532
            if (is_indirect_opcode(table[i])) {
2533
                tmp = test_opcode_table(ind_table(table[i]), 0x20);
2534
                if (tmp == 0) {
2535
                    free(table[i]);
2536
                    table[i] = &invalid_handler;
2537
                } else {
2538
                    count++;
2539
                }
2540
            } else {
2541
                count++;
2542
            }
2543
        }
2544
    }
2545

    
2546
    return count;
2547
}
2548

    
2549
static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
2550
{
2551
    if (test_opcode_table(ppc_opcodes, 0x40) == 0)
2552
        printf("*** WARNING: no opcode defined !\n");
2553
}
2554

    
2555
/*****************************************************************************/
2556
static int create_ppc_opcodes (CPUPPCState *env, ppc_def_t *def)
2557
{
2558
    opcode_t *opc, *start, *end;
2559

    
2560
    fill_new_table(env->opcodes, 0x40);
2561
#if defined(PPC_DUMP_CPU)
2562
    printf("* PowerPC instructions for PVR %08x: %s flags %016" PRIx64
2563
           " %08x\n",
2564
           def->pvr, def->name, def->insns_flags, def->flags);
2565
#endif
2566
    if (&opc_start < &opc_end) {
2567
        start = &opc_start;
2568
        end = &opc_end;
2569
    } else {
2570
        start = &opc_end;
2571
        end = &opc_start;
2572
    }
2573
    for (opc = start + 1; opc != end; opc++) {
2574
        if ((opc->handler.type & def->insns_flags) != 0) {
2575
            if (register_insn(env->opcodes, opc) < 0) {
2576
                printf("*** ERROR initializing PowerPC instruction "
2577
                       "0x%02x 0x%02x 0x%02x\n", opc->opc1, opc->opc2,
2578
                       opc->opc3);
2579
                return -1;
2580
            }
2581
#if defined(PPC_DUMP_CPU)
2582
            if (opc1 != 0x00) {
2583
                if (opc->opc3 == 0xFF) {
2584
                    if (opc->opc2 == 0xFF) {
2585
                        printf(" %02x -- -- (%2d ----) : %s\n",
2586
                               opc->opc1, opc->opc1, opc->oname);
2587
                    } else {
2588
                        printf(" %02x %02x -- (%2d %4d) : %s\n",
2589
                               opc->opc1, opc->opc2, opc->opc1, opc->opc2,
2590
                               opc->oname);
2591
                    }
2592
                } else {
2593
                    printf(" %02x %02x %02x (%2d %4d) : %s\n",
2594
                           opc->opc1, opc->opc2, opc->opc3,
2595
                           opc->opc1, (opc->opc3 << 5) | opc->opc2,
2596
                           opc->oname);
2597
                }
2598
            }
2599
#endif
2600
        }
2601
    }
2602
    fix_opcode_tables(env->opcodes);
2603
    fflush(stdout);
2604
    fflush(stderr);
2605

    
2606
    return 0;
2607
}
2608

    
2609
int cpu_ppc_register (CPUPPCState *env, ppc_def_t *def)
2610
{
2611
    env->msr_mask = def->msr_mask;
2612
    env->flags = def->flags;
2613
    if (create_ppc_opcodes(env, def) < 0)
2614
        return -1;
2615
    init_ppc_proc(env, def);
2616
#if defined(PPC_DUMP_CPU)
2617
    dump_sprs(env);
2618
    if (env->tlb != NULL) {
2619
        printf("%d %s TLB in %d ways\n", env->nb_tlb,
2620
               env->id_tlbs ? "splitted" : "merged", env->nb_ways);
2621
    }
2622
#endif
2623

    
2624
    return 0;
2625
}
2626

    
2627
void do_compute_hflags (CPUPPCState *env);
2628
CPUPPCState *cpu_ppc_init (void)
2629
{
2630
    CPUPPCState *env;
2631

    
2632
    env = qemu_mallocz(sizeof(CPUPPCState));
2633
    if (!env)
2634
        return NULL;
2635
    cpu_exec_init(env);
2636
    tlb_flush(env, 1);
2637
#if defined (DO_SINGLE_STEP) && 0
2638
    /* Single step trace mode */
2639
    msr_se = 1;
2640
    msr_be = 1;
2641
#endif
2642
    msr_fp = 1; /* Allow floating point exceptions */
2643
    msr_me = 1; /* Allow machine check exceptions  */
2644
#if defined(CONFIG_USER_ONLY)
2645
    msr_pr = 1;
2646
#else
2647
    env->nip = 0xFFFFFFFC;
2648
#endif
2649
    do_compute_hflags(env);
2650
    env->reserve = -1;
2651
    return env;
2652
}
2653

    
2654
void cpu_ppc_close(CPUPPCState *env)
2655
{
2656
    /* Should also remove all opcode tables... */
2657
    free(env);
2658
}
2659

    
2660
/*****************************************************************************/
2661
/* PowerPC CPU definitions */
2662
static ppc_def_t ppc_defs[] =
2663
    {
2664
        /* Embedded PowerPC */
2665
#if defined (TODO)
2666
        /* PowerPC 401 */
2667
        {
2668
            .name        = "401",
2669
            .pvr         = CPU_PPC_401,
2670
            .pvr_mask    = 0xFFFF0000,
2671
            .insns_flags = PPC_INSNS_401,
2672
            .flags       = PPC_FLAGS_401,
2673
            .msr_mask    = xxx,
2674
        },
2675
#endif
2676
#if defined (TODO)
2677
        /* IOP480 (401 microcontroler) */
2678
        {
2679
            .name        = "iop480",
2680
            .pvr         = CPU_PPC_IOP480,
2681
            .pvr_mask    = 0xFFFF0000,
2682
            .insns_flags = PPC_INSNS_401,
2683
            .flags       = PPC_FLAGS_401,
2684
            .msr_mask    = xxx,
2685
        },
2686
#endif
2687
#if defined (TODO)
2688
        /* IBM Processor for Network Resources */
2689
        {
2690
            .name        = "Cobra",
2691
            .pvr         = CPU_PPC_COBRA,
2692
            .pvr_mask    = 0xFFFF0000,
2693
            .insns_flags = PPC_INSNS_401,
2694
            .flags       = PPC_FLAGS_401,
2695
            .msr_mask    = xxx,
2696
        },
2697
#endif
2698
#if defined (TODO)
2699
        /* Generic PowerPC 403 */
2700
        {
2701
            .name        = "403",
2702
            .pvr         = CPU_PPC_403,
2703
            .pvr_mask    = 0xFFFFFF00,
2704
            .insns_flags = PPC_INSNS_403,
2705
            .flags       = PPC_FLAGS_403,
2706
            .msr_mask    = 0x000000000007D23D,
2707
        },
2708
#endif
2709
#if defined (TODO)
2710
        /* PowerPC 403 GA */
2711
        {
2712
            .name        = "403ga",
2713
            .pvr         = CPU_PPC_403GA,
2714
            .pvr_mask    = 0xFFFFFF00,
2715
            .insns_flags = PPC_INSNS_403,
2716
            .flags       = PPC_FLAGS_403,
2717
            .msr_mask    = 0x000000000007D23D,
2718
        },
2719
#endif
2720
#if defined (TODO)
2721
        /* PowerPC 403 GB */
2722
        {
2723
            .name        = "403gb",
2724
            .pvr         = CPU_PPC_403GB,
2725
            .pvr_mask    = 0xFFFFFF00,
2726
            .insns_flags = PPC_INSNS_403,
2727
            .flags       = PPC_FLAGS_403,
2728
            .msr_mask    = 0x000000000007D23D,
2729
        },
2730
#endif
2731
#if defined (TODO)
2732
        /* PowerPC 403 GC */
2733
        {
2734
            .name        = "403gc",
2735
            .pvr         = CPU_PPC_403GC,
2736
            .pvr_mask    = 0xFFFFFF00,
2737
            .insns_flags = PPC_INSNS_403,
2738
            .flags       = PPC_FLAGS_403,
2739
            .msr_mask    = 0x000000000007D23D,
2740
        },
2741
#endif
2742
#if defined (TODO)
2743
        /* PowerPC 403 GCX */
2744
        {
2745
            .name        = "403gcx",
2746
            .pvr         = CPU_PPC_403GCX,
2747
            .pvr_mask    = 0xFFFFFF00,
2748
            .insns_flags = PPC_INSNS_403,
2749
            .flags       = PPC_FLAGS_403,
2750
            .msr_mask    = 0x000000000007D23D,
2751
        },
2752
#endif
2753
#if defined (TODO)
2754
        /* Generic PowerPC 405 */
2755
        {
2756
            .name        = "405",
2757
            .pvr         = CPU_PPC_405,
2758
            .pvr_mask    = 0xFFFF0000,
2759
            .insns_flags = PPC_INSNS_405,
2760
            .flags       = PPC_FLAGS_405,
2761
            .msr_mask    = 0x00000000020EFF30,
2762
        },
2763
#endif
2764
#if defined (TODO)
2765
        /* PowerPC 405 CR */
2766
        {
2767
            .name        = "405cr",
2768
            .pvr         = CPU_PPC_405,
2769
            .pvr_mask    = 0xFFFF0000,
2770
            .insns_flags = PPC_INSNS_405,
2771
            .flags       = PPC_FLAGS_405,
2772
            .msr_mask    = 0x00000000020EFF30,
2773
        },
2774
#endif
2775
#if defined (TODO)
2776
        /* PowerPC 405 GP */
2777
        {
2778
            .name        = "405gp",
2779
            .pvr         = CPU_PPC_405,
2780
            .pvr_mask    = 0xFFFF0000,
2781
            .insns_flags = PPC_INSNS_405,
2782
            .flags       = PPC_FLAGS_405,
2783
            .msr_mask    = 0x00000000020EFF30,
2784
        },
2785
#endif
2786
#if defined (TODO)
2787
        /* PowerPC 405 EP */
2788
        {
2789
            .name        = "405ep",
2790
            .pvr         = CPU_PPC_405EP,
2791
            .pvr_mask    = 0xFFFF0000,
2792
            .insns_flags = PPC_INSNS_405,
2793
            .flags       = PPC_FLAGS_405,
2794
            .msr_mask    = 0x00000000020EFF30,
2795
        },
2796
#endif
2797
#if defined (TODO)
2798
        /* PowerPC 405 GPR */
2799
        {
2800
            .name        = "405gpr",
2801
            .pvr         = CPU_PPC_405GPR,
2802
            .pvr_mask    = 0xFFFF0000,
2803
            .insns_flags = PPC_INSNS_405,
2804
            .flags       = PPC_FLAGS_405,
2805
            .msr_mask    = 0x00000000020EFF30,
2806
        },
2807
#endif
2808
#if defined (TODO)
2809
        /* PowerPC 405 D2 */
2810
        {
2811
            .name        = "405d2",
2812
            .pvr         = CPU_PPC_405D2,
2813
            .pvr_mask    = 0xFFFF0000,
2814
            .insns_flags = PPC_INSNS_405,
2815
            .flags       = PPC_FLAGS_405,
2816
            .msr_mask    = 0x00000000020EFF30,
2817
        },
2818
#endif
2819
#if defined (TODO)
2820
        /* PowerPC 405 D4 */
2821
        {
2822
            .name        = "405d4",
2823
            .pvr         = CPU_PPC_405D4,
2824
            .pvr_mask    = 0xFFFF0000,
2825
            .insns_flags = PPC_INSNS_405,
2826
            .flags       = PPC_FLAGS_405,
2827
            .msr_mask    = 0x00000000020EFF30,
2828
        },
2829
#endif
2830
#if defined (TODO)
2831
        /* Npe405 H */
2832
        {
2833
            .name        = "Npe405H",
2834
            .pvr         = CPU_PPC_NPE405H,
2835
            .pvr_mask    = 0xFFFF0000,
2836
            .insns_flags = PPC_INSNS_405,
2837
            .flags       = PPC_FLAGS_405,
2838
            .msr_mask    = 0x00000000020EFF30,
2839
        },
2840
#endif
2841
#if defined (TODO)
2842
        /* Npe405 L */
2843
        {
2844
            .name        = "Npe405L",
2845
            .pvr         = CPU_PPC_NPE405L,
2846
            .pvr_mask    = 0xFFFF0000,
2847
            .insns_flags = PPC_INSNS_405,
2848
            .flags       = PPC_FLAGS_405,
2849
            .msr_mask    = 0x00000000020EFF30,
2850
        },
2851
#endif
2852
#if defined (TODO)
2853
        /* STB010000 */
2854
        {
2855
            .name        = "STB01000",
2856
            .pvr         = CPU_PPC_STB01000,
2857
            .pvr_mask    = 0xFFFF0000,
2858
            .insns_flags = PPC_INSNS_405,
2859
            .flags       = PPC_FLAGS_405,
2860
            .msr_mask    = 0x00000000020EFF30,
2861
        },
2862
#endif
2863
#if defined (TODO)
2864
        /* STB01010 */
2865
        {
2866
            .name        = "STB01010",
2867
            .pvr         = CPU_PPC_STB01010,
2868
            .pvr_mask    = 0xFFFF0000,
2869
            .insns_flags = PPC_INSNS_405,
2870
            .flags       = PPC_FLAGS_405,
2871
            .msr_mask    = 0x00000000020EFF30,
2872
        },
2873
#endif
2874
#if defined (TODO)
2875
        /* STB0210 */
2876
        {
2877
            .name        = "STB0210",
2878
            .pvr         = CPU_PPC_STB0210,
2879
            .pvr_mask    = 0xFFFF0000,
2880
            .insns_flags = PPC_INSNS_405,
2881
            .flags       = PPC_FLAGS_405,
2882
            .msr_mask    = 0x00000000020EFF30,
2883
        },
2884
#endif
2885
#if defined (TODO)
2886
        /* STB03xx */
2887
        {
2888
            .name        = "STB03",
2889
            .pvr         = CPU_PPC_STB03,
2890
            .pvr_mask    = 0xFFFF0000,
2891
            .insns_flags = PPC_INSNS_405,
2892
            .flags       = PPC_FLAGS_405,
2893
            .msr_mask    = 0x00000000020EFF30,
2894
        },
2895
#endif
2896
#if defined (TODO)
2897
        /* STB043x */
2898
        {
2899
            .name        = "STB043",
2900
            .pvr         = CPU_PPC_STB043,
2901
            .pvr_mask    = 0xFFFF0000,
2902
            .insns_flags = PPC_INSNS_405,
2903
            .flags       = PPC_FLAGS_405,
2904
            .msr_mask    = 0x00000000020EFF30,
2905
        },
2906
#endif
2907
#if defined (TODO)
2908
        /* STB045x */
2909
        {
2910
            .name        = "STB045",
2911
            .pvr         = CPU_PPC_STB045,
2912
            .pvr_mask    = 0xFFFF0000,
2913
            .insns_flags = PPC_INSNS_405,
2914
            .flags       = PPC_FLAGS_405,
2915
            .msr_mask    = 0x00000000020EFF30,
2916
        },
2917
#endif
2918
#if defined (TODO)
2919
        /* STB25xx */
2920
        {
2921
            .name        = "STB25",
2922
            .pvr         = CPU_PPC_STB25,
2923
            .pvr_mask    = 0xFFFF0000,
2924
            .insns_flags = PPC_INSNS_405,
2925
            .flags       = PPC_FLAGS_405,
2926
            .msr_mask    = 0x00000000020EFF30,
2927
        },
2928
#endif
2929
#if defined (TODO)
2930
        /* STB130 */
2931
        {
2932
            .name        = "STB130",
2933
            .pvr         = CPU_PPC_STB130,
2934
            .pvr_mask    = 0xFFFF0000,
2935
            .insns_flags = PPC_INSNS_405,
2936
            .flags       = PPC_FLAGS_405,
2937
            .msr_mask    = 0x00000000020EFF30,
2938
        },
2939
#endif
2940
        /* Xilinx PowerPC 405 cores */
2941
#if defined (TODO)
2942
        {
2943
            .name        = "x2vp4",
2944
            .pvr         = CPU_PPC_X2VP4,
2945
            .pvr_mask    = 0xFFFF0000,
2946
            .insns_flags = PPC_INSNS_405,
2947
            .flags       = PPC_FLAGS_405,
2948
            .msr_mask    = 0x00000000020EFF30,
2949
        },
2950
        {
2951
            .name        = "x2vp7",
2952
            .pvr         = CPU_PPC_X2VP7,
2953
            .pvr_mask    = 0xFFFF0000,
2954
            .insns_flags = PPC_INSNS_405,
2955
            .flags       = PPC_FLAGS_405,
2956
            .msr_mask    = 0x00000000020EFF30,
2957
        },
2958
        {
2959
            .name        = "x2vp20",
2960
            .pvr         = CPU_PPC_X2VP20,
2961
            .pvr_mask    = 0xFFFF0000,
2962
            .insns_flags = PPC_INSNS_405,
2963
            .flags       = PPC_FLAGS_405,
2964
            .msr_mask    = 0x00000000020EFF30,
2965
        },
2966
        {
2967
            .name        = "x2vp50",
2968
            .pvr         = CPU_PPC_X2VP50,
2969
            .pvr_mask    = 0xFFFF0000,
2970
            .insns_flags = PPC_INSNS_405,
2971
            .flags       = PPC_FLAGS_405,
2972
            .msr_mask    = 0x00000000020EFF30,
2973
        },
2974
#endif
2975
#if defined (TODO)
2976
        /* PowerPC 440 EP */
2977
        {
2978
            .name        = "440ep",
2979
            .pvr         = CPU_PPC_440EP,
2980
            .pvr_mask    = 0xFFFF0000,
2981
            .insns_flags = PPC_INSNS_440,
2982
            .flags       = PPC_FLAGS_440,
2983
            .msr_mask    = 0x000000000006D630,
2984
        },
2985
#endif
2986
#if defined (TODO)
2987
        /* PowerPC 440 GR */
2988
        {
2989
            .name        = "440gr",
2990
            .pvr         = CPU_PPC_440GR,
2991
            .pvr_mask    = 0xFFFF0000,
2992
            .insns_flags = PPC_INSNS_440,
2993
            .flags       = PPC_FLAGS_440,
2994
            .msr_mask    = 0x000000000006D630,
2995
        },
2996
#endif
2997
#if defined (TODO)
2998
        /* PowerPC 440 GP */
2999
        {
3000
            .name        = "440gp",
3001
            .pvr         = CPU_PPC_440GP,
3002
            .pvr_mask    = 0xFFFFFF00,
3003
            .insns_flags = PPC_INSNS_440,
3004
            .flags       = PPC_FLAGS_440,
3005
            .msr_mask    = 0x000000000006D630,
3006
        },
3007
#endif
3008
#if defined (TODO)
3009
        /* PowerPC 440 GX */
3010
        {
3011
            .name        = "440gx",
3012
            .pvr         = CPU_PPC_440GX,
3013
            .pvr_mask    = 0xFFFF0000,
3014
            .insns_flags = PPC_INSNS_405,
3015
            .flags       = PPC_FLAGS_440,
3016
            .msr_mask    = 0x000000000006D630,
3017
        },
3018
#endif
3019
#if defined (TODO)
3020
        /* PowerPC 440 GXc */
3021
        {
3022
            .name        = "440gxc",
3023
            .pvr         = CPU_PPC_440GXC,
3024
            .pvr_mask    = 0xFFFF0000,
3025
            .insns_flags = PPC_INSNS_405,
3026
            .flags       = PPC_FLAGS_440,
3027
            .msr_mask    = 0x000000000006D630,
3028
        },
3029
#endif
3030
#if defined (TODO)
3031
        /* PowerPC 440 GXf */
3032
        {
3033
            .name        = "440gxf",
3034
            .pvr         = CPU_PPC_440GXF,
3035
            .pvr_mask    = 0xFFFF0000,
3036
            .insns_flags = PPC_INSNS_405,
3037
            .flags       = PPC_FLAGS_440,
3038
            .msr_mask    = 0x000000000006D630,
3039
        },
3040
#endif
3041
#if defined (TODO)
3042
        /* PowerPC 440 SP */
3043
        {
3044
            .name        = "440sp",
3045
            .pvr         = CPU_PPC_440SP,
3046
            .pvr_mask    = 0xFFFF0000,
3047
            .insns_flags = PPC_INSNS_405,
3048
            .flags       = PPC_FLAGS_440,
3049
            .msr_mask    = 0x000000000006D630,
3050
        },
3051
#endif
3052
#if defined (TODO)
3053
        /* PowerPC 440 SP2 */
3054
        {
3055
            .name        = "440sp2",
3056
            .pvr         = CPU_PPC_440SP2,
3057
            .pvr_mask    = 0xFFFF0000,
3058
            .insns_flags = PPC_INSNS_405,
3059
            .flags       = PPC_FLAGS_440,
3060
            .msr_mask    = 0x000000000006D630,
3061
        },
3062
#endif
3063
#if defined (TODO)
3064
        /* PowerPC 440 SPE */
3065
        {
3066
            .name        = "440spe",
3067
            .pvr         = CPU_PPC_440SPE,
3068
            .pvr_mask    = 0xFFFF0000,
3069
            .insns_flags = PPC_INSNS_405,
3070
            .flags       = PPC_FLAGS_440,
3071
            .msr_mask    = 0x000000000006D630,
3072
        },
3073
#endif
3074
        /* Fake generic BookE PowerPC */
3075
        {
3076
            .name        = "BookE",
3077
            .pvr         = CPU_PPC_e500,
3078
            .pvr_mask    = 0xFFFFFFFF,
3079
            .insns_flags = PPC_INSNS_BOOKE,
3080
            .flags       = PPC_FLAGS_BOOKE,
3081
            .msr_mask    = 0x000000000006D630,
3082
        },
3083
        /* PowerPC 460 cores - TODO */
3084
        /* PowerPC MPC 5xx cores - TODO */
3085
        /* PowerPC MPC 8xx cores - TODO */
3086
        /* PowerPC MPC 8xxx cores - TODO */
3087
        /* e200 cores - TODO */
3088
        /* e500 cores - TODO */
3089
        /* e600 cores - TODO */
3090

    
3091
        /* 32 bits "classic" PowerPC */
3092
#if defined (TODO)
3093
        /* PowerPC 601 */
3094
        {
3095
            .name        = "601",
3096
            .pvr         = CPU_PPC_601,
3097
            .pvr_mask    = 0xFFFF0000,
3098
            .insns_flags = PPC_INSNS_601,
3099
            .flags       = PPC_FLAGS_601,
3100
            .msr_mask    = 0x000000000000FD70,
3101
        },
3102
#endif
3103
#if defined (TODO)
3104
        /* PowerPC 602 */
3105
        {
3106
            .name        = "602",
3107
            .pvr         = CPU_PPC_602,
3108
            .pvr_mask    = 0xFFFF0000,
3109
            .insns_flags = PPC_INSNS_602,
3110
            .flags       = PPC_FLAGS_602,
3111
            .msr_mask    = 0x0000000000C7FF73,
3112
        },
3113
#endif
3114
        /* PowerPC 603 */
3115
        {
3116
            .name        = "603",
3117
            .pvr         = CPU_PPC_603,
3118
            .pvr_mask    = 0xFFFFFFFF,
3119
            .insns_flags = PPC_INSNS_603,
3120
            .flags       = PPC_FLAGS_603,
3121
            .msr_mask    = 0x000000000007FF73,
3122
        },
3123
        /* PowerPC 603e */
3124
        {
3125
            .name        = "603e",
3126
            .pvr         = CPU_PPC_603E,
3127
            .pvr_mask    = 0xFFFFFFFF,
3128
            .insns_flags = PPC_INSNS_603,
3129
            .flags       = PPC_FLAGS_603,
3130
            .msr_mask    = 0x000000000007FF73,
3131
        },
3132
        {
3133
            .name        = "Stretch",
3134
            .pvr         = CPU_PPC_603E,
3135
            .pvr_mask    = 0xFFFFFFFF,
3136
            .insns_flags = PPC_INSNS_603,
3137
            .flags       = PPC_FLAGS_603,
3138
            .msr_mask    = 0x000000000007FF73,
3139
        },
3140
        /* PowerPC 603p */
3141
        {
3142
            .name        = "603p",
3143
            .pvr         = CPU_PPC_603P,
3144
            .pvr_mask    = 0xFFFFFFFF,
3145
            .insns_flags = PPC_INSNS_603,
3146
            .flags       = PPC_FLAGS_603,
3147
            .msr_mask    = 0x000000000007FF73,
3148
        },
3149
        /* PowerPC 603e7 */
3150
        {
3151
            .name        = "603e7",
3152
            .pvr         = CPU_PPC_603E7,
3153
            .pvr_mask    = 0xFFFFFFFF,
3154
            .insns_flags = PPC_INSNS_603,
3155
            .flags       = PPC_FLAGS_603,
3156
            .msr_mask    = 0x000000000007FF73,
3157
        },
3158
        /* PowerPC 603e7v */
3159
        {
3160
            .name        = "603e7v",
3161
            .pvr         = CPU_PPC_603E7v,
3162
            .pvr_mask    = 0xFFFFFFFF,
3163
            .insns_flags = PPC_INSNS_603,
3164
            .flags       = PPC_FLAGS_603,
3165
            .msr_mask    = 0x000000000007FF73,
3166
        },
3167
        /* PowerPC 603e7v2 */
3168
        {
3169
            .name        = "603e7v2",
3170
            .pvr         = CPU_PPC_603E7v2,
3171
            .pvr_mask    = 0xFFFFFFFF,
3172
            .insns_flags = PPC_INSNS_603,
3173
            .flags       = PPC_FLAGS_603,
3174
            .msr_mask    = 0x000000000007FF73,
3175
        },
3176
        /* PowerPC 603r */
3177
        {
3178
            .name        = "603r",
3179
            .pvr         = CPU_PPC_603R,
3180
            .pvr_mask    = 0xFFFFFFFF,
3181
            .insns_flags = PPC_INSNS_603,
3182
            .flags       = PPC_FLAGS_603,
3183
            .msr_mask    = 0x000000000007FF73,
3184
        },
3185
        {
3186
            .name        = "Goldeneye",
3187
            .pvr         = CPU_PPC_603R,
3188
            .pvr_mask    = 0xFFFFFFFF,
3189
            .insns_flags = PPC_INSNS_603,
3190
            .flags       = PPC_FLAGS_603,
3191
            .msr_mask    = 0x000000000007FF73,
3192
        },
3193
#if defined (TODO)
3194
        /* XXX: TODO: according to Motorola UM, this is a derivative to 603e */
3195
        {
3196
            .name        = "G2",
3197
            .pvr         = CPU_PPC_G2,
3198
            .pvr_mask    = 0xFFFF0000,
3199
            .insns_flags = PPC_INSNS_G2,
3200
            .flags       = PPC_FLAGS_G2,
3201
            .msr_mask    = 0x000000000006FFF2,
3202
        },
3203
        {
3204
            .name        = "G2h4",
3205
            .pvr         = CPU_PPC_G2H4,
3206
            .pvr_mask    = 0xFFFF0000,
3207
            .insns_flags = PPC_INSNS_G2,
3208
            .flags       = PPC_FLAGS_G2,
3209
            .msr_mask    = 0x000000000006FFF2,
3210
        },
3211
        {
3212
            .name        = "G2gp",
3213
            .pvr         = CPU_PPC_G2gp,
3214
            .pvr_mask    = 0xFFFF0000,
3215
            .insns_flags = PPC_INSNS_G2,
3216
            .flags       = PPC_FLAGS_G2,
3217
            .msr_mask    = 0x000000000006FFF2,
3218
        },
3219
        {
3220
            .name        = "G2ls",
3221
            .pvr         = CPU_PPC_G2ls,
3222
            .pvr_mask    = 0xFFFF0000,
3223
            .insns_flags = PPC_INSNS_G2,
3224
            .flags       = PPC_FLAGS_G2,
3225
            .msr_mask    = 0x000000000006FFF2,
3226
        },
3227
        { /* Same as G2, with LE mode support */
3228
            .name        = "G2le",
3229
            .pvr         = CPU_PPC_G2LE,
3230
            .pvr_mask    = 0xFFFF0000,
3231
            .insns_flags = PPC_INSNS_G2,
3232
            .flags       = PPC_FLAGS_G2,
3233
            .msr_mask    = 0x000000000007FFF3,
3234
        },
3235
        {
3236
            .name        = "G2legp",
3237
            .pvr         = CPU_PPC_G2LEgp,
3238
            .pvr_mask    = 0xFFFF0000,
3239
            .insns_flags = PPC_INSNS_G2,
3240
            .flags       = PPC_FLAGS_G2,
3241
            .msr_mask    = 0x000000000007FFF3,
3242
        },
3243
        {
3244
            .name        = "G2lels",
3245
            .pvr         = CPU_PPC_G2LEls,
3246
            .pvr_mask    = 0xFFFF0000,
3247
            .insns_flags = PPC_INSNS_G2,
3248
            .flags       = PPC_FLAGS_G2,
3249
            .msr_mask    = 0x000000000007FFF3,
3250
        },
3251
#endif
3252
        /* PowerPC 604 */
3253
        {
3254
            .name        = "604",
3255
            .pvr         = CPU_PPC_604,
3256
            .pvr_mask    = 0xFFFFFFFF,
3257
            .insns_flags = PPC_INSNS_604,
3258
            .flags       = PPC_FLAGS_604,
3259
            .msr_mask    = 0x000000000005FF77,
3260
        },
3261
        /* PowerPC 604e */
3262
        {
3263
            .name        = "604e",
3264
            .pvr         = CPU_PPC_604E,
3265
            .pvr_mask    = 0xFFFFFFFF,
3266
            .insns_flags = PPC_INSNS_604,
3267
            .flags       = PPC_FLAGS_604,
3268
            .msr_mask    = 0x000000000005FF77,
3269
        },
3270
        /* PowerPC 604r */
3271
        {
3272
            .name        = "604r",
3273
            .pvr         = CPU_PPC_604R,
3274
            .pvr_mask    = 0xFFFFFFFF,
3275
            .insns_flags = PPC_INSNS_604,
3276
            .flags       = PPC_FLAGS_604,
3277
            .msr_mask    = 0x000000000005FF77,
3278
        },
3279
        /* generic G3 */
3280
        {
3281
            .name        = "G3",
3282
            .pvr         = CPU_PPC_74x,
3283
            .pvr_mask    = 0xFFFFFFFF,
3284
            .insns_flags = PPC_INSNS_7x0,
3285
            .flags       = PPC_FLAGS_7x0,
3286
            .msr_mask    = 0x000000000007FF77,
3287
        },
3288
        /* MPC740 (G3) */
3289
        {
3290
            .name        = "740",
3291
            .pvr         = CPU_PPC_74x,
3292
            .pvr_mask    = 0xFFFFFFFF,
3293
            .insns_flags = PPC_INSNS_7x0,
3294
            .flags       = PPC_FLAGS_7x0,
3295
            .msr_mask    = 0x000000000007FF77,
3296
        },
3297
        {
3298
            .name        = "Arthur",
3299
            .pvr         = CPU_PPC_74x,
3300
            .pvr_mask    = 0xFFFFFFFF,
3301
            .insns_flags = PPC_INSNS_7x0,
3302
            .flags       = PPC_FLAGS_7x0,
3303
            .msr_mask    = 0x000000000007FF77,
3304
        },
3305
#if defined (TODO)
3306
        /* MPC745 (G3) */
3307
        {
3308
            .name        = "745",
3309
            .pvr         = CPU_PPC_74x,
3310
            .pvr_mask    = 0xFFFFF000,
3311
            .insns_flags = PPC_INSNS_7x5,
3312
            .flags       = PPC_FLAGS_7x5,
3313
            .msr_mask    = 0x000000000007FF77,
3314
        },
3315
        {
3316
            .name        = "Goldfinger",
3317
            .pvr         = CPU_PPC_74x,
3318
            .pvr_mask    = 0xFFFFF000,
3319
            .insns_flags = PPC_INSNS_7x5,
3320
            .flags       = PPC_FLAGS_7x5,
3321
            .msr_mask    = 0x000000000007FF77,
3322
        },
3323
#endif
3324
        /* MPC750 (G3) */
3325
        {
3326
            .name        = "750",
3327
            .pvr         = CPU_PPC_74x,
3328
            .pvr_mask    = 0xFFFFFFFF,
3329
            .insns_flags = PPC_INSNS_7x0,
3330
            .flags       = PPC_FLAGS_7x0,
3331
            .msr_mask    = 0x000000000007FF77,
3332
        },
3333
#if defined (TODO)
3334
        /* MPC755 (G3) */
3335
        {
3336
            .name        = "755",
3337
            .pvr         = CPU_PPC_755,
3338
            .pvr_mask    = 0xFFFFF000,
3339
            .insns_flags = PPC_INSNS_7x5,
3340
            .flags       = PPC_FLAGS_7x5,
3341
            .msr_mask    = 0x000000000007FF77,
3342
        },
3343
#endif
3344
        /* MPC740P (G3) */
3345
        {
3346
            .name        = "740p",
3347
            .pvr         = CPU_PPC_74xP,
3348
            .pvr_mask    = 0xFFFFFFFF,
3349
            .insns_flags = PPC_INSNS_7x0,
3350
            .flags       = PPC_FLAGS_7x0,
3351
            .msr_mask    = 0x000000000007FF77,
3352
        },
3353
        {
3354
            .name        = "Conan/Doyle",
3355
            .pvr         = CPU_PPC_74xP,
3356
            .pvr_mask    = 0xFFFFFFFF,
3357
            .insns_flags = PPC_INSNS_7x0,
3358
            .flags       = PPC_FLAGS_7x0,
3359
            .msr_mask    = 0x000000000007FF77,
3360
        },
3361
#if defined (TODO)
3362
        /* MPC745P (G3) */
3363
        {
3364
            .name        = "745p",
3365
            .pvr         = CPU_PPC_74xP,
3366
            .pvr_mask    = 0xFFFFF000,
3367
            .insns_flags = PPC_INSNS_7x5,
3368
            .flags       = PPC_FLAGS_7x5,
3369
            .msr_mask    = 0x000000000007FF77,
3370
        },
3371
#endif
3372
        /* MPC750P (G3) */
3373
        {
3374
            .name        = "750p",
3375
            .pvr         = CPU_PPC_74xP,
3376
            .pvr_mask    = 0xFFFFFFFF,
3377
            .insns_flags = PPC_INSNS_7x0,
3378
            .flags       = PPC_FLAGS_7x0,
3379
            .msr_mask    = 0x000000000007FF77,
3380
        },
3381
#if defined (TODO)
3382
        /* MPC755P (G3) */
3383
        {
3384
            .name        = "755p",
3385
            .pvr         = CPU_PPC_74xP,
3386
            .pvr_mask    = 0xFFFFF000,
3387
            .insns_flags = PPC_INSNS_7x5,
3388
            .flags       = PPC_FLAGS_7x5,
3389
            .msr_mask    = 0x000000000007FF77,
3390
        },
3391
#endif
3392
        /* IBM 750CXe (G3 embedded) */
3393
        {
3394
            .name        = "750cxe",
3395
            .pvr         = CPU_PPC_750CXE,
3396
            .pvr_mask    = 0xFFFFFFFF,
3397
            .insns_flags = PPC_INSNS_7x0,
3398
            .flags       = PPC_FLAGS_7x0,
3399
            .msr_mask    = 0x000000000007FF77,
3400
        },
3401
        /* IBM 750FX (G3 embedded) */
3402
        {
3403
            .name        = "750fx",
3404
            .pvr         = CPU_PPC_750FX,
3405
            .pvr_mask    = 0xFFFFFFFF,
3406
            .insns_flags = PPC_INSNS_7x0,
3407
            .flags       = PPC_FLAGS_7x0,
3408
            .msr_mask    = 0x000000000007FF77,
3409
        },
3410
        /* IBM 750GX (G3 embedded) */
3411
        {
3412
            .name        = "750gx",
3413
            .pvr         = CPU_PPC_750GX,
3414
            .pvr_mask    = 0xFFFFFFFF,
3415
            .insns_flags = PPC_INSNS_7x0,
3416
            .flags       = PPC_FLAGS_7x0,
3417
            .msr_mask    = 0x000000000007FF77,
3418
        },
3419
#if defined (TODO)
3420
        /* generic G4 */
3421
        {
3422
            .name        = "G4",
3423
            .pvr         = CPU_PPC_7400,
3424
            .pvr_mask    = 0xFFFF0000,
3425
            .insns_flags = PPC_INSNS_74xx,
3426
            .flags       = PPC_FLAGS_74xx,
3427
            .msr_mask    = 0x000000000205FF77,
3428
        },
3429
#endif
3430
#if defined (TODO)
3431
        /* PowerPC 7400 (G4) */
3432
        {
3433
            .name        = "7400",
3434
            .pvr         = CPU_PPC_7400,
3435
            .pvr_mask    = 0xFFFF0000,
3436
            .insns_flags = PPC_INSNS_74xx,
3437
            .flags       = PPC_FLAGS_74xx,
3438
            .msr_mask    = 0x000000000205FF77,
3439
        },
3440
        {
3441
            .name        = "Max",
3442
            .pvr         = CPU_PPC_7400,
3443
            .pvr_mask    = 0xFFFF0000,
3444
            .insns_flags = PPC_INSNS_74xx,
3445
            .flags       = PPC_FLAGS_74xx,
3446
            .msr_mask    = 0x000000000205FF77,
3447
        },
3448
#endif
3449
#if defined (TODO)
3450
        /* PowerPC 7410 (G4) */
3451
        {
3452
            .name        = "7410",
3453
            .pvr         = CPU_PPC_7410,
3454
            .pvr_mask    = 0xFFFF0000,
3455
            .insns_flags = PPC_INSNS_74xx,
3456
            .flags       = PPC_FLAGS_74xx,
3457
            .msr_mask    = 0x000000000205FF77,
3458
        },
3459
        {
3460
            .name        = "Nitro",
3461
            .pvr         = CPU_PPC_7410,
3462
            .pvr_mask    = 0xFFFF0000,
3463
            .insns_flags = PPC_INSNS_74xx,
3464
            .flags       = PPC_FLAGS_74xx,
3465
            .msr_mask    = 0x000000000205FF77,
3466
        },
3467
#endif
3468
        /* XXX: 7441 */
3469
        /* XXX: 7445 */
3470
        /* XXX: 7447 */
3471
        /* XXX: 7447A */
3472
#if defined (TODO)
3473
        /* PowerPC 7450 (G4) */
3474
        {
3475
            .name        = "7450",
3476
            .pvr         = CPU_PPC_7450,
3477
            .pvr_mask    = 0xFFFF0000,
3478
            .insns_flags = PPC_INSNS_74xx,
3479
            .flags       = PPC_FLAGS_74xx,
3480
            .msr_mask    = 0x000000000205FF77,
3481
        },
3482
        {
3483
            .name        = "Vger",
3484
            .pvr         = CPU_PPC_7450,
3485
            .pvr_mask    = 0xFFFF0000,
3486
            .insns_flags = PPC_INSNS_74xx,
3487
            .flags       = PPC_FLAGS_74xx,
3488
            .msr_mask    = 0x000000000205FF77,
3489
        },
3490
#endif
3491
        /* XXX: 7451 */
3492
#if defined (TODO)
3493
        /* PowerPC 7455 (G4) */
3494
        {
3495
            .name        = "7455",
3496
            .pvr         = CPU_PPC_7455,
3497
            .pvr_mask    = 0xFFFF0000,
3498
            .insns_flags = PPC_INSNS_74xx,
3499
            .flags       = PPC_FLAGS_74xx,
3500
            .msr_mask    = 0x000000000205FF77,
3501
        },
3502
        {
3503
            .name        = "Apollo 6",
3504
            .pvr         = CPU_PPC_7455,
3505
            .pvr_mask    = 0xFFFF0000,
3506
            .insns_flags = PPC_INSNS_74xx,
3507
            .flags       = PPC_FLAGS_74xx,
3508
            .msr_mask    = 0x000000000205FF77,
3509
        },
3510
#endif
3511
#if defined (TODO)
3512
        /* PowerPC 7457 (G4) */
3513
        {
3514
            .name        = "7457",
3515
            .pvr         = CPU_PPC_7457,
3516
            .pvr_mask    = 0xFFFF0000,
3517
            .insns_flags = PPC_INSNS_74xx,
3518
            .flags       = PPC_FLAGS_74xx,
3519
            .msr_mask    = 0x000000000205FF77,
3520
        },
3521
        {
3522
            .name        = "Apollo 7",
3523
            .pvr         = CPU_PPC_7457,
3524
            .pvr_mask    = 0xFFFF0000,
3525
            .insns_flags = PPC_INSNS_74xx,
3526
            .flags       = PPC_FLAGS_74xx,
3527
            .msr_mask    = 0x000000000205FF77,
3528
        },
3529
#endif
3530
#if defined (TODO)
3531
        /* PowerPC 7457A (G4) */
3532
        {
3533
            .name        = "7457A",
3534
            .pvr         = CPU_PPC_7457A,
3535
            .pvr_mask    = 0xFFFF0000,
3536
            .insns_flags = PPC_INSNS_74xx,
3537
            .flags       = PPC_FLAGS_74xx,
3538
            .msr_mask    = 0x000000000205FF77,
3539
        },
3540
        {
3541
            .name        = "Apollo 7 PM",
3542
            .pvr         = CPU_PPC_7457A,
3543
            .pvr_mask    = 0xFFFF0000,
3544
            .insns_flags = PPC_INSNS_74xx,
3545
            .flags       = PPC_FLAGS_74xx,
3546
            .msr_mask    = 0x000000000205FF77,
3547
        },
3548
#endif
3549
        /* 64 bits PowerPC */
3550
#if defined (TARGET_PPC64)
3551
#if defined (TODO)
3552
        /* PowerPC 620 */
3553
        {
3554
            .name        = "620",
3555
            .pvr         = CPU_PPC_620,
3556
            .pvr_mask    = 0xFFFF0000,
3557
            .insns_flags = PPC_INSNS_620,
3558
            .flags       = PPC_FLAGS_620,
3559
            .msr_mask    = 0x800000000005FF73,
3560
        },
3561
#endif
3562
#if defined (TODO)
3563
        /* PowerPC 630 (POWER3) */
3564
        {
3565
            .name        = "630",
3566
            .pvr         = CPU_PPC_630,
3567
            .pvr_mask    = 0xFFFF0000,
3568
            .insns_flags = PPC_INSNS_630,
3569
            .flags       = PPC_FLAGS_630,
3570
            .msr_mask    = xxx,
3571
        }
3572
        {
3573
            .name        = "POWER3",
3574
            .pvr         = CPU_PPC_630,
3575
            .pvr_mask    = 0xFFFF0000,
3576
            .insns_flags = PPC_INSNS_630,
3577
            .flags       = PPC_FLAGS_630,
3578
            .msr_mask    = xxx,
3579
        }
3580
#endif
3581
#if defined (TODO)
3582
        /* PowerPC 631 (Power 3+)*/
3583
        {
3584
            .name        = "631",
3585
            .pvr         = CPU_PPC_631,
3586
            .pvr_mask    = 0xFFFF0000,
3587
            .insns_flags = PPC_INSNS_631,
3588
            .flags       = PPC_FLAGS_631,
3589
            .msr_mask    = xxx,
3590
        },
3591
        {
3592
            .name        = "POWER3+",
3593
            .pvr         = CPU_PPC_631,
3594
            .pvr_mask    = 0xFFFF0000,
3595
            .insns_flags = PPC_INSNS_631,
3596
            .flags       = PPC_FLAGS_631,
3597
            .msr_mask    = xxx,
3598
        },
3599
#endif
3600
#if defined (TODO)
3601
        /* POWER4 */
3602
        {
3603
            .name        = "POWER4",
3604
            .pvr         = CPU_PPC_POWER4,
3605
            .pvr_mask    = 0xFFFF0000,
3606
            .insns_flags = PPC_INSNS_POWER4,
3607
            .flags       = PPC_FLAGS_POWER4,
3608
            .msr_mask    = xxx,
3609
        },
3610
#endif
3611
#if defined (TODO)
3612
        /* POWER4p */
3613
        {
3614
            .name        = "POWER4+",
3615
            .pvr         = CPU_PPC_POWER4P,
3616
            .pvr_mask    = 0xFFFF0000,
3617
            .insns_flags = PPC_INSNS_POWER4,
3618
            .flags       = PPC_FLAGS_POWER4,
3619
            .msr_mask    = xxx,
3620
        },
3621
#endif
3622
#if defined (TODO)
3623
        /* POWER5 */
3624
        {
3625
            .name        = "POWER5",
3626
            .pvr         = CPU_PPC_POWER5,
3627
            .pvr_mask    = 0xFFFF0000,
3628
            .insns_flags = PPC_INSNS_POWER5,
3629
            .flags       = PPC_FLAGS_POWER5,
3630
            .msr_mask    = xxx,
3631
        },
3632
#endif
3633
#if defined (TODO)
3634
        /* POWER5+ */
3635
        {
3636
            .name        = "POWER5+",
3637
            .pvr         = CPU_PPC_POWER5P,
3638
            .pvr_mask    = 0xFFFF0000,
3639
            .insns_flags = PPC_INSNS_POWER5,
3640
            .flags       = PPC_FLAGS_POWER5,
3641
            .msr_mask    = xxx,
3642
        },
3643
#endif
3644
#if defined (TODO)
3645
        /* PowerPC 970 */
3646
        {
3647
            .name        = "970",
3648
            .pvr         = CPU_PPC_970,
3649
            .pvr_mask    = 0xFFFF0000,
3650
            .insns_flags = PPC_INSNS_970,
3651
            .flags       = PPC_FLAGS_970,
3652
            .msr_mask    = 0x900000000204FF36,
3653
        },
3654
#endif
3655
#if defined (TODO)
3656
        /* PowerPC 970FX (G5) */
3657
        {
3658
            .name        = "970fx",
3659
            .pvr         = CPU_PPC_970FX,
3660
            .pvr_mask    = 0xFFFF0000,
3661
            .insns_flags = PPC_INSNS_970FX,
3662
            .flags       = PPC_FLAGS_970FX,
3663
            .msr_mask    = 0x800000000204FF36,
3664
        },
3665
#endif
3666
#if defined (TODO)
3667
        /* RS64 (Apache/A35) */
3668
        /* This one seems to support the whole POWER2 instruction set
3669
         * and the PowerPC 64 one.
3670
         */
3671
        {
3672
            .name        = "RS64",
3673
            .pvr         = CPU_PPC_RS64,
3674
            .pvr_mask    = 0xFFFF0000,
3675
            .insns_flags = PPC_INSNS_RS64,
3676
            .flags       = PPC_FLAGS_RS64,
3677
            .msr_mask    = xxx,
3678
        },
3679
        {
3680
            .name        = "Apache",
3681
            .pvr         = CPU_PPC_RS64,
3682
            .pvr_mask    = 0xFFFF0000,
3683
            .insns_flags = PPC_INSNS_RS64,
3684
            .flags       = PPC_FLAGS_RS64,
3685
            .msr_mask    = xxx,
3686
        },
3687
        {
3688
            .name        = "A35",
3689
            .pvr         = CPU_PPC_RS64,
3690
            .pvr_mask    = 0xFFFF0000,
3691
            .insns_flags = PPC_INSNS_RS64,
3692
            .flags       = PPC_FLAGS_RS64,
3693
            .msr_mask    = xxx,
3694
        },
3695
#endif
3696
#if defined (TODO)
3697
        /* RS64-II (NorthStar/A50) */
3698
        {
3699
            .name        = "RS64-II",
3700
            .pvr         = CPU_PPC_RS64II,
3701
            .pvr_mask    = 0xFFFF0000,
3702
            .insns_flags = PPC_INSNS_RS64,
3703
            .flags       = PPC_FLAGS_RS64,
3704
            .msr_mask    = xxx,
3705
        },
3706
        {
3707
            .name        = "NortStar",
3708
            .pvr         = CPU_PPC_RS64II,
3709
            .pvr_mask    = 0xFFFF0000,
3710
            .insns_flags = PPC_INSNS_RS64,
3711
            .flags       = PPC_FLAGS_RS64,
3712
            .msr_mask    = xxx,
3713
        },
3714
        {
3715
            .name        = "A50",
3716
            .pvr         = CPU_PPC_RS64II,
3717
            .pvr_mask    = 0xFFFF0000,
3718
            .insns_flags = PPC_INSNS_RS64,
3719
            .flags       = PPC_FLAGS_RS64,
3720
            .msr_mask    = xxx,
3721
        },
3722
#endif
3723
#if defined (TODO)
3724
        /* RS64-III (Pulsar) */
3725
        {
3726
            .name        = "RS64-III",
3727
            .pvr         = CPU_PPC_RS64III,
3728
            .pvr_mask    = 0xFFFF0000,
3729
            .insns_flags = PPC_INSNS_RS64,
3730
            .flags       = PPC_FLAGS_RS64,
3731
            .msr_mask    = xxx,
3732
        },
3733
        {
3734
            .name        = "Pulsar",
3735
            .pvr         = CPU_PPC_RS64III,
3736
            .pvr_mask    = 0xFFFF0000,
3737
            .insns_flags = PPC_INSNS_RS64,
3738
            .flags       = PPC_FLAGS_RS64,
3739
            .msr_mask    = xxx,
3740
        },
3741
#endif
3742
#if defined (TODO)
3743
        /* RS64-IV (IceStar/IStar/SStar) */
3744
        {
3745
            .name        = "RS64-IV",
3746
            .pvr         = CPU_PPC_RS64IV,
3747
            .pvr_mask    = 0xFFFF0000,
3748
            .insns_flags = PPC_INSNS_RS64,
3749
            .flags       = PPC_FLAGS_RS64,
3750
            .msr_mask    = xxx,
3751
        },
3752
        {
3753
            .name        = "IceStar",
3754
            .pvr         = CPU_PPC_RS64IV,
3755
            .pvr_mask    = 0xFFFF0000,
3756
            .insns_flags = PPC_INSNS_RS64,
3757
            .flags       = PPC_FLAGS_RS64,
3758
            .msr_mask    = xxx,
3759
        },
3760
        {
3761
            .name        = "IStar",
3762
            .pvr         = CPU_PPC_RS64IV,
3763
            .pvr_mask    = 0xFFFF0000,
3764
            .insns_flags = PPC_INSNS_RS64,
3765
            .flags       = PPC_FLAGS_RS64,
3766
            .msr_mask    = xxx,
3767
        },
3768
        {
3769
            .name        = "SStar",
3770
            .pvr         = CPU_PPC_RS64IV,
3771
            .pvr_mask    = 0xFFFF0000,
3772
            .insns_flags = PPC_INSNS_RS64,
3773
            .flags       = PPC_FLAGS_RS64,
3774
            .msr_mask    = xxx,
3775
        },
3776
#endif
3777
        /* POWER */
3778
#if defined (TODO)
3779
        /* Original POWER */
3780
        {
3781
            .name        = "POWER",
3782
            .pvr         = CPU_POWER,
3783
            .pvr_mask    = 0xFFFF0000,
3784
            .insns_flags = PPC_INSNS_POWER,
3785
            .flags       = PPC_FLAGS_POWER,
3786
            .msr_mask    = xxx,
3787
        },
3788
#endif
3789
#endif /* defined (TARGET_PPC64) */
3790
#if defined (TODO)
3791
        /* POWER2 */
3792
        {
3793
            .name        = "POWER2",
3794
            .pvr         = CPU_POWER2,
3795
            .pvr_mask    = 0xFFFF0000,
3796
            .insns_flags = PPC_INSNS_POWER,
3797
            .flags       = PPC_FLAGS_POWER,
3798
            .msr_mask    = xxx,
3799
        },
3800
#endif
3801
        /* Generic PowerPCs */
3802
#if defined (TODO)
3803
        {
3804
            .name        = "ppc64",
3805
            .pvr         = CPU_PPC_970,
3806
            .pvr_mask    = 0xFFFF0000,
3807
            .insns_flags = PPC_INSNS_PPC64,
3808
            .flags       = PPC_FLAGS_PPC64,
3809
            .msr_mask    = 0xA00000000204FF36,
3810
        },
3811
#endif
3812
        {
3813
            .name        = "ppc32",
3814
            .pvr         = CPU_PPC_604,
3815
            .pvr_mask    = 0xFFFFFFFF,
3816
            .insns_flags = PPC_INSNS_PPC32,
3817
            .flags       = PPC_FLAGS_PPC32,
3818
            .msr_mask    = 0x000000000005FF77,
3819
        },
3820
        /* Fallback */
3821
        {
3822
            .name        = "ppc",
3823
            .pvr         = CPU_PPC_604,
3824
            .pvr_mask    = 0xFFFFFFFF,
3825
            .insns_flags = PPC_INSNS_PPC32,
3826
            .flags       = PPC_FLAGS_PPC32,
3827
            .msr_mask    = 0x000000000005FF77,
3828
        },
3829
    };
3830

    
3831
int ppc_find_by_name (const unsigned char *name, ppc_def_t **def)
3832
{
3833
    int i, ret;
3834

    
3835
    ret = -1;
3836
    *def = NULL;
3837
    for (i = 0; strcmp(ppc_defs[i].name, "ppc") != 0; i++) {
3838
        if (strcasecmp(name, ppc_defs[i].name) == 0) {
3839
            *def = &ppc_defs[i];
3840
            ret = 0;
3841
            break;
3842
        }
3843
    }
3844

    
3845
    return ret;
3846
}
3847

    
3848
int ppc_find_by_pvr (uint32_t pvr, ppc_def_t **def)
3849
{
3850
    int i, ret;
3851

    
3852
    ret = -1;
3853
    *def = NULL;
3854
    for (i = 0; ppc_defs[i].name != NULL; i++) {
3855
        if ((pvr & ppc_defs[i].pvr_mask) ==
3856
            (ppc_defs[i].pvr & ppc_defs[i].pvr_mask)) {
3857
            *def = &ppc_defs[i];
3858
            ret = 0;
3859
            break;
3860
        }
3861
    }
3862

    
3863
    return ret;
3864
}
3865

    
3866
void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
3867
{
3868
    int i;
3869

    
3870
    for (i = 0; ; i++) {
3871
        (*cpu_fprintf)(f, "PowerPC %16s PVR %08x mask %08x\n",
3872
                       ppc_defs[i].name,
3873
                       ppc_defs[i].pvr, ppc_defs[i].pvr_mask);
3874
        if (strcmp(ppc_defs[i].name, "ppc") == 0)
3875
            break;
3876
    }
3877
}