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typedef unsigned char uint8_t;
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typedef unsigned short uint16_t;
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typedef unsigned int uint32_t;
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typedef unsigned long long uint64_t;
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typedef signed char int8_t;
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typedef signed short int16_t;
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typedef signed int int32_t;
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typedef signed long long int64_t;
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#define NULL 0
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#ifdef __i386__
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register int T0 asm("esi");
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register int T1 asm("ebx");
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register int A0 asm("edi");
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register struct CPU86State *env asm("ebp");
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#define FORCE_RET() asm volatile ("ret");
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#endif
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#ifdef __powerpc__
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register int T0 asm("r24");
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register int T1 asm("r25");
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register int A0 asm("r26");
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register struct CPU86State *env asm("r27");
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#define FORCE_RET() asm volatile ("blr");
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#endif
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#ifdef __arm__
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register int T0 asm("r4");
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register int T1 asm("r5");
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register int A0 asm("r6");
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register struct CPU86State *env asm("r7");
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#define FORCE_RET() asm volatile ("mov pc, lr");
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#endif
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#ifdef __mips__
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register int T0 asm("s0");
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register int T1 asm("s1");
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register int A0 asm("s2");
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register struct CPU86State *env asm("s3");
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#define FORCE_RET() asm volatile ("jr $31");
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#endif
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#ifdef __sparc__
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register int T0 asm("l0");
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register int T1 asm("l1");
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register int A0 asm("l2");
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register struct CPU86State *env asm("l3");
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#define FORCE_RET() asm volatile ("retl ; nop");
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#endif
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#ifndef OPPROTO
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#define OPPROTO
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#endif
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#define xglue(x, y) x ## y
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#define glue(x, y) xglue(x, y)
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#define EAX (env->regs[R_EAX])
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#define ECX (env->regs[R_ECX])
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#define EDX (env->regs[R_EDX])
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#define EBX (env->regs[R_EBX])
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#define ESP (env->regs[R_ESP])
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#define EBP (env->regs[R_EBP])
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#define ESI (env->regs[R_ESI])
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#define EDI (env->regs[R_EDI])
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#define PC  (env->pc)
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#define DF  (env->df)
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#define CC_SRC (env->cc_src)
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#define CC_DST (env->cc_dst)
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#define CC_OP (env->cc_op)
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extern int __op_param1, __op_param2, __op_param3;
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#define PARAM1 ((long)(&__op_param1))
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#define PARAM2 ((long)(&__op_param2))
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#define PARAM3 ((long)(&__op_param3))
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#include "cpu-i386.h"
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typedef struct CCTable {
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    int (*compute_all)(void); /* return all the flags */
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    int (*compute_c)(void);  /* return the C flag */
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} CCTable;
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extern CCTable cc_table[];
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uint8_t parity_table[256] = {
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    CC_P, 0, 0, CC_P, 0, CC_P, CC_P, 0,
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    0, CC_P, CC_P, 0, CC_P, 0, 0, CC_P,
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};
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/* modulo 17 table */
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const uint8_t rclw_table[32] = {
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    0, 1, 2, 3, 4, 5, 6, 7, 
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    8, 9,10,11,12,13,14,15,
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   16, 0, 1, 2, 3, 4, 5, 6,
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    7, 8, 9,10,11,12,13,14,
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};
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/* modulo 9 table */
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const uint8_t rclb_table[32] = {
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    0, 1, 2, 3, 4, 5, 6, 7, 
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    8, 0, 1, 2, 3, 4, 5, 6,
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    7, 8, 0, 1, 2, 3, 4, 5, 
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    6, 7, 8, 0, 1, 2, 3, 4,
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};
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/* n must be a constant to be efficient */
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static inline int lshift(int x, int n)
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{
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    if (n >= 0)
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        return x << n;
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    else
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        return x >> (-n);
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}
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/* we define the various pieces of code used by the JIT */
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#define REG EAX
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#define REGNAME _EAX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ECX
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#define REGNAME _ECX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDX
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#define REGNAME _EDX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBX
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#define REGNAME _EBX
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESP
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#define REGNAME _ESP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EBP
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#define REGNAME _EBP
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG ESI
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#define REGNAME _ESI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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#define REG EDI
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#define REGNAME _EDI
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#include "opreg_template.h"
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#undef REG
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#undef REGNAME
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/* operations */
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void OPPROTO op_addl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    T0 += T1;
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    CC_DST = T0;
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}
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void OPPROTO op_orl_T0_T1_cc(void)
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{
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    T0 |= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_adcl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    T0 = T0 + T1 + cc_table[CC_OP].compute_c();
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    CC_DST = T0;
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}
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void OPPROTO op_sbbl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    T0 = T0 - T1 - cc_table[CC_OP].compute_c();
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    CC_DST = T0;
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}
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void OPPROTO op_andl_T0_T1_cc(void)
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{
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    T0 &= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_subl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    T0 -= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_xorl_T0_T1_cc(void)
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{
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    T0 ^= T1;
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    CC_DST = T0;
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}
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void OPPROTO op_cmpl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    CC_DST = T0 - T1;
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}
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void OPPROTO op_notl_T0(void)
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{
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    T0 = ~T0;
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}
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void OPPROTO op_negl_T0_cc(void)
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{
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    CC_SRC = 0;
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    T0 = -T0;
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    CC_DST = T0;
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}
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void OPPROTO op_incl_T0_cc(void)
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{
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    T0++;
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    CC_DST = T0;
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}
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void OPPROTO op_decl_T0_cc(void)
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{
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    T0--;
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    CC_DST = T0;
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}
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void OPPROTO op_testl_T0_T1_cc(void)
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{
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    CC_SRC = T0;
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    CC_DST = T0 & T1;
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}
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/* multiply/divide */
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void OPPROTO op_mulb_AL_T0(void)
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{
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    unsigned int res;
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    res = (uint8_t)EAX * (uint8_t)T0;
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    EAX = (EAX & 0xffff0000) | res;
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    CC_SRC = (res & 0xff00);
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}
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void OPPROTO op_imulb_AL_T0(void)
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{
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    int res;
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    res = (int8_t)EAX * (int8_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    CC_SRC = (res != (int8_t)res);
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}
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void OPPROTO op_mulw_AX_T0(void)
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{
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    unsigned int res;
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    res = (uint16_t)EAX * (uint16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = res >> 16;
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}
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void OPPROTO op_imulw_AX_T0(void)
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{
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    int res;
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    res = (int16_t)EAX * (int16_t)T0;
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    EAX = (EAX & 0xffff0000) | (res & 0xffff);
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    EDX = (EDX & 0xffff0000) | ((res >> 16) & 0xffff);
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_mull_EAX_T0(void)
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{
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    uint64_t res;
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    res = (uint64_t)((uint32_t)EAX) * (uint64_t)((uint32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = res >> 32;
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}
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void OPPROTO op_imull_EAX_T0(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T0);
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    EAX = res;
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    EDX = res >> 32;
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    CC_SRC = (res != (int32_t)res);
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}
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void OPPROTO op_imulw_T0_T1(void)
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{
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    int res;
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    res = (int16_t)T0 * (int16_t)T1;
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    T0 = res;
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    CC_SRC = (res != (int16_t)res);
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}
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void OPPROTO op_imull_T0_T1(void)
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{
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    int64_t res;
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    res = (int64_t)((int32_t)EAX) * (int64_t)((int32_t)T1);
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    T0 = res;
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    CC_SRC = (res != (int32_t)res);
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}
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/* division, flags are undefined */
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/* XXX: add exceptions for overflow & div by zero */
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void OPPROTO op_divb_AL_T0(void)
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{
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    unsigned int num, den, q, r;
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    num = (EAX & 0xffff);
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    den = (T0 & 0xff);
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    q = (num / den) & 0xff;
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    r = (num % den) & 0xff;
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    EAX = (EAX & 0xffff0000) | (r << 8) | q;
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}
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void OPPROTO op_idivb_AL_T0(void)
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{
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    int num, den, q, r;
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    num = (int16_t)EAX;
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    den = (int8_t)T0;
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    q = (num / den) & 0xff;
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    r = (num % den) & 0xff;
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    EAX = (EAX & 0xffff0000) | (r << 8) | q;
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}
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void OPPROTO op_divw_AX_T0(void)
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{
374 7bfdb6d1 bellard
    unsigned int num, den, q, r;
375 7bfdb6d1 bellard
376 7bfdb6d1 bellard
    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
377 7bfdb6d1 bellard
    den = (T0 & 0xffff);
378 7bfdb6d1 bellard
    q = (num / den) & 0xffff;
379 7bfdb6d1 bellard
    r = (num % den) & 0xffff;
380 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | q;
381 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | r;
382 7bfdb6d1 bellard
}
383 7bfdb6d1 bellard
384 7bfdb6d1 bellard
void OPPROTO op_idivw_AX_T0(void)
385 7bfdb6d1 bellard
{
386 7bfdb6d1 bellard
    int num, den, q, r;
387 7bfdb6d1 bellard
388 7bfdb6d1 bellard
    num = (EAX & 0xffff) | ((EDX & 0xffff) << 16);
389 7bfdb6d1 bellard
    den = (int16_t)T0;
390 7bfdb6d1 bellard
    q = (num / den) & 0xffff;
391 7bfdb6d1 bellard
    r = (num % den) & 0xffff;
392 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | q;
393 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | r;
394 7bfdb6d1 bellard
}
395 7bfdb6d1 bellard
396 7bfdb6d1 bellard
void OPPROTO op_divl_EAX_T0(void)
397 7bfdb6d1 bellard
{
398 7bfdb6d1 bellard
    unsigned int den, q, r;
399 7bfdb6d1 bellard
    uint64_t num;
400 7bfdb6d1 bellard
    
401 7bfdb6d1 bellard
    num = EAX | ((uint64_t)EDX << 32);
402 7bfdb6d1 bellard
    den = T0;
403 7bfdb6d1 bellard
    q = (num / den);
404 7bfdb6d1 bellard
    r = (num % den);
405 7bfdb6d1 bellard
    EAX = q;
406 7bfdb6d1 bellard
    EDX = r;
407 7bfdb6d1 bellard
}
408 7bfdb6d1 bellard
409 7bfdb6d1 bellard
void OPPROTO op_idivl_EAX_T0(void)
410 7bfdb6d1 bellard
{
411 7bfdb6d1 bellard
    int den, q, r;
412 7bfdb6d1 bellard
    int16_t num;
413 7bfdb6d1 bellard
    
414 7bfdb6d1 bellard
    num = EAX | ((uint64_t)EDX << 32);
415 7bfdb6d1 bellard
    den = (int16_t)T0;
416 7bfdb6d1 bellard
    q = (num / den);
417 7bfdb6d1 bellard
    r = (num % den);
418 7bfdb6d1 bellard
    EAX = q;
419 7bfdb6d1 bellard
    EDX = r;
420 7bfdb6d1 bellard
}
421 7bfdb6d1 bellard
422 7bfdb6d1 bellard
/* constant load */
423 7bfdb6d1 bellard
424 7bfdb6d1 bellard
void OPPROTO op1_movl_T0_im(void)
425 7bfdb6d1 bellard
{
426 7bfdb6d1 bellard
    T0 = PARAM1;
427 7bfdb6d1 bellard
}
428 7bfdb6d1 bellard
429 7bfdb6d1 bellard
void OPPROTO op1_movl_T1_im(void)
430 7bfdb6d1 bellard
{
431 7bfdb6d1 bellard
    T1 = PARAM1;
432 7bfdb6d1 bellard
}
433 7bfdb6d1 bellard
434 7bfdb6d1 bellard
void OPPROTO op1_movl_A0_im(void)
435 7bfdb6d1 bellard
{
436 7bfdb6d1 bellard
    A0 = PARAM1;
437 7bfdb6d1 bellard
}
438 7bfdb6d1 bellard
439 7bfdb6d1 bellard
/* memory access */
440 7bfdb6d1 bellard
441 7bfdb6d1 bellard
void OPPROTO op_ldub_T0_A0(void)
442 7bfdb6d1 bellard
{
443 7bfdb6d1 bellard
    T0 = ldub((uint8_t *)A0);
444 7bfdb6d1 bellard
}
445 7bfdb6d1 bellard
446 7bfdb6d1 bellard
void OPPROTO op_ldsb_T0_A0(void)
447 7bfdb6d1 bellard
{
448 7bfdb6d1 bellard
    T0 = ldsb((int8_t *)A0);
449 7bfdb6d1 bellard
}
450 7bfdb6d1 bellard
451 7bfdb6d1 bellard
void OPPROTO op_lduw_T0_A0(void)
452 7bfdb6d1 bellard
{
453 7bfdb6d1 bellard
    T0 = lduw((uint8_t *)A0);
454 7bfdb6d1 bellard
}
455 7bfdb6d1 bellard
456 7bfdb6d1 bellard
void OPPROTO op_ldsw_T0_A0(void)
457 7bfdb6d1 bellard
{
458 7bfdb6d1 bellard
    T0 = ldsw((int8_t *)A0);
459 7bfdb6d1 bellard
}
460 7bfdb6d1 bellard
461 7bfdb6d1 bellard
void OPPROTO op_ldl_T0_A0(void)
462 7bfdb6d1 bellard
{
463 7bfdb6d1 bellard
    T0 = ldl((uint8_t *)A0);
464 7bfdb6d1 bellard
}
465 7bfdb6d1 bellard
466 7bfdb6d1 bellard
void OPPROTO op_ldub_T1_A0(void)
467 7bfdb6d1 bellard
{
468 7bfdb6d1 bellard
    T1 = ldub((uint8_t *)A0);
469 7bfdb6d1 bellard
}
470 7bfdb6d1 bellard
471 7bfdb6d1 bellard
void OPPROTO op_ldsb_T1_A0(void)
472 7bfdb6d1 bellard
{
473 7bfdb6d1 bellard
    T1 = ldsb((int8_t *)A0);
474 7bfdb6d1 bellard
}
475 7bfdb6d1 bellard
476 7bfdb6d1 bellard
void OPPROTO op_lduw_T1_A0(void)
477 7bfdb6d1 bellard
{
478 7bfdb6d1 bellard
    T1 = lduw((uint8_t *)A0);
479 7bfdb6d1 bellard
}
480 7bfdb6d1 bellard
481 7bfdb6d1 bellard
void OPPROTO op_ldsw_T1_A0(void)
482 7bfdb6d1 bellard
{
483 7bfdb6d1 bellard
    T1 = ldsw((int8_t *)A0);
484 7bfdb6d1 bellard
}
485 7bfdb6d1 bellard
486 7bfdb6d1 bellard
void OPPROTO op_ldl_T1_A0(void)
487 7bfdb6d1 bellard
{
488 7bfdb6d1 bellard
    T1 = ldl((uint8_t *)A0);
489 7bfdb6d1 bellard
}
490 7bfdb6d1 bellard
491 7bfdb6d1 bellard
void OPPROTO op_stb_T0_A0(void)
492 7bfdb6d1 bellard
{
493 7bfdb6d1 bellard
    stb((uint8_t *)A0, T0);
494 7bfdb6d1 bellard
}
495 7bfdb6d1 bellard
496 7bfdb6d1 bellard
void OPPROTO op_stw_T0_A0(void)
497 7bfdb6d1 bellard
{
498 7bfdb6d1 bellard
    stw((uint8_t *)A0, T0);
499 7bfdb6d1 bellard
}
500 7bfdb6d1 bellard
501 7bfdb6d1 bellard
void OPPROTO op_stl_T0_A0(void)
502 7bfdb6d1 bellard
{
503 7bfdb6d1 bellard
    stl((uint8_t *)A0, T0);
504 7bfdb6d1 bellard
}
505 7bfdb6d1 bellard
506 7bfdb6d1 bellard
/* jumps */
507 7bfdb6d1 bellard
508 7bfdb6d1 bellard
/* indirect jump */
509 7bfdb6d1 bellard
void OPPROTO op_jmp_T0(void)
510 7bfdb6d1 bellard
{
511 7bfdb6d1 bellard
    PC = T0;
512 7bfdb6d1 bellard
}
513 7bfdb6d1 bellard
514 7bfdb6d1 bellard
void OPPROTO op_jmp_im(void)
515 7bfdb6d1 bellard
{
516 7bfdb6d1 bellard
    PC = PARAM1;
517 7bfdb6d1 bellard
}
518 7bfdb6d1 bellard
519 7bfdb6d1 bellard
/* string ops */
520 7bfdb6d1 bellard
521 7bfdb6d1 bellard
#define ldul ldl
522 7bfdb6d1 bellard
523 7bfdb6d1 bellard
#define SHIFT 0
524 367e86e8 bellard
#include "ops_template.h"
525 7bfdb6d1 bellard
#undef SHIFT
526 7bfdb6d1 bellard
527 7bfdb6d1 bellard
#define SHIFT 1
528 367e86e8 bellard
#include "ops_template.h"
529 7bfdb6d1 bellard
#undef SHIFT
530 7bfdb6d1 bellard
531 7bfdb6d1 bellard
#define SHIFT 2
532 367e86e8 bellard
#include "ops_template.h"
533 7bfdb6d1 bellard
#undef SHIFT
534 7bfdb6d1 bellard
535 7bfdb6d1 bellard
/* sign extend */
536 7bfdb6d1 bellard
537 7bfdb6d1 bellard
void OPPROTO op_movsbl_T0_T0(void)
538 7bfdb6d1 bellard
{
539 7bfdb6d1 bellard
    T0 = (int8_t)T0;
540 7bfdb6d1 bellard
}
541 7bfdb6d1 bellard
542 7bfdb6d1 bellard
void OPPROTO op_movzbl_T0_T0(void)
543 7bfdb6d1 bellard
{
544 7bfdb6d1 bellard
    T0 = (uint8_t)T0;
545 7bfdb6d1 bellard
}
546 7bfdb6d1 bellard
547 7bfdb6d1 bellard
void OPPROTO op_movswl_T0_T0(void)
548 7bfdb6d1 bellard
{
549 7bfdb6d1 bellard
    T0 = (int16_t)T0;
550 7bfdb6d1 bellard
}
551 7bfdb6d1 bellard
552 7bfdb6d1 bellard
void OPPROTO op_movzwl_T0_T0(void)
553 7bfdb6d1 bellard
{
554 7bfdb6d1 bellard
    T0 = (uint16_t)T0;
555 7bfdb6d1 bellard
}
556 7bfdb6d1 bellard
557 7bfdb6d1 bellard
void OPPROTO op_movswl_EAX_AX(void)
558 7bfdb6d1 bellard
{
559 7bfdb6d1 bellard
    EAX = (int16_t)EAX;
560 7bfdb6d1 bellard
}
561 7bfdb6d1 bellard
562 7bfdb6d1 bellard
void OPPROTO op_movsbw_AX_AL(void)
563 7bfdb6d1 bellard
{
564 7bfdb6d1 bellard
    EAX = (EAX & 0xffff0000) | ((int8_t)EAX & 0xffff);
565 7bfdb6d1 bellard
}
566 7bfdb6d1 bellard
567 7bfdb6d1 bellard
void OPPROTO op_movslq_EDX_EAX(void)
568 7bfdb6d1 bellard
{
569 7bfdb6d1 bellard
    EDX = (int32_t)EAX >> 31;
570 7bfdb6d1 bellard
}
571 7bfdb6d1 bellard
572 7bfdb6d1 bellard
void OPPROTO op_movswl_DX_AX(void)
573 7bfdb6d1 bellard
{
574 7bfdb6d1 bellard
    EDX = (EDX & 0xffff0000) | (((int16_t)EAX >> 15) & 0xffff);
575 7bfdb6d1 bellard
}
576 7bfdb6d1 bellard
577 7bfdb6d1 bellard
/* push/pop */
578 7bfdb6d1 bellard
/* XXX: add 16 bit operand/16 bit seg variants */
579 7bfdb6d1 bellard
580 7bfdb6d1 bellard
void op_pushl_T0(void)
581 7bfdb6d1 bellard
{
582 7bfdb6d1 bellard
    uint32_t offset;
583 7bfdb6d1 bellard
    offset = ESP - 4;
584 7bfdb6d1 bellard
    stl((void *)offset, T0);
585 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
586 7bfdb6d1 bellard
    ESP = offset;
587 7bfdb6d1 bellard
}
588 7bfdb6d1 bellard
589 7bfdb6d1 bellard
void op_pushl_T1(void)
590 7bfdb6d1 bellard
{
591 7bfdb6d1 bellard
    uint32_t offset;
592 7bfdb6d1 bellard
    offset = ESP - 4;
593 7bfdb6d1 bellard
    stl((void *)offset, T1);
594 7bfdb6d1 bellard
    /* modify ESP after to handle exceptions correctly */
595 7bfdb6d1 bellard
    ESP = offset;
596 7bfdb6d1 bellard
}
597 7bfdb6d1 bellard
598 7bfdb6d1 bellard
void op_popl_T0(void)
599 7bfdb6d1 bellard
{
600 7bfdb6d1 bellard
    T0 = ldl((void *)ESP);
601 7bfdb6d1 bellard
    ESP += 4;
602 7bfdb6d1 bellard
}
603 7bfdb6d1 bellard
604 7bfdb6d1 bellard
void op_addl_ESP_im(void)
605 7bfdb6d1 bellard
{
606 7bfdb6d1 bellard
    ESP += PARAM1;
607 7bfdb6d1 bellard
}
608 367e86e8 bellard
609 367e86e8 bellard
/* flags handling */
610 367e86e8 bellard
611 367e86e8 bellard
/* slow jumps cases (compute x86 flags) */
612 367e86e8 bellard
void OPPROTO op_jo_cc(void)
613 367e86e8 bellard
{
614 367e86e8 bellard
    int eflags;
615 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
616 367e86e8 bellard
    if (eflags & CC_O)
617 367e86e8 bellard
        PC += PARAM1;
618 367e86e8 bellard
    else
619 367e86e8 bellard
        PC += PARAM2;
620 367e86e8 bellard
}
621 367e86e8 bellard
622 367e86e8 bellard
void OPPROTO op_jb_cc(void)
623 367e86e8 bellard
{
624 367e86e8 bellard
    if (cc_table[CC_OP].compute_c())
625 367e86e8 bellard
        PC += PARAM1;
626 367e86e8 bellard
    else
627 367e86e8 bellard
        PC += PARAM2;
628 367e86e8 bellard
}
629 367e86e8 bellard
630 367e86e8 bellard
void OPPROTO op_jz_cc(void)
631 367e86e8 bellard
{
632 367e86e8 bellard
    int eflags;
633 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
634 367e86e8 bellard
    if (eflags & CC_Z)
635 367e86e8 bellard
        PC += PARAM1;
636 367e86e8 bellard
    else
637 367e86e8 bellard
        PC += PARAM2;
638 367e86e8 bellard
}
639 367e86e8 bellard
640 367e86e8 bellard
void OPPROTO op_jbe_cc(void)
641 367e86e8 bellard
{
642 367e86e8 bellard
    int eflags;
643 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
644 367e86e8 bellard
    if (eflags & (CC_Z | CC_C))
645 367e86e8 bellard
        PC += PARAM1;
646 367e86e8 bellard
    else
647 367e86e8 bellard
        PC += PARAM2;
648 367e86e8 bellard
}
649 367e86e8 bellard
650 367e86e8 bellard
void OPPROTO op_js_cc(void)
651 367e86e8 bellard
{
652 367e86e8 bellard
    int eflags;
653 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
654 367e86e8 bellard
    if (eflags & CC_S)
655 367e86e8 bellard
        PC += PARAM1;
656 367e86e8 bellard
    else
657 367e86e8 bellard
        PC += PARAM2;
658 367e86e8 bellard
}
659 367e86e8 bellard
660 367e86e8 bellard
void OPPROTO op_jp_cc(void)
661 367e86e8 bellard
{
662 367e86e8 bellard
    int eflags;
663 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
664 367e86e8 bellard
    if (eflags & CC_P)
665 367e86e8 bellard
        PC += PARAM1;
666 367e86e8 bellard
    else
667 367e86e8 bellard
        PC += PARAM2;
668 367e86e8 bellard
}
669 367e86e8 bellard
670 367e86e8 bellard
void OPPROTO op_jl_cc(void)
671 367e86e8 bellard
{
672 367e86e8 bellard
    int eflags;
673 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
674 367e86e8 bellard
    if ((eflags ^ (eflags >> 4)) & 0x80)
675 367e86e8 bellard
        PC += PARAM1;
676 367e86e8 bellard
    else
677 367e86e8 bellard
        PC += PARAM2;
678 367e86e8 bellard
}
679 367e86e8 bellard
680 367e86e8 bellard
void OPPROTO op_jle_cc(void)
681 367e86e8 bellard
{
682 367e86e8 bellard
    int eflags;
683 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
684 367e86e8 bellard
    if (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z))
685 367e86e8 bellard
        PC += PARAM1;
686 367e86e8 bellard
    else
687 367e86e8 bellard
        PC += PARAM2;
688 367e86e8 bellard
}
689 367e86e8 bellard
690 367e86e8 bellard
/* slow set cases (compute x86 flags) */
691 367e86e8 bellard
void OPPROTO op_seto_T0_cc(void)
692 367e86e8 bellard
{
693 367e86e8 bellard
    int eflags;
694 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
695 367e86e8 bellard
    T0 = (eflags >> 11) & 1;
696 367e86e8 bellard
}
697 367e86e8 bellard
698 367e86e8 bellard
void OPPROTO op_setb_T0_cc(void)
699 367e86e8 bellard
{
700 367e86e8 bellard
    T0 = cc_table[CC_OP].compute_c();
701 367e86e8 bellard
}
702 367e86e8 bellard
703 367e86e8 bellard
void OPPROTO op_setz_T0_cc(void)
704 367e86e8 bellard
{
705 367e86e8 bellard
    int eflags;
706 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
707 367e86e8 bellard
    T0 = (eflags >> 6) & 1;
708 367e86e8 bellard
}
709 367e86e8 bellard
710 367e86e8 bellard
void OPPROTO op_setbe_T0_cc(void)
711 367e86e8 bellard
{
712 367e86e8 bellard
    int eflags;
713 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
714 367e86e8 bellard
    T0 = (eflags & (CC_Z | CC_C)) != 0;
715 367e86e8 bellard
}
716 367e86e8 bellard
717 367e86e8 bellard
void OPPROTO op_sets_T0_cc(void)
718 367e86e8 bellard
{
719 367e86e8 bellard
    int eflags;
720 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
721 367e86e8 bellard
    T0 = (eflags >> 7) & 1;
722 367e86e8 bellard
}
723 367e86e8 bellard
724 367e86e8 bellard
void OPPROTO op_setp_T0_cc(void)
725 367e86e8 bellard
{
726 367e86e8 bellard
    int eflags;
727 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
728 367e86e8 bellard
    T0 = (eflags >> 2) & 1;
729 367e86e8 bellard
}
730 367e86e8 bellard
731 367e86e8 bellard
void OPPROTO op_setl_T0_cc(void)
732 367e86e8 bellard
{
733 367e86e8 bellard
    int eflags;
734 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
735 367e86e8 bellard
    T0 = ((eflags ^ (eflags >> 4)) >> 7) & 1;
736 367e86e8 bellard
}
737 367e86e8 bellard
738 367e86e8 bellard
void OPPROTO op_setle_T0_cc(void)
739 367e86e8 bellard
{
740 367e86e8 bellard
    int eflags;
741 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
742 367e86e8 bellard
    T0 = (((eflags ^ (eflags >> 4)) & 0x80) || (eflags & CC_Z)) != 0;
743 367e86e8 bellard
}
744 367e86e8 bellard
745 367e86e8 bellard
void OPPROTO op_xor_T0_1(void)
746 367e86e8 bellard
{
747 367e86e8 bellard
    T0 ^= 1;
748 367e86e8 bellard
}
749 367e86e8 bellard
750 367e86e8 bellard
void OPPROTO op_set_cc_op(void)
751 367e86e8 bellard
{
752 367e86e8 bellard
    CC_OP = PARAM1;
753 367e86e8 bellard
}
754 367e86e8 bellard
755 367e86e8 bellard
void OPPROTO op_movl_eflags_T0(void)
756 367e86e8 bellard
{
757 367e86e8 bellard
    CC_SRC = T0;
758 367e86e8 bellard
    DF = 1 - (2 * ((T0 >> 10) & 1));
759 367e86e8 bellard
}
760 367e86e8 bellard
761 367e86e8 bellard
/* XXX: compute only O flag */
762 367e86e8 bellard
void OPPROTO op_movb_eflags_T0(void)
763 367e86e8 bellard
{
764 367e86e8 bellard
    int of;
765 367e86e8 bellard
    of = cc_table[CC_OP].compute_all() & CC_O;
766 367e86e8 bellard
    CC_SRC = T0 | of;
767 367e86e8 bellard
}
768 367e86e8 bellard
769 367e86e8 bellard
void OPPROTO op_movl_T0_eflags(void)
770 367e86e8 bellard
{
771 367e86e8 bellard
    T0 = cc_table[CC_OP].compute_all();
772 367e86e8 bellard
    T0 |= (DF & DIRECTION_FLAG);
773 367e86e8 bellard
}
774 367e86e8 bellard
775 367e86e8 bellard
void OPPROTO op_cld(void)
776 367e86e8 bellard
{
777 367e86e8 bellard
    DF = 1;
778 367e86e8 bellard
}
779 367e86e8 bellard
780 367e86e8 bellard
void OPPROTO op_std(void)
781 367e86e8 bellard
{
782 367e86e8 bellard
    DF = -1;
783 367e86e8 bellard
}
784 367e86e8 bellard
785 367e86e8 bellard
void OPPROTO op_clc(void)
786 367e86e8 bellard
{
787 367e86e8 bellard
    int eflags;
788 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
789 367e86e8 bellard
    eflags &= ~CC_C;
790 367e86e8 bellard
    CC_SRC = eflags;
791 367e86e8 bellard
}
792 367e86e8 bellard
793 367e86e8 bellard
void OPPROTO op_stc(void)
794 367e86e8 bellard
{
795 367e86e8 bellard
    int eflags;
796 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
797 367e86e8 bellard
    eflags |= CC_C;
798 367e86e8 bellard
    CC_SRC = eflags;
799 367e86e8 bellard
}
800 367e86e8 bellard
801 367e86e8 bellard
void OPPROTO op_cmc(void)
802 367e86e8 bellard
{
803 367e86e8 bellard
    int eflags;
804 367e86e8 bellard
    eflags = cc_table[CC_OP].compute_all();
805 367e86e8 bellard
    eflags ^= CC_C;
806 367e86e8 bellard
    CC_SRC = eflags;
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}
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static int compute_all_eflags(void)
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{
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    return CC_SRC;
812 367e86e8 bellard
}
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static int compute_c_eflags(void)
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{
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    return CC_SRC & CC_C;
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}
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static int compute_c_mul(void)
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{
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    int cf;
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    cf = (CC_SRC != 0);
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    return cf;
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}
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static int compute_all_mul(void)
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{
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    int cf, pf, af, zf, sf, of;
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    cf = (CC_SRC != 0);
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    pf = 0; /* undefined */
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    af = 0; /* undefined */
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    zf = 0; /* undefined */
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    sf = 0; /* undefined */
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    of = cf << 11;
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    return cf | pf | af | zf | sf | of;
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}
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CCTable cc_table[CC_OP_NB] = {
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    [CC_OP_DYNAMIC] = { /* should never happen */ },
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    [CC_OP_EFLAGS] = { compute_all_eflags, compute_c_eflags },
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    [CC_OP_MUL] = { compute_all_mul, compute_c_mul },
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    [CC_OP_ADDB] = { compute_all_addb, compute_c_addb },
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    [CC_OP_ADDW] = { compute_all_addw, compute_c_addw  },
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    [CC_OP_ADDL] = { compute_all_addl, compute_c_addl  },
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    [CC_OP_SUBB] = { compute_all_subb, compute_c_subb  },
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    [CC_OP_SUBW] = { compute_all_subw, compute_c_subw  },
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    [CC_OP_SUBL] = { compute_all_subl, compute_c_subl  },
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    [CC_OP_LOGICB] = { compute_all_logicb, compute_c_logicb },
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    [CC_OP_LOGICW] = { compute_all_logicw, compute_c_logicw },
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    [CC_OP_LOGICL] = { compute_all_logicl, compute_c_logicl },
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    [CC_OP_INCB] = { compute_all_incb, compute_c_incb },
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    [CC_OP_INCW] = { compute_all_incw, compute_c_incw },
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    [CC_OP_INCL] = { compute_all_incl, compute_c_incl },
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    [CC_OP_DECB] = { compute_all_decb, compute_c_incb },
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    [CC_OP_DECW] = { compute_all_decw, compute_c_incw },
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    [CC_OP_DECL] = { compute_all_decl, compute_c_incl },
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    [CC_OP_SHLB] = { compute_all_shlb, compute_c_shlb },
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    [CC_OP_SHLW] = { compute_all_shlw, compute_c_shlw },
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    [CC_OP_SHLL] = { compute_all_shll, compute_c_shll },
868 367e86e8 bellard
};