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# Date Author Comment
605a6aed 05/15/2011 01:22 am Peter Maydell

target-arm: Fix VMLA, VMLS, VNMLS, VNMLA handling of NaNs

Correct handling of NaNs for VFP VMLA, VMLS, VNMLS and VNMLA requires that
we implement the set of negations and additions specified by the ARM ARM;
plausible looking simplifications like turning (-A + B) into (B - A) or...

1301f322 05/08/2011 12:02 pm Stefan Weil

Fix typos in comments (neccessary -> necessary)

Signed-off-by: Stefan Weil <>
Signed-off-by: Stefan Hajnoczi <>

a1c7273b 05/08/2011 12:02 pm Stefan Weil

Fix typos in comments and code (occured -> occurred and related)

The code changed here is an unused data type name (evt_flush_occurred).

Signed-off-by: Stefan Weil <>
Signed-off-by: Stefan Hajnoczi <>

a7d3970d 04/27/2011 09:14 pm Peter Maydell

target-arm: Don't update base register on abort in Thumb T1 LDM

Make sure the base register isn't updated if it is in the load list
for a Thumb LDM (T1 encoding) which aborts partway through the load.

Signed-off-by: Peter Maydell <>...

5856d44e 04/27/2011 09:13 pm YuYeon Oh

target-arm: fix LDMIA bug on page boundary
target-arm: fix LDMIA bug on page boundary

When consecutive memory locations are on page boundary, a base register may be
loaded before page fault occurs. After page fault handling, it losts the memory
location information. To solve this problem, loading a base register has to put back....

f2dd89d0 04/25/2011 11:10 pm Peter Maydell

target-arm: Handle UNDEF cases for Neon VLD/VST multiple-structures

Correctly UNDEF for Neon VLD/VST "multiple structures" forms where the
align field is not valid.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

93262b16 04/25/2011 11:10 pm Peter Maydell

target-arm: Handle UNDEFs for Neon single element load/stores

Handle the UNDEF and UNPREDICTABLE cases for Neon "single element to
one lane" VLD and "single element from one lane" VST.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

e87b7cb0 04/20/2011 11:33 am Stefan Weil

Remove unused function parameters from gen_pc_load and rename the function

Function gen_pc_load was introduced in commit
d2856f1ad4c259e5766847c49acbb4e390731bd4.
The only reason for parameter searched_pc was
a debug statement in target-i386/translate.c....

7b59220e 04/17/2011 09:41 pm Lluís

move helpers.h to helper.h

This provides a consistent naming scheme across all targets.

Signed-off-by: Lluís Vilanova <>
Signed-off-by: Aurelien Jarno <>

7d80fee5 04/13/2011 12:33 am Peter Maydell

target-arm: Handle UNDEF cases for Neon invalid modified-immediates

For Neon "one register and a modified immediate value" forms, the
combination op=1 cmode=1111 is unallocated and should UNDEF.
All instructions of this form also UNDEF if Q 1 and Vd&lt;0&gt; 1....

695272dc 04/13/2011 12:33 am Peter Maydell

target-arm: Handle UNDEF cases for Neon 3-regs-different-widths

Add missing UNDEF checks for instructions in the Neon "3 registers of
different widths" data processing space.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

3e3326df 04/13/2011 12:33 am Peter Maydell

target-arm: Handle UNDEF cases for Neon 2 regs + scalar forms

Add missing checks for cases which must UNDEF in the Neon "2 registers and
a scalar" data processing instruction space.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

52579ea1 04/13/2011 12:33 am Peter Maydell

target-arm: Handle UNDEF cases for VEXT

VEXT must UNDEF if Q 1 && (Vd&lt;0&gt; 1 || Vr<0> 1 || Vm&lt;0&gt; 1)

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

600b828c 04/13/2011 12:33 am Peter Maydell

target-arm: Simplify checking of size field in Neon 2reg-misc forms

Many of the Neon "2 register misc" instruction forms require invalid
size fields to cause the instruction to UNDEF. Pull this information
out into an array; this simplifies the code and also means we can do...

fc2a9b37 04/13/2011 12:33 am Peter Maydell

target-arm: Handle UNDEF cases for Neon 2 register misc forms

Add missing UNDEF checks for Neon "two register miscellaneous" forms: * all instructions except VMOVN,VQMOVN must UNDEF
if Q==1 && (Vd<0> 1 || Vm&lt;0&gt; 1) * VMOVN,VQMOVN,VCVT.F16.F32 UNDEF if Q 1 || Vm&lt;0&gt; 1...

56907d77 04/13/2011 12:33 am Peter Maydell

target-arm: Treat UNPREDICTABLE VTBL, VTBX case as UNDEF

Catch the UNPREDICTABLE case for Neon VTBL,VTBX, and UNDEF it
rather than allowing the helper function to index off the end
of the register file.

Signed-off-by: Peter Maydell <>...

133da6aa 04/13/2011 12:33 am Juha Riihimäki

target-arm: Handle UNDEF cases for VDUP (scalar)

Handle the UNDEF cases for VDUP:
imm4 x000
Q 1 && Vd<0> == 1

Signed-off-by: Juha Riihimäki <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

2bc70834 04/13/2011 12:33 am Peter Maydell

target-arm: Collapse VSRI case into VSHL, VSLI

Collapse some switch cases for VSRI into those for VSHL, VSLI,
since the bodies are the same. (This is not completely obvious
for the size < 3 case, but since for VSRI we know U=1 the
GEN_NEON_INTEGER_OP() expansion is equivalent to the open-coded...

62698be3 04/12/2011 10:51 pm Peter Maydell

target-arm: Use lookup table for size check on Neon 3-reg-same insns

Simplify the checks for invalid size values for the Neon "three registers
of the same size" instruction forms (and add them where they were missing)
by using a lookup table.

This includes adding symbolic constants for the op values in this space,...

25f84f79 04/12/2011 10:51 pm Peter Maydell

target-arm: Handle UNDEF cases for Neon 3-regs-same insns

Correct the handling of UNDEF cases for the NEON "3 registers same
size" forms, by adding missing checks and rationalising some others
so they are done early enough to avoid leaking TCG temporaries....

a5a14945 04/12/2011 10:51 pm Juha Riihimäki

target-arm: Simplify three-register pairwise code

Since we know that the case of (pairwise && q) has been caught
earlier, we can simplify the register setup code for each pass
in the three-register-same-size Neon loop.

Signed-off-by: Juha Riihimäki <>...

cc13115b 04/12/2011 10:51 pm Peter Maydell

target-arm: Handle UNDEF cases for Neon "2 regs and shift" insns

Correctly handle all the UNDEF cases for Neon instructions of the
"2 registers and shift" form, and make sure that we check for these
cases early enough not to leak TCG temporaries.

Signed-off-by: Peter Maydell <>...

be5e7a76 04/10/2011 01:53 am Dmitry Eremin-Solenikov

arm: basic support for ARMv4/ARMv4T emulation

Currently target-arm/ assumes at least ARMv5 core. Add support for
handling also ARMv4/ARMv4T. This changes the following instructions:

BX

BKPT, BLX, CDP2, CLZ, LDC2, LDRD, MCRR, MCRR2, MRRC, MCRR, MRC2, MRRC,...

4b4a72e5 04/10/2011 01:45 am Stefan Weil

Fix conversions from pointer to tcg_target_long

tcg_gen_exit_tb takes a parameter of type tcg_target_long,
so the type casts of pointer to long should be replaced by
type casts of pointer to tcg_target_long (suggested by Blue Swirl).

These changes are needed for build environments where...

947a2fa2 04/04/2011 09:18 pm Peter Maydell

target-arm: Use global env in iwmmxt_helper.c helpers

Use the global 'env' variable in the helper functions in iwmmxt_helper.c.
This means we don't need to pass env as an argument to them any more.

Signed-off-by: Peter Maydell <>...

2a3f75b4 04/04/2011 09:18 pm Peter Maydell

target-arm: Use global env in neon_helper.c helpers

Use the global 'env' variable in the helper functions in neon_helper.c.
This means we don't need to pass env as an argument to them any more.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

0e326109 04/03/2011 06:19 pm Peter Maydell

target-arm: Fix VCLE.F32 #0, VCLT.F32 #0 NaN handling

Implementing the floating-point versions of VCLE #0 and VCLT #0 by
doing a GT comparison and inverting the result gives the wrong
result if the input is a NaN. Implement as a GT comparison with the
operands swapped instead....

8e18cde3 04/01/2011 11:33 pm Peter Maydell

target-arm: Fix VLD of single element to all lanes

Fix several bugs in VLD of single element to all lanes:

The "single element to all lanes" form of VLD1 differs from those for
VLD2, VLD3 and VLD4 in that bit 5 indicates whether the loaded element
should be written to one or two Dregs (rather than being a register...

e318a60b 04/01/2011 11:33 pm Peter Maydell

target-arm: Don't leak TCG temp for UNDEFs in Neon load/store space

Move the allocation and freeing of the TCG temp used for the address for
Neon load/store instructions so that we don't allocate the temporary
until we've done enough decoding to know that the instruction is not...

7d2aabe2 03/22/2011 08:56 am Peter Maydell

target-arm: Fix TCG temporary leaks for scalar VMULL

Fix a TCG temporary leak when translating 32-bit scalar VMULL.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

e1d177b9 03/22/2011 08:56 am Peter Maydell

target-arm: Set Q bit for overflow in SMUAD and SMLAD

SMUAD and SMLAD are supposed to set the Q bit if the addition of
the two 16x16 multiply products and optional accumulator overflows
considered as a signed value. However we were only doing this check
for the addition of the accumulator, not when adding the products,...

2a0308c5 03/22/2011 08:52 am Peter Maydell

target-arm: Fix UNDEF cases in Thumb load/store

Decode of Thumb load/store was merging together the cases of 'bit 11==0'
(reg+reg LSL imm) and 'bit 11==1' (reg+imm). This happens to work for
valid instruction patterns but meant that we would not UNDEF for the...

ca27c052 03/07/2011 10:46 am Peter Maydell

target-arm: Implement a minimal set of cp14 debug registers

Newer ARM kernels try to probe for whether the CPU has hardware breakpoint
support. For this to work QEMU has to implement a minimal set of the cp14
debug registers. The architecture requires v7 cores to implement debug...

3849902c 03/07/2011 10:26 am Peter Maydell

target-arm: Use TCG temporary leak debugging facilities

Use the new TCG temporary leak debugging facilities to
check that each ARM instruction does not leak temporaries.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

7d1b0095 03/07/2011 10:26 am Peter Maydell

target-arm: Remove ad-hoc leak checking code

This commit removes the ad-hoc resource leak checking code from
target-arm. This includes replacing all uses of new_tmp() with
tcg_temp_new_i32() and all uses of dead_tmp() with
tcg_temp_free_i32().

Signed-off-by: Peter Maydell <>...

29501f1b 03/07/2011 12:30 am Peter Maydell

target-arm: Set carry flag correctly for Thumb2 ORNS

The code for Thumb2 ORNS (or negated and set flags) was trashing
a TCG input register which was needed later for use in calculating
flags, with the effect that the carry flag was always set with
the wrong sense. Fix this by using the TCG orc op instead of...

8387da81 03/06/2011 09:28 pm Peter Maydell

target-arm: Handle VMOV between two core and VFP single regs

Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
pair of VFP single precision registers):

  • An incorrect condition meant these instruction patterns were being...
cc688901 03/06/2011 09:20 pm Peter Maydell

target-arm: Don't decode old cp15 WFI instructions on v7 cores

In v7 of the ARM architecture, WFI (wait for interrupt) is a first-class
instruction, but in previous versions this functionality was provided
via a cp15 coprocessor register. Add correct feature checks to the...

92cdfaeb 02/21/2011 04:39 pm Peter Maydell

target-arm: Fix shift by immediate and narrow where src, dest overlap

For Neon shifts by immediate and narrow, correctly handle the case
where the source registers and the destination registers overlap
(the second pass should use the original register contents, not the...

c33171c7 02/21/2011 04:39 pm Peter Maydell

target-arm: Refactor to pull narrowing decode into separate function

Pull the code which decodes narrowing operations as being either
signed/unsigned saturate or plain out into its own function.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

b408a9b0 02/20/2011 06:43 pm Christophe Lyon

target-arm: fix Neon VQSHRN and VSHRN.

Call the normal shift helpers instead of the rounding ones.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

0b36f4cd 02/20/2011 06:43 pm Christophe Lyon

target-arm: fix decoding of Neon 64 bit shifts.

Fix decoding of 64 bits variants of VSHRN, VRSHRN, VQSHRN, VQSHRUN,
VQRSHRN, VQRSHRUN, taking into account whether inputs are unsigned
or not.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>...

d68a6f3a 02/20/2011 06:31 pm Peter Maydell

target-arm: Move Neon VZIP to helper functions

Move the implementation of the Neon VUZP unzip instruction from inline
code to helper functions. (At 50+ TCG ops it was well over the
recommended limit for coding inline.) The helper implementations also
give the correct answers where the inline implementation did not....

02acedf9 02/20/2011 06:31 pm Peter Maydell

target-arm: Move Neon VUZP to helper functions

Move the implementation of the Neon VUZP unzip instruction from inline
code to helper functions. (At 50+ TCG ops it was well over the
recommended limit for coding inline.) The helper implementations also
fix the handling of the quadword version of the instruction....

f06053e3 02/20/2011 06:30 pm Juha Riihimäki

target-arm: Correct conversion of Thumb Neon dp encodings into ARM

We handle Thumb Neon data processing instructions by converting them
into the equivalent ARM encoding, as the two are very close. However
the ARM encoding should have bit 28 set, not clear. This wasn't causing...

4dc064e6 02/20/2011 06:28 pm Peter Maydell

target-arm: Fix Neon VQDMLSL instruction

For VQDMLSL, negation has to occur after saturation, not before.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

ebcd88ce 02/20/2011 06:28 pm Peter Maydell

target-arm: Refactor handling of VQDMULL

Refactor the handling of VQDMULL so that it is dealt with in
its own if() case rather than together with the accumulating
instructions.

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

e5ca24cb 02/20/2011 06:26 pm Peter Maydell

target-arm: Implement VMULL.P8

Implement VMULL.P8 (the 32x32->64 version of the polynomial multiply
instruction).

Signed-off-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

2d981da7 02/10/2011 07:28 pm Peter Maydell

target-arm: Use standard FPSCR for Neon half-precision operations

The Neon half-precision conversion operations (VCVT.F16.F32 and
VCVT.F32.F16) use ARM standard floating-point arithmetic, unlike
the VFP versions (VCVTB and VCVTT).

Signed-off-by: Peter Maydell <>...

923e6509 02/09/2011 08:48 pm Christophe Lyon

target-arm: implement vsli.64, vsri.64

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

acdf01ef 02/09/2011 08:47 pm Christophe Lyon

target-arm: fix VSHLL Neon instruction.

Fix bit mask used when widening the result of shift on narrow input.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

af1bbf30 02/09/2011 08:37 pm Juha Riihimäki

target-arm: Fix VQMOVUN Neon instruction.

VQMOVUN does a signed-to-unsigned saturating conversion. This is
different from both the signed-to-signed and unsigned-to-unsigned
conversions already implemented, so we need a new set of helper
functions (neon_unarrow_sat*)....

3d185e5d 02/04/2011 10:30 pm Peter Maydell

target-arm: Fix decoding of preload and memory hint space

Correct the decoding of the ARM preload and memory hint space,
by adding decoding of PLI, PLDW and the v7MP unallocated hint
space. This commit also corrects a slightly overexuberant
decoding of PLD which was not checking that bit 4...

a2fdc890 02/04/2011 10:30 pm Peter Maydell

target-arm: Fix decoding of Thumb preload and hint space

Refine the decoding of the Thumb preload and hint space, so we
UNDEF on the patterns that are supposed to UNDEF rather than NOP.
We also move the tests for this space earlier, so we don't emit
harmless but unnecessary address generation code for preload...

72902672 02/04/2011 09:57 pm Christophe Lyon

Set the right overflow bit for neon 32 and 64 bit saturating add/sub.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

5371cb81 02/04/2011 09:48 pm Christophe Lyon

target-arm: Fix Neon vsra instructions.

This patch fixes the errors reported by my tests in VSRA.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

40d3c433 01/26/2011 03:30 pm Christophe Lyon

Support saturation with shift=0.

This patch fixes corner-case saturations, when the target range is
zero. It merely removes the guard against (sh == 0), and makes:
_ssat(0x87654321, 1) return 0xffffffff and set the saturation flag
_usat(0x87654321, 0) return 0 and set the saturation flag...

c6067f04 01/26/2011 03:30 pm Christophe Lyon

target-arm: Fix garbage collection of temporaries in Neon emulation.

Fix garbage collection of temporaries in Neon emulation.

Signed-off-by: Christophe Lyon <>
Reviewed-by: Peter Maydell <>
Signed-off-by: Aurelien Jarno <>

0fad6efc 01/26/2011 03:30 pm Peter Maydell

target-arm: Fix loading of scalar value for Neon multiply-by-scalar

Fix the register and part of register we get the scalar from in
the various "multiply vector by scalar" ops (VMUL by scalar
and friends).

Signed-off-by: Peter Maydell <>...

5642463a 01/18/2011 04:23 pm Peter Maydell

target-arm: Log instruction start in TCG code

Add support for logging the start of instructions in TCG
code debug dumps for ARM targets.

Signed-off-by: Peter Maydell <>
Signed-off-by: Edgar E. Iglesias <>

5df8bac1 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with VFP-enabled from TB flags, not CPUState

When translating code, whether the VFP unit is enabled for this TB
is stored in a bit in the TB flags. Use this rather than incorrectly
reading the FPEXC from the CPUState passed to translation....

69d1fc22 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with VFP len/stride from TB flags, not CPUState

When translating, the VFP vector length and stride for this TB are encoded
in the TB flags; the CPUState copies may be different and must not be used.

Signed-off-by: Peter Maydell <>...

7204ab88 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with Thumb state from TB flags, not CPUState

The Thumb/ARM state for the TB being translated should come from
the TB flags, not the CPUState.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>...

98eac7ca 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with condexec bits from TB flags, not CPUState

When translating, the condexec bits for the TB are in the TB flags;
the CPUState condexec bits may be different.

This patch fixes https://bugs.launchpad.net/bugs/604872 where we might
segfault if we took an exception in the middle of a TB with an IT...

61f74d6a 01/14/2011 09:39 pm Peter Maydell

target-arm: Translate with user-state from TB flags, not CPUState

When translating, get the user/priv state from the TB flags, not
the CPUState.

Signed-off-by: Peter Maydell <>
Reviewed-by: Aurelien Jarno <>
Signed-off-by: Aurelien Jarno <>

5de3a9d3 01/14/2011 09:39 pm Peter Maydell

target-arm: Remove redundant setting of IT bits before Thumb SWI

Remove a redundant call to gen_set_condexec() in the translation of Thumb
mode SWI. (SWI and WFI generate "exceptions" which happen after the
execution of the instruction, ie when PC and IT bits have updated....

bc4a0de0 01/14/2011 09:39 pm Peter Maydell

target-arm: Refactor translation of exception generating instructions

Create a new function which does the common sequence of gen_set_condexec,
gen_set_pc_im, gen_exception, set is_jmp to DISAS_JUMP.

Signed-off-by: Peter Maydell <>...

e12ce78d 01/14/2011 09:39 pm Peter Maydell

target-arm: Restore IT bits when resuming after an exception

We were not correctly restoring the IT bits when resuming execution
after taking an unexpected exception in the middle of an IT block.
Fix this by tracking them along with PC changes and restoring in...

39ea3d4e 01/14/2011 09:39 pm Peter Maydell

target-arm: Don't generate code specific to current CPU mode for SRS

When translating the SRS instruction, handle the "store registers
to stack of current mode" case in the helper function rather than
inline. This means the generated code does not make assumptions...

0322b26e 01/12/2011 01:06 am Peter Maydell

ARM: Fix decoding of VQSHL/VQSHLU immediate forms

Fix errors in the decoding of ARM VQSHL/VQSHLU immediate forms,
including using the new VQSHLU helper functions where appropriate.

Reviewed-by: Aurelien Jarno <>
Signed-off-by: Peter Maydell <>...

838fa72d 01/06/2011 11:16 pm Aurelien Jarno

target-arm: fix SMMLA/SMMLS instructions

SMMLA and SMMLS are broken on both in normal and thumb mode, that is
both (different) implementations are wrong. They try to avoid a 64-bit
add for the rounding, which is not trivial if you want to support both
SMMLA and SMMLS with the same code....

8aac08b1 12/31/2010 11:22 pm Aurelien Jarno

target-arm: fix UMAAL instruction

UMAAL should use unsigned multiply instead of signed.

This patch fixes this issue by handling UMAAL separately from
UMULL/UMLAL/SMULL/SMLAL as these instructions are different
enough. It also explicitly list instructions in case and catch...

def126ce 12/27/2010 10:06 pm Juha Riihimäki

target-arm: Fix arguments passed to VQSHL helpers

Correct the arguments passed when generating neon qshl_{u,s}64()
helpers so that we use the correct registers.

Signed-off-by: Juha Riihimäki <>
Reviewed-by: Peter Maydell <>...

1a855029 12/27/2010 08:56 pm Aurelien Jarno

target-arm: fix bug in translation of REVSH

The translation of REVSH shifted the low byte 8 steps left before performing
an 8-bit sign extend, causing this part of the expression to alwas be 0.

Reported-by: Johan Bengtsson <>
Signed-off-by: Aurelien Jarno <>

2c9adbda 12/07/2010 05:37 pm Peter Maydell

ARM: fix ldrexd/strexd

Correct ldrexd and strexd code to always read and write the
high word of the 64-bit value from addr+4.
Also make ldrexd and strexd agree that for a 64 bit value the
address in env->exclusive_addr is that of the low word.

This fixes the issues reported in...

04595bf6 12/07/2010 05:37 pm Peter Maydell

ARM: Fix decoding of VFP forms of VCVT between float and int/fixed

Correct the decoding of source and destination registers
for the VFP forms of the VCVT instructions which convert
between floating point and integer or fixed-point.

Signed-off-by: Peter Maydell <>...

f73534a5 12/07/2010 05:37 pm Peter Maydell

ARM: Fix decoding of Neon forms of VCVT between float and fixed point

Fix errors in the decoding of the Neon forms of fixed-point VCVT: * fixed-point VCVT is op 14 and 15, not 15 and 16 * the fbits immediate field was being misinterpreted * the sense of the to_fixed bit was inverted...

d3587ef8 12/07/2010 05:37 pm Peter Maydell

ARM: Fix sense of to_integer bit in Neon VCVT float/int conversion

Signed-off-by: Peter Maydell <>
Reviewed-by: Nathan Froyd <>

2af9ab77 12/07/2010 02:01 pm Johan Bengtsson

target-arm: Add support for PKHxx in thumb2

The PKHxx instructions were not recognized by the thumb2 decoder. The
solution provided in this changeset is identical to the arm-mode
implementation.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Peter Maydell <>...

4809c612 12/07/2010 02:01 pm Johan Bengtsson

target-arm: Fix mixup in decoding of saturating add and sub

The thumb2 decoder contained a mixup between the bit controlling
doubling and the bit controlling if the operation was an add or a sub.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Peter Maydell <>...

49e14940 12/07/2010 02:01 pm Adam Lackorzynski

target-arm: Handle 'smc' as an undefined instruction

Refine check on bkpt so that smc and undefined instruction encodings are
handled as an undefined instruction and trap.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Peter Maydell <>...

9a78eead 10/30/2010 11:01 am Stefan Weil

target-xxx: Use fprintf_function (format checking)

fprintf_function uses format checking with GCC_FMT_ATTR.

Format errors were fixed in
  • target-i386/helper.c
  • target-mips/translate.c
  • target-ppc/translate.c

Cc: Blue Swirl <>
Signed-off-by: Stefan Weil <>...

ed89a2f1 07/02/2010 12:45 am Chih-Min Chao

target-arm : fix thumb2 parallel add/sub opcode decoding

Signed-off-by: Chih-Min Chao <>
Signed-off-by: Aurelien Jarno <>

41ba8341 06/11/2010 10:37 pm Paul Brook

NEON vldN optimization

When combining multiple values as part of a NEON array load, do explcit
shift/or rather than using gen_bfi. This voids redundant mask
operations.

Signed-off-by: Paul Brook <>

22ed1d34 04/25/2010 10:31 pm Blue Swirl

arm: remove dead assignments, spotted by clang analyzer

Value stored is never read.

Signed-off-by: Blue Swirl <>

8e31209e 04/08/2010 10:12 pm Juha Riihimäki

target-arm: fix neon vmon/vmvn with modified immediate

Signed-Off-By: Riku Voipio <>
Signed-off-by: Juha Riihimäki <>
Signed-off-by: Aurelien Jarno <>

d9968827 04/08/2010 12:11 pm Lars Munch

target-arm: resource leak fixes for iwmmxt disassemble

This patch fixes few resource leaks in the iwmmxt disassemble.

Signed-off-by: Lars Munch <>
Signed-off-by: Aurelien Jarno <>

bedd2912 03/23/2010 11:10 pm Johan Bengtsson

target-arm: Fix handling of AL condition in IT instruction

Do not try to insert a conditional jump over next instruction when the
condition code is AL as this will trigger an internal error.

Signed-off-by: Johan Bengtsson <>
Signed-off-by: Aurelien Jarno <>

ea825eee 03/13/2010 01:01 pm Adam Lackorzynski

target-arm: make RFE usable with any register

The rfe instruction can be used with any register, not just sp. Adjust the
condition check accordingly.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>

a990f58f 03/07/2010 12:22 am Adam Lackorzynski

target-arm: Fix missing 'return' in SRS handling.

There's a return missing in the srs handling which leads to srs always being
treated an an invalid op.

Signed-off-by: Adam Lackorzynski <>
Signed-off-by: Aurelien Jarno <>

30d11a2a 02/28/2010 08:30 pm Juha Riihimäki

target-arm: neon vshll instruction fix

implementation only widened the 32bit source vector elements into a
64bit destination vector but forgot to perform the actual shifting
operation.

Signed-off-by: Juha Riihimäki <>
Signed-off-by: Riku Voipio <>...

79b0e534 02/28/2010 08:30 pm Riku Voipio

target-arm: neon - fix VRADDHN/VRSUBHN vs VADDHN/VSUBHN

The rounding/truncating options were inverted. truncating
was done when rounding was meant and vice verse.

Signed-off-by: Riku Voipio <>
Acked-by: Laurent Desnogues <>...

c5883be2 02/23/2010 04:45 pm Paul Brook

ARM CP15 tls fix

Fix temporary handling in cp15 tls register load/store.

Signed-off-by: Paul Brook <>

b8b45b68 02/19/2010 03:38 pm Rabin Vincent

target-arm: implement Thumb-2 exception return

Support the "subs pc, lr" Thumb-2 exception return instruction.

Signed-off-by: Rabin Vincent <>
Signed-off-by: Paul Brook <>

fa26df03 02/19/2010 03:38 pm Rabin Vincent

target-arm: fix thumb CPS

The Thumb CPS currently does not work correctly: CPSID touches more bits
than the instruction wants to, and CPSIE does nothing. Fix it by
passing the correct mask (the "affect" bits) and value.

Signed-off-by: Rabin Vincent <>

3f26c122 02/06/2010 06:19 pm Riku Voipio

target-arm: refactor cp15.c13 register access

Access the cp15.c13 TLS registers directly with TCG ops instead of with
a slow helper. If the the cp15 read/write was not TLS register access,
fall back to the cp15 helper.

This makes accessing __thread variables in linux-user when apps are compiled...

502e64fe 12/24/2009 01:18 am Aurelien Jarno

target-arm: fix strexd

Signed-off-by: Aurelien Jarno <>

426f5abc 11/22/2009 11:35 pm Paul Brook

ARM atomic ops rewrite

Implement ARMv6 atomic ops (ldrex/strex) using the same trick as PPC.

Signed-off-by: Paul Brook <>

60011498 11/19/2009 06:45 pm Paul Brook

ARM FP16 support

Implement the ARM VFP half precision floating point extensions.

Signed-off-by: Paul Brook <>

f669df27 10/27/2009 10:46 am Aurelien Jarno

target-arm: use native tcg-ops for ror/bic/vorn

Acked-by: Laurent Desnogues <>
Signed-off-by: Aurelien Jarno <>