Revision 36aa55dc target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 693 | 693 |
if (ctx->hflags & MIPS_HFLAG_F64) |
| 694 | 694 |
tcg_gen_mov_i64(t, fpu_fpr64[reg]); |
| 695 | 695 |
else {
|
| 696 |
TCGv r_tmp2 = tcg_temp_new(TCG_TYPE_I64); |
|
| 697 |
|
|
| 698 |
tcg_gen_extu_i32_i64(t, fpu_fpr32[reg | 1]); |
|
| 699 |
tcg_gen_shli_i64(t, t, 32); |
|
| 700 |
tcg_gen_extu_i32_i64(r_tmp2, fpu_fpr32[reg & ~1]); |
|
| 701 |
tcg_gen_or_i64(t, t, r_tmp2); |
|
| 702 |
tcg_temp_free(r_tmp2); |
|
| 696 |
tcg_gen_concat_i32_i64(t, fpu_fpr32[reg & ~1], fpu_fpr32[reg | 1]); |
|
| 703 | 697 |
} |
| 704 | 698 |
} |
| 705 | 699 |
|
| ... | ... | |
| 6546 | 6540 |
case FOP(38, 16): |
| 6547 | 6541 |
check_cp1_64bitmode(ctx); |
| 6548 | 6542 |
{
|
| 6549 |
TCGv fp64_0 = tcg_temp_new(TCG_TYPE_I64); |
|
| 6550 |
TCGv fp64_1 = tcg_temp_new(TCG_TYPE_I64); |
|
| 6543 |
TCGv fp64 = tcg_temp_new(TCG_TYPE_I64); |
|
| 6551 | 6544 |
TCGv fp32_0 = tcg_temp_new(TCG_TYPE_I32); |
| 6552 | 6545 |
TCGv fp32_1 = tcg_temp_new(TCG_TYPE_I32); |
| 6553 | 6546 |
|
| 6554 | 6547 |
gen_load_fpr32(fp32_0, fs); |
| 6555 | 6548 |
gen_load_fpr32(fp32_1, ft); |
| 6556 |
tcg_gen_extu_i32_i64(fp64_0, fp32_0); |
|
| 6557 |
tcg_gen_extu_i32_i64(fp64_1, fp32_1); |
|
| 6558 |
tcg_temp_free(fp32_0); |
|
| 6549 |
tcg_gen_concat_i32_i64(fp64, fp32_0, fp32_1); |
|
| 6559 | 6550 |
tcg_temp_free(fp32_1); |
| 6560 |
tcg_gen_shli_i64(fp64_1, fp64_1, 32); |
|
| 6561 |
tcg_gen_or_i64(fp64_0, fp64_0, fp64_1); |
|
| 6562 |
tcg_temp_free(fp64_1); |
|
| 6563 |
gen_store_fpr64(ctx, fp64_0, fd); |
|
| 6564 |
tcg_temp_free(fp64_0); |
|
| 6551 |
tcg_temp_free(fp32_0); |
|
| 6552 |
gen_store_fpr64(ctx, fp64, fd); |
|
| 6553 |
tcg_temp_free(fp64); |
|
| 6565 | 6554 |
} |
| 6566 | 6555 |
opn = "cvt.ps.s"; |
| 6567 | 6556 |
break; |
Also available in: Unified diff