root / hw / intel-hda.c @ 36ac4ad3
History | View | Annotate | Download (38.2 kB)
| 1 |
/*
|
|---|---|
| 2 |
* Copyright (C) 2010 Red Hat, Inc.
|
| 3 |
*
|
| 4 |
* written by Gerd Hoffmann <kraxel@redhat.com>
|
| 5 |
*
|
| 6 |
* This program is free software; you can redistribute it and/or
|
| 7 |
* modify it under the terms of the GNU General Public License as
|
| 8 |
* published by the Free Software Foundation; either version 2 or
|
| 9 |
* (at your option) version 3 of the License.
|
| 10 |
*
|
| 11 |
* This program is distributed in the hope that it will be useful,
|
| 12 |
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
| 13 |
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
| 14 |
* GNU General Public License for more details.
|
| 15 |
*
|
| 16 |
* You should have received a copy of the GNU General Public License
|
| 17 |
* along with this program; if not, see <http://www.gnu.org/licenses/>.
|
| 18 |
*/
|
| 19 |
|
| 20 |
#include "hw.h" |
| 21 |
#include "pci.h" |
| 22 |
#include "msi.h" |
| 23 |
#include "qemu-timer.h" |
| 24 |
#include "audiodev.h" |
| 25 |
#include "intel-hda.h" |
| 26 |
#include "intel-hda-defs.h" |
| 27 |
|
| 28 |
/* --------------------------------------------------------------------- */
|
| 29 |
/* hda bus */
|
| 30 |
|
| 31 |
static struct BusInfo hda_codec_bus_info = { |
| 32 |
.name = "HDA",
|
| 33 |
.size = sizeof(HDACodecBus),
|
| 34 |
.props = (Property[]) {
|
| 35 |
DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), |
| 36 |
DEFINE_PROP_END_OF_LIST() |
| 37 |
} |
| 38 |
}; |
| 39 |
|
| 40 |
void hda_codec_bus_init(DeviceState *dev, HDACodecBus *bus,
|
| 41 |
hda_codec_response_func response, |
| 42 |
hda_codec_xfer_func xfer) |
| 43 |
{
|
| 44 |
qbus_create_inplace(&bus->qbus, &hda_codec_bus_info, dev, NULL);
|
| 45 |
bus->response = response; |
| 46 |
bus->xfer = xfer; |
| 47 |
} |
| 48 |
|
| 49 |
static int hda_codec_dev_init(DeviceState *qdev, DeviceInfo *base) |
| 50 |
{
|
| 51 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, qdev->parent_bus); |
| 52 |
HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 53 |
HDACodecDeviceInfo *info = DO_UPCAST(HDACodecDeviceInfo, qdev, base); |
| 54 |
|
| 55 |
dev->info = info; |
| 56 |
if (dev->cad == -1) { |
| 57 |
dev->cad = bus->next_cad; |
| 58 |
} |
| 59 |
if (dev->cad >= 15) { |
| 60 |
return -1; |
| 61 |
} |
| 62 |
bus->next_cad = dev->cad + 1;
|
| 63 |
return info->init(dev);
|
| 64 |
} |
| 65 |
|
| 66 |
static int hda_codec_dev_exit(DeviceState *qdev) |
| 67 |
{
|
| 68 |
HDACodecDevice *dev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 69 |
|
| 70 |
if (dev->info->exit) {
|
| 71 |
dev->info->exit(dev); |
| 72 |
} |
| 73 |
return 0; |
| 74 |
} |
| 75 |
|
| 76 |
void hda_codec_register(HDACodecDeviceInfo *info)
|
| 77 |
{
|
| 78 |
info->qdev.init = hda_codec_dev_init; |
| 79 |
info->qdev.exit = hda_codec_dev_exit; |
| 80 |
info->qdev.bus_info = &hda_codec_bus_info; |
| 81 |
qdev_register(&info->qdev); |
| 82 |
} |
| 83 |
|
| 84 |
HDACodecDevice *hda_codec_find(HDACodecBus *bus, uint32_t cad) |
| 85 |
{
|
| 86 |
DeviceState *qdev; |
| 87 |
HDACodecDevice *cdev; |
| 88 |
|
| 89 |
QLIST_FOREACH(qdev, &bus->qbus.children, sibling) {
|
| 90 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 91 |
if (cdev->cad == cad) {
|
| 92 |
return cdev;
|
| 93 |
} |
| 94 |
} |
| 95 |
return NULL; |
| 96 |
} |
| 97 |
|
| 98 |
void hda_codec_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
| 99 |
{
|
| 100 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 101 |
bus->response(dev, solicited, response); |
| 102 |
} |
| 103 |
|
| 104 |
bool hda_codec_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
| 105 |
uint8_t *buf, uint32_t len) |
| 106 |
{
|
| 107 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 108 |
return bus->xfer(dev, stnr, output, buf, len);
|
| 109 |
} |
| 110 |
|
| 111 |
/* --------------------------------------------------------------------- */
|
| 112 |
/* intel hda emulation */
|
| 113 |
|
| 114 |
typedef struct IntelHDAStream IntelHDAStream; |
| 115 |
typedef struct IntelHDAState IntelHDAState; |
| 116 |
typedef struct IntelHDAReg IntelHDAReg; |
| 117 |
|
| 118 |
typedef struct bpl { |
| 119 |
uint64_t addr; |
| 120 |
uint32_t len; |
| 121 |
uint32_t flags; |
| 122 |
} bpl; |
| 123 |
|
| 124 |
struct IntelHDAStream {
|
| 125 |
/* registers */
|
| 126 |
uint32_t ctl; |
| 127 |
uint32_t lpib; |
| 128 |
uint32_t cbl; |
| 129 |
uint32_t lvi; |
| 130 |
uint32_t fmt; |
| 131 |
uint32_t bdlp_lbase; |
| 132 |
uint32_t bdlp_ubase; |
| 133 |
|
| 134 |
/* state */
|
| 135 |
bpl *bpl; |
| 136 |
uint32_t bentries; |
| 137 |
uint32_t bsize, be, bp; |
| 138 |
}; |
| 139 |
|
| 140 |
struct IntelHDAState {
|
| 141 |
PCIDevice pci; |
| 142 |
const char *name; |
| 143 |
HDACodecBus codecs; |
| 144 |
|
| 145 |
/* registers */
|
| 146 |
uint32_t g_ctl; |
| 147 |
uint32_t wake_en; |
| 148 |
uint32_t state_sts; |
| 149 |
uint32_t int_ctl; |
| 150 |
uint32_t int_sts; |
| 151 |
uint32_t wall_clk; |
| 152 |
|
| 153 |
uint32_t corb_lbase; |
| 154 |
uint32_t corb_ubase; |
| 155 |
uint32_t corb_rp; |
| 156 |
uint32_t corb_wp; |
| 157 |
uint32_t corb_ctl; |
| 158 |
uint32_t corb_sts; |
| 159 |
uint32_t corb_size; |
| 160 |
|
| 161 |
uint32_t rirb_lbase; |
| 162 |
uint32_t rirb_ubase; |
| 163 |
uint32_t rirb_wp; |
| 164 |
uint32_t rirb_cnt; |
| 165 |
uint32_t rirb_ctl; |
| 166 |
uint32_t rirb_sts; |
| 167 |
uint32_t rirb_size; |
| 168 |
|
| 169 |
uint32_t dp_lbase; |
| 170 |
uint32_t dp_ubase; |
| 171 |
|
| 172 |
uint32_t icw; |
| 173 |
uint32_t irr; |
| 174 |
uint32_t ics; |
| 175 |
|
| 176 |
/* streams */
|
| 177 |
IntelHDAStream st[8];
|
| 178 |
|
| 179 |
/* state */
|
| 180 |
MemoryRegion mmio; |
| 181 |
uint32_t rirb_count; |
| 182 |
int64_t wall_base_ns; |
| 183 |
|
| 184 |
/* debug logging */
|
| 185 |
const IntelHDAReg *last_reg;
|
| 186 |
uint32_t last_val; |
| 187 |
uint32_t last_write; |
| 188 |
uint32_t last_sec; |
| 189 |
uint32_t repeat_count; |
| 190 |
|
| 191 |
/* properties */
|
| 192 |
uint32_t debug; |
| 193 |
uint32_t msi; |
| 194 |
}; |
| 195 |
|
| 196 |
struct IntelHDAReg {
|
| 197 |
const char *name; /* register name */ |
| 198 |
uint32_t size; /* size in bytes */
|
| 199 |
uint32_t reset; /* reset value */
|
| 200 |
uint32_t wmask; /* write mask */
|
| 201 |
uint32_t wclear; /* write 1 to clear bits */
|
| 202 |
uint32_t offset; /* location in IntelHDAState */
|
| 203 |
uint32_t shift; /* byte access entries for dwords */
|
| 204 |
uint32_t stream; |
| 205 |
void (*whandler)(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old); |
| 206 |
void (*rhandler)(IntelHDAState *d, const IntelHDAReg *reg); |
| 207 |
}; |
| 208 |
|
| 209 |
static void intel_hda_reset(DeviceState *dev); |
| 210 |
|
| 211 |
/* --------------------------------------------------------------------- */
|
| 212 |
|
| 213 |
static target_phys_addr_t intel_hda_addr(uint32_t lbase, uint32_t ubase)
|
| 214 |
{
|
| 215 |
target_phys_addr_t addr; |
| 216 |
|
| 217 |
#if TARGET_PHYS_ADDR_BITS == 32 |
| 218 |
addr = lbase; |
| 219 |
#else
|
| 220 |
addr = ubase; |
| 221 |
addr <<= 32;
|
| 222 |
addr |= lbase; |
| 223 |
#endif
|
| 224 |
return addr;
|
| 225 |
} |
| 226 |
|
| 227 |
static void intel_hda_update_int_sts(IntelHDAState *d) |
| 228 |
{
|
| 229 |
uint32_t sts = 0;
|
| 230 |
uint32_t i; |
| 231 |
|
| 232 |
/* update controller status */
|
| 233 |
if (d->rirb_sts & ICH6_RBSTS_IRQ) {
|
| 234 |
sts |= (1 << 30); |
| 235 |
} |
| 236 |
if (d->rirb_sts & ICH6_RBSTS_OVERRUN) {
|
| 237 |
sts |= (1 << 30); |
| 238 |
} |
| 239 |
if (d->state_sts & d->wake_en) {
|
| 240 |
sts |= (1 << 30); |
| 241 |
} |
| 242 |
|
| 243 |
/* update stream status */
|
| 244 |
for (i = 0; i < 8; i++) { |
| 245 |
/* buffer completion interrupt */
|
| 246 |
if (d->st[i].ctl & (1 << 26)) { |
| 247 |
sts |= (1 << i);
|
| 248 |
} |
| 249 |
} |
| 250 |
|
| 251 |
/* update global status */
|
| 252 |
if (sts & d->int_ctl) {
|
| 253 |
sts |= (1 << 31); |
| 254 |
} |
| 255 |
|
| 256 |
d->int_sts = sts; |
| 257 |
} |
| 258 |
|
| 259 |
static void intel_hda_update_irq(IntelHDAState *d) |
| 260 |
{
|
| 261 |
int msi = d->msi && msi_enabled(&d->pci);
|
| 262 |
int level;
|
| 263 |
|
| 264 |
intel_hda_update_int_sts(d); |
| 265 |
if (d->int_sts & (1 << 31) && d->int_ctl & (1 << 31)) { |
| 266 |
level = 1;
|
| 267 |
} else {
|
| 268 |
level = 0;
|
| 269 |
} |
| 270 |
dprint(d, 2, "%s: level %d [%s]\n", __FUNCTION__, |
| 271 |
level, msi ? "msi" : "intx"); |
| 272 |
if (msi) {
|
| 273 |
if (level) {
|
| 274 |
msi_notify(&d->pci, 0);
|
| 275 |
} |
| 276 |
} else {
|
| 277 |
qemu_set_irq(d->pci.irq[0], level);
|
| 278 |
} |
| 279 |
} |
| 280 |
|
| 281 |
static int intel_hda_send_command(IntelHDAState *d, uint32_t verb) |
| 282 |
{
|
| 283 |
uint32_t cad, nid, data; |
| 284 |
HDACodecDevice *codec; |
| 285 |
|
| 286 |
cad = (verb >> 28) & 0x0f; |
| 287 |
if (verb & (1 << 27)) { |
| 288 |
/* indirect node addressing, not specified in HDA 1.0 */
|
| 289 |
dprint(d, 1, "%s: indirect node addressing (guest bug?)\n", __FUNCTION__); |
| 290 |
return -1; |
| 291 |
} |
| 292 |
nid = (verb >> 20) & 0x7f; |
| 293 |
data = verb & 0xfffff;
|
| 294 |
|
| 295 |
codec = hda_codec_find(&d->codecs, cad); |
| 296 |
if (codec == NULL) { |
| 297 |
dprint(d, 1, "%s: addressed non-existing codec\n", __FUNCTION__); |
| 298 |
return -1; |
| 299 |
} |
| 300 |
codec->info->command(codec, nid, data); |
| 301 |
return 0; |
| 302 |
} |
| 303 |
|
| 304 |
static void intel_hda_corb_run(IntelHDAState *d) |
| 305 |
{
|
| 306 |
target_phys_addr_t addr; |
| 307 |
uint32_t rp, verb; |
| 308 |
|
| 309 |
if (d->ics & ICH6_IRS_BUSY) {
|
| 310 |
dprint(d, 2, "%s: [icw] verb 0x%08x\n", __FUNCTION__, d->icw); |
| 311 |
intel_hda_send_command(d, d->icw); |
| 312 |
return;
|
| 313 |
} |
| 314 |
|
| 315 |
for (;;) {
|
| 316 |
if (!(d->corb_ctl & ICH6_CORBCTL_RUN)) {
|
| 317 |
dprint(d, 2, "%s: !run\n", __FUNCTION__); |
| 318 |
return;
|
| 319 |
} |
| 320 |
if ((d->corb_rp & 0xff) == d->corb_wp) { |
| 321 |
dprint(d, 2, "%s: corb ring empty\n", __FUNCTION__); |
| 322 |
return;
|
| 323 |
} |
| 324 |
if (d->rirb_count == d->rirb_cnt) {
|
| 325 |
dprint(d, 2, "%s: rirb count reached\n", __FUNCTION__); |
| 326 |
return;
|
| 327 |
} |
| 328 |
|
| 329 |
rp = (d->corb_rp + 1) & 0xff; |
| 330 |
addr = intel_hda_addr(d->corb_lbase, d->corb_ubase); |
| 331 |
verb = ldl_le_phys(addr + 4*rp);
|
| 332 |
d->corb_rp = rp; |
| 333 |
|
| 334 |
dprint(d, 2, "%s: [rp 0x%x] verb 0x%08x\n", __FUNCTION__, rp, verb); |
| 335 |
intel_hda_send_command(d, verb); |
| 336 |
} |
| 337 |
} |
| 338 |
|
| 339 |
static void intel_hda_response(HDACodecDevice *dev, bool solicited, uint32_t response) |
| 340 |
{
|
| 341 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 342 |
IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
| 343 |
target_phys_addr_t addr; |
| 344 |
uint32_t wp, ex; |
| 345 |
|
| 346 |
if (d->ics & ICH6_IRS_BUSY) {
|
| 347 |
dprint(d, 2, "%s: [irr] response 0x%x, cad 0x%x\n", |
| 348 |
__FUNCTION__, response, dev->cad); |
| 349 |
d->irr = response; |
| 350 |
d->ics &= ~(ICH6_IRS_BUSY | 0xf0);
|
| 351 |
d->ics |= (ICH6_IRS_VALID | (dev->cad << 4));
|
| 352 |
return;
|
| 353 |
} |
| 354 |
|
| 355 |
if (!(d->rirb_ctl & ICH6_RBCTL_DMA_EN)) {
|
| 356 |
dprint(d, 1, "%s: rirb dma disabled, drop codec response\n", __FUNCTION__); |
| 357 |
return;
|
| 358 |
} |
| 359 |
|
| 360 |
ex = (solicited ? 0 : (1 << 4)) | dev->cad; |
| 361 |
wp = (d->rirb_wp + 1) & 0xff; |
| 362 |
addr = intel_hda_addr(d->rirb_lbase, d->rirb_ubase); |
| 363 |
stl_le_phys(addr + 8*wp, response);
|
| 364 |
stl_le_phys(addr + 8*wp + 4, ex); |
| 365 |
d->rirb_wp = wp; |
| 366 |
|
| 367 |
dprint(d, 2, "%s: [wp 0x%x] response 0x%x, extra 0x%x\n", |
| 368 |
__FUNCTION__, wp, response, ex); |
| 369 |
|
| 370 |
d->rirb_count++; |
| 371 |
if (d->rirb_count == d->rirb_cnt) {
|
| 372 |
dprint(d, 2, "%s: rirb count reached (%d)\n", __FUNCTION__, d->rirb_count); |
| 373 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
| 374 |
d->rirb_sts |= ICH6_RBSTS_IRQ; |
| 375 |
intel_hda_update_irq(d); |
| 376 |
} |
| 377 |
} else if ((d->corb_rp & 0xff) == d->corb_wp) { |
| 378 |
dprint(d, 2, "%s: corb ring empty (%d/%d)\n", __FUNCTION__, |
| 379 |
d->rirb_count, d->rirb_cnt); |
| 380 |
if (d->rirb_ctl & ICH6_RBCTL_IRQ_EN) {
|
| 381 |
d->rirb_sts |= ICH6_RBSTS_IRQ; |
| 382 |
intel_hda_update_irq(d); |
| 383 |
} |
| 384 |
} |
| 385 |
} |
| 386 |
|
| 387 |
static bool intel_hda_xfer(HDACodecDevice *dev, uint32_t stnr, bool output, |
| 388 |
uint8_t *buf, uint32_t len) |
| 389 |
{
|
| 390 |
HDACodecBus *bus = DO_UPCAST(HDACodecBus, qbus, dev->qdev.parent_bus); |
| 391 |
IntelHDAState *d = container_of(bus, IntelHDAState, codecs); |
| 392 |
target_phys_addr_t addr; |
| 393 |
uint32_t s, copy, left; |
| 394 |
IntelHDAStream *st; |
| 395 |
bool irq = false; |
| 396 |
|
| 397 |
st = output ? d->st + 4 : d->st;
|
| 398 |
for (s = 0; s < 4; s++) { |
| 399 |
if (stnr == ((st[s].ctl >> 20) & 0x0f)) { |
| 400 |
st = st + s; |
| 401 |
break;
|
| 402 |
} |
| 403 |
} |
| 404 |
if (st == NULL) { |
| 405 |
return false; |
| 406 |
} |
| 407 |
if (st->bpl == NULL) { |
| 408 |
return false; |
| 409 |
} |
| 410 |
if (st->ctl & (1 << 26)) { |
| 411 |
/*
|
| 412 |
* Wait with the next DMA xfer until the guest
|
| 413 |
* has acked the buffer completion interrupt
|
| 414 |
*/
|
| 415 |
return false; |
| 416 |
} |
| 417 |
|
| 418 |
left = len; |
| 419 |
while (left > 0) { |
| 420 |
copy = left; |
| 421 |
if (copy > st->bsize - st->lpib)
|
| 422 |
copy = st->bsize - st->lpib; |
| 423 |
if (copy > st->bpl[st->be].len - st->bp)
|
| 424 |
copy = st->bpl[st->be].len - st->bp; |
| 425 |
|
| 426 |
dprint(d, 3, "dma: entry %d, pos %d/%d, copy %d\n", |
| 427 |
st->be, st->bp, st->bpl[st->be].len, copy); |
| 428 |
|
| 429 |
cpu_physical_memory_rw(st->bpl[st->be].addr + st->bp, |
| 430 |
buf, copy, !output); |
| 431 |
st->lpib += copy; |
| 432 |
st->bp += copy; |
| 433 |
buf += copy; |
| 434 |
left -= copy; |
| 435 |
|
| 436 |
if (st->bpl[st->be].len == st->bp) {
|
| 437 |
/* bpl entry filled */
|
| 438 |
if (st->bpl[st->be].flags & 0x01) { |
| 439 |
irq = true;
|
| 440 |
} |
| 441 |
st->bp = 0;
|
| 442 |
st->be++; |
| 443 |
if (st->be == st->bentries) {
|
| 444 |
/* bpl wrap around */
|
| 445 |
st->be = 0;
|
| 446 |
st->lpib = 0;
|
| 447 |
} |
| 448 |
} |
| 449 |
} |
| 450 |
if (d->dp_lbase & 0x01) { |
| 451 |
addr = intel_hda_addr(d->dp_lbase & ~0x01, d->dp_ubase);
|
| 452 |
stl_le_phys(addr + 8*s, st->lpib);
|
| 453 |
} |
| 454 |
dprint(d, 3, "dma: --\n"); |
| 455 |
|
| 456 |
if (irq) {
|
| 457 |
st->ctl |= (1 << 26); /* buffer completion interrupt */ |
| 458 |
intel_hda_update_irq(d); |
| 459 |
} |
| 460 |
return true; |
| 461 |
} |
| 462 |
|
| 463 |
static void intel_hda_parse_bdl(IntelHDAState *d, IntelHDAStream *st) |
| 464 |
{
|
| 465 |
target_phys_addr_t addr; |
| 466 |
uint8_t buf[16];
|
| 467 |
uint32_t i; |
| 468 |
|
| 469 |
addr = intel_hda_addr(st->bdlp_lbase, st->bdlp_ubase); |
| 470 |
st->bentries = st->lvi +1;
|
| 471 |
g_free(st->bpl); |
| 472 |
st->bpl = g_malloc(sizeof(bpl) * st->bentries);
|
| 473 |
for (i = 0; i < st->bentries; i++, addr += 16) { |
| 474 |
cpu_physical_memory_read(addr, buf, 16);
|
| 475 |
st->bpl[i].addr = le64_to_cpu(*(uint64_t *)buf); |
| 476 |
st->bpl[i].len = le32_to_cpu(*(uint32_t *)(buf + 8));
|
| 477 |
st->bpl[i].flags = le32_to_cpu(*(uint32_t *)(buf + 12));
|
| 478 |
dprint(d, 1, "bdl/%d: 0x%" PRIx64 " +0x%x, 0x%x\n", |
| 479 |
i, st->bpl[i].addr, st->bpl[i].len, st->bpl[i].flags); |
| 480 |
} |
| 481 |
|
| 482 |
st->bsize = st->cbl; |
| 483 |
st->lpib = 0;
|
| 484 |
st->be = 0;
|
| 485 |
st->bp = 0;
|
| 486 |
} |
| 487 |
|
| 488 |
static void intel_hda_notify_codecs(IntelHDAState *d, uint32_t stream, bool running) |
| 489 |
{
|
| 490 |
DeviceState *qdev; |
| 491 |
HDACodecDevice *cdev; |
| 492 |
|
| 493 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
|
| 494 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 495 |
if (cdev->info->stream) {
|
| 496 |
cdev->info->stream(cdev, stream, running); |
| 497 |
} |
| 498 |
} |
| 499 |
} |
| 500 |
|
| 501 |
/* --------------------------------------------------------------------- */
|
| 502 |
|
| 503 |
static void intel_hda_set_g_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 504 |
{
|
| 505 |
if ((d->g_ctl & ICH6_GCTL_RESET) == 0) { |
| 506 |
intel_hda_reset(&d->pci.qdev); |
| 507 |
} |
| 508 |
} |
| 509 |
|
| 510 |
static void intel_hda_set_wake_en(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 511 |
{
|
| 512 |
intel_hda_update_irq(d); |
| 513 |
} |
| 514 |
|
| 515 |
static void intel_hda_set_state_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 516 |
{
|
| 517 |
intel_hda_update_irq(d); |
| 518 |
} |
| 519 |
|
| 520 |
static void intel_hda_set_int_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 521 |
{
|
| 522 |
intel_hda_update_irq(d); |
| 523 |
} |
| 524 |
|
| 525 |
static void intel_hda_get_wall_clk(IntelHDAState *d, const IntelHDAReg *reg) |
| 526 |
{
|
| 527 |
int64_t ns; |
| 528 |
|
| 529 |
ns = qemu_get_clock_ns(vm_clock) - d->wall_base_ns; |
| 530 |
d->wall_clk = (uint32_t)(ns * 24 / 1000); /* 24 MHz */ |
| 531 |
} |
| 532 |
|
| 533 |
static void intel_hda_set_corb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 534 |
{
|
| 535 |
intel_hda_corb_run(d); |
| 536 |
} |
| 537 |
|
| 538 |
static void intel_hda_set_corb_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 539 |
{
|
| 540 |
intel_hda_corb_run(d); |
| 541 |
} |
| 542 |
|
| 543 |
static void intel_hda_set_rirb_wp(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 544 |
{
|
| 545 |
if (d->rirb_wp & ICH6_RIRBWP_RST) {
|
| 546 |
d->rirb_wp = 0;
|
| 547 |
} |
| 548 |
} |
| 549 |
|
| 550 |
static void intel_hda_set_rirb_sts(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 551 |
{
|
| 552 |
intel_hda_update_irq(d); |
| 553 |
|
| 554 |
if ((old & ICH6_RBSTS_IRQ) && !(d->rirb_sts & ICH6_RBSTS_IRQ)) {
|
| 555 |
/* cleared ICH6_RBSTS_IRQ */
|
| 556 |
d->rirb_count = 0;
|
| 557 |
intel_hda_corb_run(d); |
| 558 |
} |
| 559 |
} |
| 560 |
|
| 561 |
static void intel_hda_set_ics(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 562 |
{
|
| 563 |
if (d->ics & ICH6_IRS_BUSY) {
|
| 564 |
intel_hda_corb_run(d); |
| 565 |
} |
| 566 |
} |
| 567 |
|
| 568 |
static void intel_hda_set_st_ctl(IntelHDAState *d, const IntelHDAReg *reg, uint32_t old) |
| 569 |
{
|
| 570 |
IntelHDAStream *st = d->st + reg->stream; |
| 571 |
|
| 572 |
if (st->ctl & 0x01) { |
| 573 |
/* reset */
|
| 574 |
dprint(d, 1, "st #%d: reset\n", reg->stream); |
| 575 |
st->ctl = 0;
|
| 576 |
} |
| 577 |
if ((st->ctl & 0x02) != (old & 0x02)) { |
| 578 |
uint32_t stnr = (st->ctl >> 20) & 0x0f; |
| 579 |
/* run bit flipped */
|
| 580 |
if (st->ctl & 0x02) { |
| 581 |
/* start */
|
| 582 |
dprint(d, 1, "st #%d: start %d (ring buf %d bytes)\n", |
| 583 |
reg->stream, stnr, st->cbl); |
| 584 |
intel_hda_parse_bdl(d, st); |
| 585 |
intel_hda_notify_codecs(d, stnr, true);
|
| 586 |
} else {
|
| 587 |
/* stop */
|
| 588 |
dprint(d, 1, "st #%d: stop %d\n", reg->stream, stnr); |
| 589 |
intel_hda_notify_codecs(d, stnr, false);
|
| 590 |
} |
| 591 |
} |
| 592 |
intel_hda_update_irq(d); |
| 593 |
} |
| 594 |
|
| 595 |
/* --------------------------------------------------------------------- */
|
| 596 |
|
| 597 |
#define ST_REG(_n, _o) (0x80 + (_n) * 0x20 + (_o)) |
| 598 |
|
| 599 |
static const struct IntelHDAReg regtab[] = { |
| 600 |
/* global */
|
| 601 |
[ ICH6_REG_GCAP ] = {
|
| 602 |
.name = "GCAP",
|
| 603 |
.size = 2,
|
| 604 |
.reset = 0x4401,
|
| 605 |
}, |
| 606 |
[ ICH6_REG_VMIN ] = {
|
| 607 |
.name = "VMIN",
|
| 608 |
.size = 1,
|
| 609 |
}, |
| 610 |
[ ICH6_REG_VMAJ ] = {
|
| 611 |
.name = "VMAJ",
|
| 612 |
.size = 1,
|
| 613 |
.reset = 1,
|
| 614 |
}, |
| 615 |
[ ICH6_REG_OUTPAY ] = {
|
| 616 |
.name = "OUTPAY",
|
| 617 |
.size = 2,
|
| 618 |
.reset = 0x3c,
|
| 619 |
}, |
| 620 |
[ ICH6_REG_INPAY ] = {
|
| 621 |
.name = "INPAY",
|
| 622 |
.size = 2,
|
| 623 |
.reset = 0x1d,
|
| 624 |
}, |
| 625 |
[ ICH6_REG_GCTL ] = {
|
| 626 |
.name = "GCTL",
|
| 627 |
.size = 4,
|
| 628 |
.wmask = 0x0103,
|
| 629 |
.offset = offsetof(IntelHDAState, g_ctl), |
| 630 |
.whandler = intel_hda_set_g_ctl, |
| 631 |
}, |
| 632 |
[ ICH6_REG_WAKEEN ] = {
|
| 633 |
.name = "WAKEEN",
|
| 634 |
.size = 2,
|
| 635 |
.wmask = 0x7fff,
|
| 636 |
.offset = offsetof(IntelHDAState, wake_en), |
| 637 |
.whandler = intel_hda_set_wake_en, |
| 638 |
}, |
| 639 |
[ ICH6_REG_STATESTS ] = {
|
| 640 |
.name = "STATESTS",
|
| 641 |
.size = 2,
|
| 642 |
.wmask = 0x7fff,
|
| 643 |
.wclear = 0x7fff,
|
| 644 |
.offset = offsetof(IntelHDAState, state_sts), |
| 645 |
.whandler = intel_hda_set_state_sts, |
| 646 |
}, |
| 647 |
|
| 648 |
/* interrupts */
|
| 649 |
[ ICH6_REG_INTCTL ] = {
|
| 650 |
.name = "INTCTL",
|
| 651 |
.size = 4,
|
| 652 |
.wmask = 0xc00000ff,
|
| 653 |
.offset = offsetof(IntelHDAState, int_ctl), |
| 654 |
.whandler = intel_hda_set_int_ctl, |
| 655 |
}, |
| 656 |
[ ICH6_REG_INTSTS ] = {
|
| 657 |
.name = "INTSTS",
|
| 658 |
.size = 4,
|
| 659 |
.wmask = 0xc00000ff,
|
| 660 |
.wclear = 0xc00000ff,
|
| 661 |
.offset = offsetof(IntelHDAState, int_sts), |
| 662 |
}, |
| 663 |
|
| 664 |
/* misc */
|
| 665 |
[ ICH6_REG_WALLCLK ] = {
|
| 666 |
.name = "WALLCLK",
|
| 667 |
.size = 4,
|
| 668 |
.offset = offsetof(IntelHDAState, wall_clk), |
| 669 |
.rhandler = intel_hda_get_wall_clk, |
| 670 |
}, |
| 671 |
[ ICH6_REG_WALLCLK + 0x2000 ] = {
|
| 672 |
.name = "WALLCLK(alias)",
|
| 673 |
.size = 4,
|
| 674 |
.offset = offsetof(IntelHDAState, wall_clk), |
| 675 |
.rhandler = intel_hda_get_wall_clk, |
| 676 |
}, |
| 677 |
|
| 678 |
/* dma engine */
|
| 679 |
[ ICH6_REG_CORBLBASE ] = {
|
| 680 |
.name = "CORBLBASE",
|
| 681 |
.size = 4,
|
| 682 |
.wmask = 0xffffff80,
|
| 683 |
.offset = offsetof(IntelHDAState, corb_lbase), |
| 684 |
}, |
| 685 |
[ ICH6_REG_CORBUBASE ] = {
|
| 686 |
.name = "CORBUBASE",
|
| 687 |
.size = 4,
|
| 688 |
.wmask = 0xffffffff,
|
| 689 |
.offset = offsetof(IntelHDAState, corb_ubase), |
| 690 |
}, |
| 691 |
[ ICH6_REG_CORBWP ] = {
|
| 692 |
.name = "CORBWP",
|
| 693 |
.size = 2,
|
| 694 |
.wmask = 0xff,
|
| 695 |
.offset = offsetof(IntelHDAState, corb_wp), |
| 696 |
.whandler = intel_hda_set_corb_wp, |
| 697 |
}, |
| 698 |
[ ICH6_REG_CORBRP ] = {
|
| 699 |
.name = "CORBRP",
|
| 700 |
.size = 2,
|
| 701 |
.wmask = 0x80ff,
|
| 702 |
.offset = offsetof(IntelHDAState, corb_rp), |
| 703 |
}, |
| 704 |
[ ICH6_REG_CORBCTL ] = {
|
| 705 |
.name = "CORBCTL",
|
| 706 |
.size = 1,
|
| 707 |
.wmask = 0x03,
|
| 708 |
.offset = offsetof(IntelHDAState, corb_ctl), |
| 709 |
.whandler = intel_hda_set_corb_ctl, |
| 710 |
}, |
| 711 |
[ ICH6_REG_CORBSTS ] = {
|
| 712 |
.name = "CORBSTS",
|
| 713 |
.size = 1,
|
| 714 |
.wmask = 0x01,
|
| 715 |
.wclear = 0x01,
|
| 716 |
.offset = offsetof(IntelHDAState, corb_sts), |
| 717 |
}, |
| 718 |
[ ICH6_REG_CORBSIZE ] = {
|
| 719 |
.name = "CORBSIZE",
|
| 720 |
.size = 1,
|
| 721 |
.reset = 0x42,
|
| 722 |
.offset = offsetof(IntelHDAState, corb_size), |
| 723 |
}, |
| 724 |
[ ICH6_REG_RIRBLBASE ] = {
|
| 725 |
.name = "RIRBLBASE",
|
| 726 |
.size = 4,
|
| 727 |
.wmask = 0xffffff80,
|
| 728 |
.offset = offsetof(IntelHDAState, rirb_lbase), |
| 729 |
}, |
| 730 |
[ ICH6_REG_RIRBUBASE ] = {
|
| 731 |
.name = "RIRBUBASE",
|
| 732 |
.size = 4,
|
| 733 |
.wmask = 0xffffffff,
|
| 734 |
.offset = offsetof(IntelHDAState, rirb_ubase), |
| 735 |
}, |
| 736 |
[ ICH6_REG_RIRBWP ] = {
|
| 737 |
.name = "RIRBWP",
|
| 738 |
.size = 2,
|
| 739 |
.wmask = 0x8000,
|
| 740 |
.offset = offsetof(IntelHDAState, rirb_wp), |
| 741 |
.whandler = intel_hda_set_rirb_wp, |
| 742 |
}, |
| 743 |
[ ICH6_REG_RINTCNT ] = {
|
| 744 |
.name = "RINTCNT",
|
| 745 |
.size = 2,
|
| 746 |
.wmask = 0xff,
|
| 747 |
.offset = offsetof(IntelHDAState, rirb_cnt), |
| 748 |
}, |
| 749 |
[ ICH6_REG_RIRBCTL ] = {
|
| 750 |
.name = "RIRBCTL",
|
| 751 |
.size = 1,
|
| 752 |
.wmask = 0x07,
|
| 753 |
.offset = offsetof(IntelHDAState, rirb_ctl), |
| 754 |
}, |
| 755 |
[ ICH6_REG_RIRBSTS ] = {
|
| 756 |
.name = "RIRBSTS",
|
| 757 |
.size = 1,
|
| 758 |
.wmask = 0x05,
|
| 759 |
.wclear = 0x05,
|
| 760 |
.offset = offsetof(IntelHDAState, rirb_sts), |
| 761 |
.whandler = intel_hda_set_rirb_sts, |
| 762 |
}, |
| 763 |
[ ICH6_REG_RIRBSIZE ] = {
|
| 764 |
.name = "RIRBSIZE",
|
| 765 |
.size = 1,
|
| 766 |
.reset = 0x42,
|
| 767 |
.offset = offsetof(IntelHDAState, rirb_size), |
| 768 |
}, |
| 769 |
|
| 770 |
[ ICH6_REG_DPLBASE ] = {
|
| 771 |
.name = "DPLBASE",
|
| 772 |
.size = 4,
|
| 773 |
.wmask = 0xffffff81,
|
| 774 |
.offset = offsetof(IntelHDAState, dp_lbase), |
| 775 |
}, |
| 776 |
[ ICH6_REG_DPUBASE ] = {
|
| 777 |
.name = "DPUBASE",
|
| 778 |
.size = 4,
|
| 779 |
.wmask = 0xffffffff,
|
| 780 |
.offset = offsetof(IntelHDAState, dp_ubase), |
| 781 |
}, |
| 782 |
|
| 783 |
[ ICH6_REG_IC ] = {
|
| 784 |
.name = "ICW",
|
| 785 |
.size = 4,
|
| 786 |
.wmask = 0xffffffff,
|
| 787 |
.offset = offsetof(IntelHDAState, icw), |
| 788 |
}, |
| 789 |
[ ICH6_REG_IR ] = {
|
| 790 |
.name = "IRR",
|
| 791 |
.size = 4,
|
| 792 |
.offset = offsetof(IntelHDAState, irr), |
| 793 |
}, |
| 794 |
[ ICH6_REG_IRS ] = {
|
| 795 |
.name = "ICS",
|
| 796 |
.size = 2,
|
| 797 |
.wmask = 0x0003,
|
| 798 |
.wclear = 0x0002,
|
| 799 |
.offset = offsetof(IntelHDAState, ics), |
| 800 |
.whandler = intel_hda_set_ics, |
| 801 |
}, |
| 802 |
|
| 803 |
#define HDA_STREAM(_t, _i) \
|
| 804 |
[ ST_REG(_i, ICH6_REG_SD_CTL) ] = { \
|
| 805 |
.stream = _i, \ |
| 806 |
.name = _t stringify(_i) " CTL", \
|
| 807 |
.size = 4, \
|
| 808 |
.wmask = 0x1cff001f, \
|
| 809 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 810 |
.whandler = intel_hda_set_st_ctl, \ |
| 811 |
}, \ |
| 812 |
[ ST_REG(_i, ICH6_REG_SD_CTL) + 2] = { \
|
| 813 |
.stream = _i, \ |
| 814 |
.name = _t stringify(_i) " CTL(stnr)", \
|
| 815 |
.size = 1, \
|
| 816 |
.shift = 16, \
|
| 817 |
.wmask = 0x00ff0000, \
|
| 818 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 819 |
.whandler = intel_hda_set_st_ctl, \ |
| 820 |
}, \ |
| 821 |
[ ST_REG(_i, ICH6_REG_SD_STS)] = { \
|
| 822 |
.stream = _i, \ |
| 823 |
.name = _t stringify(_i) " CTL(sts)", \
|
| 824 |
.size = 1, \
|
| 825 |
.shift = 24, \
|
| 826 |
.wmask = 0x1c000000, \
|
| 827 |
.wclear = 0x1c000000, \
|
| 828 |
.offset = offsetof(IntelHDAState, st[_i].ctl), \ |
| 829 |
.whandler = intel_hda_set_st_ctl, \ |
| 830 |
}, \ |
| 831 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) ] = { \
|
| 832 |
.stream = _i, \ |
| 833 |
.name = _t stringify(_i) " LPIB", \
|
| 834 |
.size = 4, \
|
| 835 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
| 836 |
}, \ |
| 837 |
[ ST_REG(_i, ICH6_REG_SD_LPIB) + 0x2000 ] = { \
|
| 838 |
.stream = _i, \ |
| 839 |
.name = _t stringify(_i) " LPIB(alias)", \
|
| 840 |
.size = 4, \
|
| 841 |
.offset = offsetof(IntelHDAState, st[_i].lpib), \ |
| 842 |
}, \ |
| 843 |
[ ST_REG(_i, ICH6_REG_SD_CBL) ] = { \
|
| 844 |
.stream = _i, \ |
| 845 |
.name = _t stringify(_i) " CBL", \
|
| 846 |
.size = 4, \
|
| 847 |
.wmask = 0xffffffff, \
|
| 848 |
.offset = offsetof(IntelHDAState, st[_i].cbl), \ |
| 849 |
}, \ |
| 850 |
[ ST_REG(_i, ICH6_REG_SD_LVI) ] = { \
|
| 851 |
.stream = _i, \ |
| 852 |
.name = _t stringify(_i) " LVI", \
|
| 853 |
.size = 2, \
|
| 854 |
.wmask = 0x00ff, \
|
| 855 |
.offset = offsetof(IntelHDAState, st[_i].lvi), \ |
| 856 |
}, \ |
| 857 |
[ ST_REG(_i, ICH6_REG_SD_FIFOSIZE) ] = { \
|
| 858 |
.stream = _i, \ |
| 859 |
.name = _t stringify(_i) " FIFOS", \
|
| 860 |
.size = 2, \
|
| 861 |
.reset = HDA_BUFFER_SIZE, \ |
| 862 |
}, \ |
| 863 |
[ ST_REG(_i, ICH6_REG_SD_FORMAT) ] = { \
|
| 864 |
.stream = _i, \ |
| 865 |
.name = _t stringify(_i) " FMT", \
|
| 866 |
.size = 2, \
|
| 867 |
.wmask = 0x7f7f, \
|
| 868 |
.offset = offsetof(IntelHDAState, st[_i].fmt), \ |
| 869 |
}, \ |
| 870 |
[ ST_REG(_i, ICH6_REG_SD_BDLPL) ] = { \
|
| 871 |
.stream = _i, \ |
| 872 |
.name = _t stringify(_i) " BDLPL", \
|
| 873 |
.size = 4, \
|
| 874 |
.wmask = 0xffffff80, \
|
| 875 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_lbase), \ |
| 876 |
}, \ |
| 877 |
[ ST_REG(_i, ICH6_REG_SD_BDLPU) ] = { \
|
| 878 |
.stream = _i, \ |
| 879 |
.name = _t stringify(_i) " BDLPU", \
|
| 880 |
.size = 4, \
|
| 881 |
.wmask = 0xffffffff, \
|
| 882 |
.offset = offsetof(IntelHDAState, st[_i].bdlp_ubase), \ |
| 883 |
}, \ |
| 884 |
|
| 885 |
HDA_STREAM("IN", 0) |
| 886 |
HDA_STREAM("IN", 1) |
| 887 |
HDA_STREAM("IN", 2) |
| 888 |
HDA_STREAM("IN", 3) |
| 889 |
|
| 890 |
HDA_STREAM("OUT", 4) |
| 891 |
HDA_STREAM("OUT", 5) |
| 892 |
HDA_STREAM("OUT", 6) |
| 893 |
HDA_STREAM("OUT", 7) |
| 894 |
|
| 895 |
}; |
| 896 |
|
| 897 |
static const IntelHDAReg *intel_hda_reg_find(IntelHDAState *d, target_phys_addr_t addr) |
| 898 |
{
|
| 899 |
const IntelHDAReg *reg;
|
| 900 |
|
| 901 |
if (addr >= sizeof(regtab)/sizeof(regtab[0])) { |
| 902 |
goto noreg;
|
| 903 |
} |
| 904 |
reg = regtab+addr; |
| 905 |
if (reg->name == NULL) { |
| 906 |
goto noreg;
|
| 907 |
} |
| 908 |
return reg;
|
| 909 |
|
| 910 |
noreg:
|
| 911 |
dprint(d, 1, "unknown register, addr 0x%x\n", (int) addr); |
| 912 |
return NULL; |
| 913 |
} |
| 914 |
|
| 915 |
static uint32_t *intel_hda_reg_addr(IntelHDAState *d, const IntelHDAReg *reg) |
| 916 |
{
|
| 917 |
uint8_t *addr = (void*)d;
|
| 918 |
|
| 919 |
addr += reg->offset; |
| 920 |
return (uint32_t*)addr;
|
| 921 |
} |
| 922 |
|
| 923 |
static void intel_hda_reg_write(IntelHDAState *d, const IntelHDAReg *reg, uint32_t val, |
| 924 |
uint32_t wmask) |
| 925 |
{
|
| 926 |
uint32_t *addr; |
| 927 |
uint32_t old; |
| 928 |
|
| 929 |
if (!reg) {
|
| 930 |
return;
|
| 931 |
} |
| 932 |
|
| 933 |
if (d->debug) {
|
| 934 |
time_t now = time(NULL);
|
| 935 |
if (d->last_write && d->last_reg == reg && d->last_val == val) {
|
| 936 |
d->repeat_count++; |
| 937 |
if (d->last_sec != now) {
|
| 938 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 939 |
d->last_sec = now; |
| 940 |
d->repeat_count = 0;
|
| 941 |
} |
| 942 |
} else {
|
| 943 |
if (d->repeat_count) {
|
| 944 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 945 |
} |
| 946 |
dprint(d, 2, "write %-16s: 0x%x (%x)\n", reg->name, val, wmask); |
| 947 |
d->last_write = 1;
|
| 948 |
d->last_reg = reg; |
| 949 |
d->last_val = val; |
| 950 |
d->last_sec = now; |
| 951 |
d->repeat_count = 0;
|
| 952 |
} |
| 953 |
} |
| 954 |
assert(reg->offset != 0);
|
| 955 |
|
| 956 |
addr = intel_hda_reg_addr(d, reg); |
| 957 |
old = *addr; |
| 958 |
|
| 959 |
if (reg->shift) {
|
| 960 |
val <<= reg->shift; |
| 961 |
wmask <<= reg->shift; |
| 962 |
} |
| 963 |
wmask &= reg->wmask; |
| 964 |
*addr &= ~wmask; |
| 965 |
*addr |= wmask & val; |
| 966 |
*addr &= ~(val & reg->wclear); |
| 967 |
|
| 968 |
if (reg->whandler) {
|
| 969 |
reg->whandler(d, reg, old); |
| 970 |
} |
| 971 |
} |
| 972 |
|
| 973 |
static uint32_t intel_hda_reg_read(IntelHDAState *d, const IntelHDAReg *reg, |
| 974 |
uint32_t rmask) |
| 975 |
{
|
| 976 |
uint32_t *addr, ret; |
| 977 |
|
| 978 |
if (!reg) {
|
| 979 |
return 0; |
| 980 |
} |
| 981 |
|
| 982 |
if (reg->rhandler) {
|
| 983 |
reg->rhandler(d, reg); |
| 984 |
} |
| 985 |
|
| 986 |
if (reg->offset == 0) { |
| 987 |
/* constant read-only register */
|
| 988 |
ret = reg->reset; |
| 989 |
} else {
|
| 990 |
addr = intel_hda_reg_addr(d, reg); |
| 991 |
ret = *addr; |
| 992 |
if (reg->shift) {
|
| 993 |
ret >>= reg->shift; |
| 994 |
} |
| 995 |
ret &= rmask; |
| 996 |
} |
| 997 |
if (d->debug) {
|
| 998 |
time_t now = time(NULL);
|
| 999 |
if (!d->last_write && d->last_reg == reg && d->last_val == ret) {
|
| 1000 |
d->repeat_count++; |
| 1001 |
if (d->last_sec != now) {
|
| 1002 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 1003 |
d->last_sec = now; |
| 1004 |
d->repeat_count = 0;
|
| 1005 |
} |
| 1006 |
} else {
|
| 1007 |
if (d->repeat_count) {
|
| 1008 |
dprint(d, 2, "previous register op repeated %d times\n", d->repeat_count); |
| 1009 |
} |
| 1010 |
dprint(d, 2, "read %-16s: 0x%x (%x)\n", reg->name, ret, rmask); |
| 1011 |
d->last_write = 0;
|
| 1012 |
d->last_reg = reg; |
| 1013 |
d->last_val = ret; |
| 1014 |
d->last_sec = now; |
| 1015 |
d->repeat_count = 0;
|
| 1016 |
} |
| 1017 |
} |
| 1018 |
return ret;
|
| 1019 |
} |
| 1020 |
|
| 1021 |
static void intel_hda_regs_reset(IntelHDAState *d) |
| 1022 |
{
|
| 1023 |
uint32_t *addr; |
| 1024 |
int i;
|
| 1025 |
|
| 1026 |
for (i = 0; i < sizeof(regtab)/sizeof(regtab[0]); i++) { |
| 1027 |
if (regtab[i].name == NULL) { |
| 1028 |
continue;
|
| 1029 |
} |
| 1030 |
if (regtab[i].offset == 0) { |
| 1031 |
continue;
|
| 1032 |
} |
| 1033 |
addr = intel_hda_reg_addr(d, regtab + i); |
| 1034 |
*addr = regtab[i].reset; |
| 1035 |
} |
| 1036 |
} |
| 1037 |
|
| 1038 |
/* --------------------------------------------------------------------- */
|
| 1039 |
|
| 1040 |
static void intel_hda_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1041 |
{
|
| 1042 |
IntelHDAState *d = opaque; |
| 1043 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1044 |
|
| 1045 |
intel_hda_reg_write(d, reg, val, 0xff);
|
| 1046 |
} |
| 1047 |
|
| 1048 |
static void intel_hda_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1049 |
{
|
| 1050 |
IntelHDAState *d = opaque; |
| 1051 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1052 |
|
| 1053 |
intel_hda_reg_write(d, reg, val, 0xffff);
|
| 1054 |
} |
| 1055 |
|
| 1056 |
static void intel_hda_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val) |
| 1057 |
{
|
| 1058 |
IntelHDAState *d = opaque; |
| 1059 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1060 |
|
| 1061 |
intel_hda_reg_write(d, reg, val, 0xffffffff);
|
| 1062 |
} |
| 1063 |
|
| 1064 |
static uint32_t intel_hda_mmio_readb(void *opaque, target_phys_addr_t addr) |
| 1065 |
{
|
| 1066 |
IntelHDAState *d = opaque; |
| 1067 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1068 |
|
| 1069 |
return intel_hda_reg_read(d, reg, 0xff); |
| 1070 |
} |
| 1071 |
|
| 1072 |
static uint32_t intel_hda_mmio_readw(void *opaque, target_phys_addr_t addr) |
| 1073 |
{
|
| 1074 |
IntelHDAState *d = opaque; |
| 1075 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1076 |
|
| 1077 |
return intel_hda_reg_read(d, reg, 0xffff); |
| 1078 |
} |
| 1079 |
|
| 1080 |
static uint32_t intel_hda_mmio_readl(void *opaque, target_phys_addr_t addr) |
| 1081 |
{
|
| 1082 |
IntelHDAState *d = opaque; |
| 1083 |
const IntelHDAReg *reg = intel_hda_reg_find(d, addr);
|
| 1084 |
|
| 1085 |
return intel_hda_reg_read(d, reg, 0xffffffff); |
| 1086 |
} |
| 1087 |
|
| 1088 |
static const MemoryRegionOps intel_hda_mmio_ops = { |
| 1089 |
.old_mmio = {
|
| 1090 |
.read = {
|
| 1091 |
intel_hda_mmio_readb, |
| 1092 |
intel_hda_mmio_readw, |
| 1093 |
intel_hda_mmio_readl, |
| 1094 |
}, |
| 1095 |
.write = {
|
| 1096 |
intel_hda_mmio_writeb, |
| 1097 |
intel_hda_mmio_writew, |
| 1098 |
intel_hda_mmio_writel, |
| 1099 |
}, |
| 1100 |
}, |
| 1101 |
.endianness = DEVICE_NATIVE_ENDIAN, |
| 1102 |
}; |
| 1103 |
|
| 1104 |
/* --------------------------------------------------------------------- */
|
| 1105 |
|
| 1106 |
static void intel_hda_reset(DeviceState *dev) |
| 1107 |
{
|
| 1108 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci.qdev, dev); |
| 1109 |
DeviceState *qdev; |
| 1110 |
HDACodecDevice *cdev; |
| 1111 |
|
| 1112 |
intel_hda_regs_reset(d); |
| 1113 |
d->wall_base_ns = qemu_get_clock_ns(vm_clock); |
| 1114 |
|
| 1115 |
/* reset codecs */
|
| 1116 |
QLIST_FOREACH(qdev, &d->codecs.qbus.children, sibling) {
|
| 1117 |
cdev = DO_UPCAST(HDACodecDevice, qdev, qdev); |
| 1118 |
if (qdev->info->reset) {
|
| 1119 |
qdev->info->reset(qdev); |
| 1120 |
} |
| 1121 |
d->state_sts |= (1 << cdev->cad);
|
| 1122 |
} |
| 1123 |
intel_hda_update_irq(d); |
| 1124 |
} |
| 1125 |
|
| 1126 |
static int intel_hda_init(PCIDevice *pci) |
| 1127 |
{
|
| 1128 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1129 |
uint8_t *conf = d->pci.config; |
| 1130 |
|
| 1131 |
d->name = d->pci.qdev.info->name; |
| 1132 |
|
| 1133 |
pci_config_set_interrupt_pin(conf, 1);
|
| 1134 |
|
| 1135 |
/* HDCTL off 0x40 bit 0 selects signaling mode (1-HDA, 0 - Ac97) 18.1.19 */
|
| 1136 |
conf[0x40] = 0x01; |
| 1137 |
|
| 1138 |
memory_region_init_io(&d->mmio, &intel_hda_mmio_ops, d, |
| 1139 |
"intel-hda", 0x4000); |
| 1140 |
pci_register_bar(&d->pci, 0, 0, &d->mmio); |
| 1141 |
if (d->msi) {
|
| 1142 |
msi_init(&d->pci, 0x50, 1, true, false); |
| 1143 |
} |
| 1144 |
|
| 1145 |
hda_codec_bus_init(&d->pci.qdev, &d->codecs, |
| 1146 |
intel_hda_response, intel_hda_xfer); |
| 1147 |
|
| 1148 |
return 0; |
| 1149 |
} |
| 1150 |
|
| 1151 |
static int intel_hda_exit(PCIDevice *pci) |
| 1152 |
{
|
| 1153 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1154 |
|
| 1155 |
msi_uninit(&d->pci); |
| 1156 |
memory_region_destroy(&d->mmio); |
| 1157 |
return 0; |
| 1158 |
} |
| 1159 |
|
| 1160 |
static void intel_hda_write_config(PCIDevice *pci, uint32_t addr, |
| 1161 |
uint32_t val, int len)
|
| 1162 |
{
|
| 1163 |
IntelHDAState *d = DO_UPCAST(IntelHDAState, pci, pci); |
| 1164 |
|
| 1165 |
pci_default_write_config(pci, addr, val, len); |
| 1166 |
if (d->msi) {
|
| 1167 |
msi_write_config(pci, addr, val, len); |
| 1168 |
} |
| 1169 |
} |
| 1170 |
|
| 1171 |
static int intel_hda_post_load(void *opaque, int version) |
| 1172 |
{
|
| 1173 |
IntelHDAState* d = opaque; |
| 1174 |
int i;
|
| 1175 |
|
| 1176 |
dprint(d, 1, "%s\n", __FUNCTION__); |
| 1177 |
for (i = 0; i < ARRAY_SIZE(d->st); i++) { |
| 1178 |
if (d->st[i].ctl & 0x02) { |
| 1179 |
intel_hda_parse_bdl(d, &d->st[i]); |
| 1180 |
} |
| 1181 |
} |
| 1182 |
intel_hda_update_irq(d); |
| 1183 |
return 0; |
| 1184 |
} |
| 1185 |
|
| 1186 |
static const VMStateDescription vmstate_intel_hda_stream = { |
| 1187 |
.name = "intel-hda-stream",
|
| 1188 |
.version_id = 1,
|
| 1189 |
.fields = (VMStateField []) {
|
| 1190 |
VMSTATE_UINT32(ctl, IntelHDAStream), |
| 1191 |
VMSTATE_UINT32(lpib, IntelHDAStream), |
| 1192 |
VMSTATE_UINT32(cbl, IntelHDAStream), |
| 1193 |
VMSTATE_UINT32(lvi, IntelHDAStream), |
| 1194 |
VMSTATE_UINT32(fmt, IntelHDAStream), |
| 1195 |
VMSTATE_UINT32(bdlp_lbase, IntelHDAStream), |
| 1196 |
VMSTATE_UINT32(bdlp_ubase, IntelHDAStream), |
| 1197 |
VMSTATE_END_OF_LIST() |
| 1198 |
} |
| 1199 |
}; |
| 1200 |
|
| 1201 |
static const VMStateDescription vmstate_intel_hda = { |
| 1202 |
.name = "intel-hda",
|
| 1203 |
.version_id = 1,
|
| 1204 |
.post_load = intel_hda_post_load, |
| 1205 |
.fields = (VMStateField []) {
|
| 1206 |
VMSTATE_PCI_DEVICE(pci, IntelHDAState), |
| 1207 |
|
| 1208 |
/* registers */
|
| 1209 |
VMSTATE_UINT32(g_ctl, IntelHDAState), |
| 1210 |
VMSTATE_UINT32(wake_en, IntelHDAState), |
| 1211 |
VMSTATE_UINT32(state_sts, IntelHDAState), |
| 1212 |
VMSTATE_UINT32(int_ctl, IntelHDAState), |
| 1213 |
VMSTATE_UINT32(int_sts, IntelHDAState), |
| 1214 |
VMSTATE_UINT32(wall_clk, IntelHDAState), |
| 1215 |
VMSTATE_UINT32(corb_lbase, IntelHDAState), |
| 1216 |
VMSTATE_UINT32(corb_ubase, IntelHDAState), |
| 1217 |
VMSTATE_UINT32(corb_rp, IntelHDAState), |
| 1218 |
VMSTATE_UINT32(corb_wp, IntelHDAState), |
| 1219 |
VMSTATE_UINT32(corb_ctl, IntelHDAState), |
| 1220 |
VMSTATE_UINT32(corb_sts, IntelHDAState), |
| 1221 |
VMSTATE_UINT32(corb_size, IntelHDAState), |
| 1222 |
VMSTATE_UINT32(rirb_lbase, IntelHDAState), |
| 1223 |
VMSTATE_UINT32(rirb_ubase, IntelHDAState), |
| 1224 |
VMSTATE_UINT32(rirb_wp, IntelHDAState), |
| 1225 |
VMSTATE_UINT32(rirb_cnt, IntelHDAState), |
| 1226 |
VMSTATE_UINT32(rirb_ctl, IntelHDAState), |
| 1227 |
VMSTATE_UINT32(rirb_sts, IntelHDAState), |
| 1228 |
VMSTATE_UINT32(rirb_size, IntelHDAState), |
| 1229 |
VMSTATE_UINT32(dp_lbase, IntelHDAState), |
| 1230 |
VMSTATE_UINT32(dp_ubase, IntelHDAState), |
| 1231 |
VMSTATE_UINT32(icw, IntelHDAState), |
| 1232 |
VMSTATE_UINT32(irr, IntelHDAState), |
| 1233 |
VMSTATE_UINT32(ics, IntelHDAState), |
| 1234 |
VMSTATE_STRUCT_ARRAY(st, IntelHDAState, 8, 0, |
| 1235 |
vmstate_intel_hda_stream, |
| 1236 |
IntelHDAStream), |
| 1237 |
|
| 1238 |
/* additional state info */
|
| 1239 |
VMSTATE_UINT32(rirb_count, IntelHDAState), |
| 1240 |
VMSTATE_INT64(wall_base_ns, IntelHDAState), |
| 1241 |
|
| 1242 |
VMSTATE_END_OF_LIST() |
| 1243 |
} |
| 1244 |
}; |
| 1245 |
|
| 1246 |
static PCIDeviceInfo intel_hda_info = {
|
| 1247 |
.qdev.name = "intel-hda",
|
| 1248 |
.qdev.desc = "Intel HD Audio Controller",
|
| 1249 |
.qdev.size = sizeof(IntelHDAState),
|
| 1250 |
.qdev.vmsd = &vmstate_intel_hda, |
| 1251 |
.qdev.reset = intel_hda_reset, |
| 1252 |
.init = intel_hda_init, |
| 1253 |
.exit = intel_hda_exit, |
| 1254 |
.config_write = intel_hda_write_config, |
| 1255 |
.vendor_id = PCI_VENDOR_ID_INTEL, |
| 1256 |
.device_id = 0x2668,
|
| 1257 |
.revision = 1,
|
| 1258 |
.class_id = PCI_CLASS_MULTIMEDIA_HD_AUDIO, |
| 1259 |
.qdev.props = (Property[]) {
|
| 1260 |
DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), |
| 1261 |
DEFINE_PROP_UINT32("msi", IntelHDAState, msi, 1), |
| 1262 |
DEFINE_PROP_END_OF_LIST(), |
| 1263 |
} |
| 1264 |
}; |
| 1265 |
|
| 1266 |
static void intel_hda_register(void) |
| 1267 |
{
|
| 1268 |
pci_qdev_register(&intel_hda_info); |
| 1269 |
} |
| 1270 |
device_init(intel_hda_register); |
| 1271 |
|
| 1272 |
/*
|
| 1273 |
* create intel hda controller with codec attached to it,
|
| 1274 |
* so '-soundhw hda' works.
|
| 1275 |
*/
|
| 1276 |
int intel_hda_and_codec_init(PCIBus *bus)
|
| 1277 |
{
|
| 1278 |
PCIDevice *controller; |
| 1279 |
BusState *hdabus; |
| 1280 |
DeviceState *codec; |
| 1281 |
|
| 1282 |
controller = pci_create_simple(bus, -1, "intel-hda"); |
| 1283 |
hdabus = QLIST_FIRST(&controller->qdev.child_bus); |
| 1284 |
codec = qdev_create(hdabus, "hda-duplex");
|
| 1285 |
qdev_init_nofail(codec); |
| 1286 |
return 0; |
| 1287 |
} |
| 1288 |
|