Revision 36d23958 target-mips/mips-defs.h

b/target-mips/mips-defs.h
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   2-way Icache, 64 sets Dcache, 16 bytes Dcache line, 2-way Dcache,
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   no coprocessor2 attached, no MDMX support attached,
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   no performance counters, watch registers present,
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   no code compression, EJTAG present, FPU enable bit depending on
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   MIPS_USES_FPU */
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#define MIPS_CONFIG1_1                                            \
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   no code compression, EJTAG present, no FPU */
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#define MIPS_CONFIG1                                              \
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((1 << CP0C1_M) | ((MIPS_TLB_NB - 1) << CP0C1_MMU) |              \
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 (0x0 << CP0C1_IS) | (0x3 << CP0C1_IL) | (0x1 << CP0C1_IA) |      \
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 (0x0 << CP0C1_DS) | (0x3 << CP0C1_DL) | (0x1 << CP0C1_DA) |      \
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 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) |            \
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 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP))
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#ifdef MIPS_USES_FPU
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#define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (1 << CP0C1_FP))
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#else
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#define MIPS_CONFIG1  (MIPS_CONFIG1_1 | (0 << CP0C1_FP))
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#endif
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 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) |            \
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 (0 << CP0C1_FP))
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/* Have config3, no tertiary/secondary caches implemented */
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#define MIPS_CONFIG2                                              \
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((1 << CP0C2_M))

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