root / target-mips / op_mem.c @ 36d23958
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/*
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* MIPS emulation memory micro-operations for qemu.
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*
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* Copyright (c) 2004-2005 Jocelyn Mayer
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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/* Standard loads and stores */
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void glue(op_lb, MEMSUFFIX) (void) |
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{ |
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T0 = glue(ldsb, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_lbu, MEMSUFFIX) (void) |
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{ |
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T0 = glue(ldub, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_sb, MEMSUFFIX) (void) |
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{ |
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glue(stb, MEMSUFFIX)(T0, T1); |
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RETURN(); |
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} |
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void glue(op_lh, MEMSUFFIX) (void) |
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{ |
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T0 = glue(ldsw, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_lhu, MEMSUFFIX) (void) |
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{ |
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T0 = glue(lduw, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_sh, MEMSUFFIX) (void) |
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{ |
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glue(stw, MEMSUFFIX)(T0, T1); |
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RETURN(); |
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} |
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void glue(op_lw, MEMSUFFIX) (void) |
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{ |
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T0 = glue(ldl, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_lwu, MEMSUFFIX) (void) |
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{ |
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T0 = glue(ldl, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_sw, MEMSUFFIX) (void) |
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{ |
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glue(stl, MEMSUFFIX)(T0, T1); |
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RETURN(); |
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} |
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/* "half" load and stores. We must do the memory access inline,
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or fault handling won't work. */
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/* XXX: This is broken, CP0_BADVADDR has the wrong (aligned) value. */
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void glue(op_lwl, MEMSUFFIX) (void) |
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{ |
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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CALL_FROM_TB1(glue(do_lwl, MEMSUFFIX), tmp); |
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RETURN(); |
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} |
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void glue(op_lwr, MEMSUFFIX) (void) |
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{ |
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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CALL_FROM_TB1(glue(do_lwr, MEMSUFFIX), tmp); |
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RETURN(); |
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} |
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void glue(op_swl, MEMSUFFIX) (void) |
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{ |
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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tmp = CALL_FROM_TB1(glue(do_swl, MEMSUFFIX), tmp); |
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glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
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RETURN(); |
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} |
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void glue(op_swr, MEMSUFFIX) (void) |
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{ |
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uint32_t tmp = glue(ldl, MEMSUFFIX)(T0 & ~3);
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tmp = CALL_FROM_TB1(glue(do_swr, MEMSUFFIX), tmp); |
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glue(stl, MEMSUFFIX)(T0 & ~3, tmp);
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RETURN(); |
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} |
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void glue(op_ll, MEMSUFFIX) (void) |
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{ |
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T1 = T0; |
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T0 = glue(ldl, MEMSUFFIX)(T0); |
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env->CP0_LLAddr = T1; |
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RETURN(); |
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} |
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void glue(op_sc, MEMSUFFIX) (void) |
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{ |
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CALL_FROM_TB0(dump_sc); |
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if (T0 == env->CP0_LLAddr) {
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glue(stl, MEMSUFFIX)(T0, T1); |
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T0 = 1;
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} else {
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T0 = 0;
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} |
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RETURN(); |
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} |
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#ifdef MIPS_HAS_MIPS64
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void glue(op_ld, MEMSUFFIX) (void) |
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{ |
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T0 = glue(ldq, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_sd, MEMSUFFIX) (void) |
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{ |
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glue(stq, MEMSUFFIX)(T0, T1); |
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RETURN(); |
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} |
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/* "half" load and stores. We must do the memory access inline,
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or fault handling won't work. */
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void glue(op_ldl, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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CALL_FROM_TB1(glue(do_ldl, MEMSUFFIX), tmp); |
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RETURN(); |
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} |
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void glue(op_ldr, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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CALL_FROM_TB1(glue(do_ldr, MEMSUFFIX), tmp); |
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RETURN(); |
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} |
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void glue(op_sdl, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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tmp = CALL_FROM_TB1(glue(do_sdl, MEMSUFFIX), tmp); |
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glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
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RETURN(); |
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} |
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void glue(op_sdr, MEMSUFFIX) (void) |
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{ |
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target_long tmp = glue(ldq, MEMSUFFIX)(T0 & ~7);
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tmp = CALL_FROM_TB1(glue(do_sdr, MEMSUFFIX), tmp); |
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glue(stq, MEMSUFFIX)(T0 & ~7, tmp);
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RETURN(); |
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} |
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void glue(op_lld, MEMSUFFIX) (void) |
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{ |
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T1 = T0; |
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T0 = glue(ldq, MEMSUFFIX)(T0); |
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env->CP0_LLAddr = T1; |
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RETURN(); |
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} |
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void glue(op_scd, MEMSUFFIX) (void) |
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{ |
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CALL_FROM_TB0(dump_sc); |
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if (T0 == env->CP0_LLAddr) {
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glue(stq, MEMSUFFIX)(T0, T1); |
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T0 = 1;
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} else {
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T0 = 0;
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} |
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RETURN(); |
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} |
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#endif /* MIPS_HAS_MIPS64 */ |
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void glue(op_lwc1, MEMSUFFIX) (void) |
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{ |
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WT0 = glue(ldl, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_swc1, MEMSUFFIX) (void) |
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{ |
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glue(stl, MEMSUFFIX)(T0, WT0); |
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RETURN(); |
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} |
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void glue(op_ldc1, MEMSUFFIX) (void) |
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{ |
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DT0 = glue(ldq, MEMSUFFIX)(T0); |
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RETURN(); |
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} |
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void glue(op_sdc1, MEMSUFFIX) (void) |
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{ |
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glue(stq, MEMSUFFIX)(T0, DT0); |
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RETURN(); |
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} |