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/*
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* QEMU NE2000 emulation
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*
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* Copyright (c) 2003-2004 Fabrice Bellard
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw.h" |
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#include "pci.h" |
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#include "pc.h" |
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#include "net.h" |
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|
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/* debug NE2000 card */
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//#define DEBUG_NE2000
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#define MAX_ETH_FRAME_SIZE 1514 |
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#define E8390_CMD 0x00 /* The command register (for all pages) */ |
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/* Page 0 register offsets. */
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#define EN0_CLDALO 0x01 /* Low byte of current local dma addr RD */ |
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#define EN0_STARTPG 0x01 /* Starting page of ring bfr WR */ |
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#define EN0_CLDAHI 0x02 /* High byte of current local dma addr RD */ |
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#define EN0_STOPPG 0x02 /* Ending page +1 of ring bfr WR */ |
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#define EN0_BOUNDARY 0x03 /* Boundary page of ring bfr RD WR */ |
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#define EN0_TSR 0x04 /* Transmit status reg RD */ |
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#define EN0_TPSR 0x04 /* Transmit starting page WR */ |
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#define EN0_NCR 0x05 /* Number of collision reg RD */ |
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#define EN0_TCNTLO 0x05 /* Low byte of tx byte count WR */ |
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#define EN0_FIFO 0x06 /* FIFO RD */ |
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#define EN0_TCNTHI 0x06 /* High byte of tx byte count WR */ |
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#define EN0_ISR 0x07 /* Interrupt status reg RD WR */ |
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#define EN0_CRDALO 0x08 /* low byte of current remote dma address RD */ |
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#define EN0_RSARLO 0x08 /* Remote start address reg 0 */ |
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#define EN0_CRDAHI 0x09 /* high byte, current remote dma address RD */ |
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#define EN0_RSARHI 0x09 /* Remote start address reg 1 */ |
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#define EN0_RCNTLO 0x0a /* Remote byte count reg WR */ |
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#define EN0_RTL8029ID0 0x0a /* Realtek ID byte #1 RD */ |
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#define EN0_RCNTHI 0x0b /* Remote byte count reg WR */ |
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#define EN0_RTL8029ID1 0x0b /* Realtek ID byte #2 RD */ |
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#define EN0_RSR 0x0c /* rx status reg RD */ |
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#define EN0_RXCR 0x0c /* RX configuration reg WR */ |
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#define EN0_TXCR 0x0d /* TX configuration reg WR */ |
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#define EN0_COUNTER0 0x0d /* Rcv alignment error counter RD */ |
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#define EN0_DCFG 0x0e /* Data configuration reg WR */ |
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#define EN0_COUNTER1 0x0e /* Rcv CRC error counter RD */ |
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#define EN0_IMR 0x0f /* Interrupt mask reg WR */ |
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#define EN0_COUNTER2 0x0f /* Rcv missed frame error counter RD */ |
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|
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#define EN1_PHYS 0x11 |
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#define EN1_CURPAG 0x17 |
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#define EN1_MULT 0x18 |
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|
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#define EN2_STARTPG 0x21 /* Starting page of ring bfr RD */ |
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#define EN2_STOPPG 0x22 /* Ending page +1 of ring bfr RD */ |
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|
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#define EN3_CONFIG0 0x33 |
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#define EN3_CONFIG1 0x34 |
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#define EN3_CONFIG2 0x35 |
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#define EN3_CONFIG3 0x36 |
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/* Register accessed at EN_CMD, the 8390 base addr. */
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#define E8390_STOP 0x01 /* Stop and reset the chip */ |
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#define E8390_START 0x02 /* Start the chip, clear reset */ |
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#define E8390_TRANS 0x04 /* Transmit a frame */ |
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#define E8390_RREAD 0x08 /* Remote read */ |
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#define E8390_RWRITE 0x10 /* Remote write */ |
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#define E8390_NODMA 0x20 /* Remote DMA */ |
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#define E8390_PAGE0 0x00 /* Select page chip registers */ |
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#define E8390_PAGE1 0x40 /* using the two high-order bits */ |
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#define E8390_PAGE2 0x80 /* Page 3 is invalid. */ |
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|
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/* Bits in EN0_ISR - Interrupt status register */
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#define ENISR_RX 0x01 /* Receiver, no error */ |
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#define ENISR_TX 0x02 /* Transmitter, no error */ |
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#define ENISR_RX_ERR 0x04 /* Receiver, with error */ |
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#define ENISR_TX_ERR 0x08 /* Transmitter, with error */ |
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#define ENISR_OVER 0x10 /* Receiver overwrote the ring */ |
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#define ENISR_COUNTERS 0x20 /* Counters need emptying */ |
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#define ENISR_RDC 0x40 /* remote dma complete */ |
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#define ENISR_RESET 0x80 /* Reset completed */ |
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#define ENISR_ALL 0x3f /* Interrupts we will enable */ |
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/* Bits in received packet status byte and EN0_RSR*/
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#define ENRSR_RXOK 0x01 /* Received a good packet */ |
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#define ENRSR_CRC 0x02 /* CRC error */ |
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#define ENRSR_FAE 0x04 /* frame alignment error */ |
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#define ENRSR_FO 0x08 /* FIFO overrun */ |
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#define ENRSR_MPA 0x10 /* missed pkt */ |
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#define ENRSR_PHY 0x20 /* physical/multicast address */ |
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#define ENRSR_DIS 0x40 /* receiver disable. set in monitor mode */ |
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#define ENRSR_DEF 0x80 /* deferring */ |
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/* Transmitted packet status, EN0_TSR. */
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#define ENTSR_PTX 0x01 /* Packet transmitted without error */ |
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#define ENTSR_ND 0x02 /* The transmit wasn't deferred. */ |
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#define ENTSR_COL 0x04 /* The transmit collided at least once. */ |
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#define ENTSR_ABT 0x08 /* The transmit collided 16 times, and was deferred. */ |
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#define ENTSR_CRS 0x10 /* The carrier sense was lost. */ |
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#define ENTSR_FU 0x20 /* A "FIFO underrun" occurred during transmit. */ |
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#define ENTSR_CDH 0x40 /* The collision detect "heartbeat" signal was lost. */ |
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#define ENTSR_OWC 0x80 /* There was an out-of-window collision. */ |
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#define NE2000_PMEM_SIZE (32*1024) |
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#define NE2000_PMEM_START (16*1024) |
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#define NE2000_PMEM_END (NE2000_PMEM_SIZE+NE2000_PMEM_START)
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#define NE2000_MEM_SIZE NE2000_PMEM_END
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typedef struct NE2000State { |
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uint8_t cmd; |
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uint32_t start; |
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uint32_t stop; |
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uint8_t boundary; |
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uint8_t tsr; |
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uint8_t tpsr; |
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uint16_t tcnt; |
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uint16_t rcnt; |
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uint32_t rsar; |
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uint8_t rsr; |
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uint8_t rxcr; |
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uint8_t isr; |
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uint8_t dcfg; |
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uint8_t imr; |
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uint8_t phys[6]; /* mac address */ |
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uint8_t curpag; |
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uint8_t mult[8]; /* multicast mask array */ |
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qemu_irq irq; |
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int isa_io_base;
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PCIDevice *pci_dev; |
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VLANClientState *vc; |
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uint8_t macaddr[6];
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uint8_t mem[NE2000_MEM_SIZE]; |
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} NE2000State; |
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|
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static void ne2000_reset(NE2000State *s) |
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{
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int i;
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s->isr = ENISR_RESET; |
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memcpy(s->mem, s->macaddr, 6);
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s->mem[14] = 0x57; |
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s->mem[15] = 0x57; |
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/* duplicate prom data */
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for(i = 15;i >= 0; i--) { |
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s->mem[2 * i] = s->mem[i];
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s->mem[2 * i + 1] = s->mem[i]; |
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} |
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} |
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static void ne2000_update_irq(NE2000State *s) |
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{
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int isr;
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isr = (s->isr & s->imr) & 0x7f;
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#if defined(DEBUG_NE2000)
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printf("NE2000: Set IRQ to %d (%02x %02x)\n",
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isr ? 1 : 0, s->isr, s->imr); |
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#endif
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qemu_set_irq(s->irq, (isr != 0));
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} |
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#define POLYNOMIAL 0x04c11db6 |
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|
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/* From FreeBSD */
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/* XXX: optimize */
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static int compute_mcast_idx(const uint8_t *ep) |
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{
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uint32_t crc; |
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int carry, i, j;
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uint8_t b; |
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crc = 0xffffffff;
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for (i = 0; i < 6; i++) { |
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b = *ep++; |
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for (j = 0; j < 8; j++) { |
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carry = ((crc & 0x80000000L) ? 1 : 0) ^ (b & 0x01); |
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crc <<= 1;
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b >>= 1;
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if (carry)
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crc = ((crc ^ POLYNOMIAL) | carry); |
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} |
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} |
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return (crc >> 26); |
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} |
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|
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static int ne2000_buffer_full(NE2000State *s) |
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{
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int avail, index, boundary;
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index = s->curpag << 8;
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boundary = s->boundary << 8;
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if (index < boundary)
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avail = boundary - index; |
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else
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avail = (s->stop - s->start) - (index - boundary); |
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if (avail < (MAX_ETH_FRAME_SIZE + 4)) |
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return 1; |
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return 0; |
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} |
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|
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static int ne2000_can_receive(VLANClientState *vc) |
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{
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NE2000State *s = vc->opaque; |
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|
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if (s->cmd & E8390_STOP)
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return 1; |
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return !ne2000_buffer_full(s);
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} |
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|
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#define MIN_BUF_SIZE 60 |
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|
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static ssize_t ne2000_receive(VLANClientState *vc, const uint8_t *buf, size_t size_) |
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{
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NE2000State *s = vc->opaque; |
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int size = size_;
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uint8_t *p; |
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unsigned int total_len, next, avail, len, index, mcast_idx; |
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uint8_t buf1[60];
|
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static const uint8_t broadcast_macaddr[6] = |
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{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
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|
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#if defined(DEBUG_NE2000)
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printf("NE2000: received len=%d\n", size);
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#endif
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if (s->cmd & E8390_STOP || ne2000_buffer_full(s))
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return -1; |
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|
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/* XXX: check this */
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if (s->rxcr & 0x10) { |
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/* promiscuous: receive all */
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} else {
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if (!memcmp(buf, broadcast_macaddr, 6)) { |
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/* broadcast address */
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if (!(s->rxcr & 0x04)) |
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return size;
|
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} else if (buf[0] & 0x01) { |
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/* multicast */
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if (!(s->rxcr & 0x08)) |
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return size;
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mcast_idx = compute_mcast_idx(buf); |
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if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7)))) |
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return size;
|
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} else if (s->mem[0] == buf[0] && |
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s->mem[2] == buf[1] && |
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s->mem[4] == buf[2] && |
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s->mem[6] == buf[3] && |
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s->mem[8] == buf[4] && |
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s->mem[10] == buf[5]) { |
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/* match */
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} else {
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return size;
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} |
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} |
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|
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|
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/* if too small buffer, then expand it */
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if (size < MIN_BUF_SIZE) {
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memcpy(buf1, buf, size); |
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memset(buf1 + size, 0, MIN_BUF_SIZE - size);
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buf = buf1; |
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size = MIN_BUF_SIZE; |
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} |
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|
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index = s->curpag << 8;
|
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/* 4 bytes for header */
|
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total_len = size + 4;
|
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/* address for next packet (4 bytes for CRC) */
|
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next = index + ((total_len + 4 + 255) & ~0xff); |
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if (next >= s->stop)
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next -= (s->stop - s->start); |
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/* prepare packet header */
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p = s->mem + index; |
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s->rsr = ENRSR_RXOK; /* receive status */
|
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/* XXX: check this */
|
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if (buf[0] & 0x01) |
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s->rsr |= ENRSR_PHY; |
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p[0] = s->rsr;
|
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p[1] = next >> 8; |
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p[2] = total_len;
|
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p[3] = total_len >> 8; |
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index += 4;
|
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|
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/* write packet data */
|
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while (size > 0) { |
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if (index <= s->stop)
|
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avail = s->stop - index; |
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else
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avail = 0;
|
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len = size; |
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if (len > avail)
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len = avail; |
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memcpy(s->mem + index, buf, len); |
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buf += len; |
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index += len; |
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if (index == s->stop)
|
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index = s->start; |
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size -= len; |
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} |
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s->curpag = next >> 8;
|
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|
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/* now we can signal we have received something */
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s->isr |= ENISR_RX; |
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ne2000_update_irq(s); |
| 320 |
|
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return size_;
|
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} |
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|
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static void ne2000_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
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{
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NE2000State *s = opaque; |
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int offset, page, index;
|
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|
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addr &= 0xf;
|
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#ifdef DEBUG_NE2000
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printf("NE2000: write addr=0x%x val=0x%02x\n", addr, val);
|
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#endif
|
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if (addr == E8390_CMD) {
|
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/* control register */
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s->cmd = val; |
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if (!(val & E8390_STOP)) { /* START bit makes no sense on RTL8029... */ |
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s->isr &= ~ENISR_RESET; |
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/* test specific case: zero length transfer */
|
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if ((val & (E8390_RREAD | E8390_RWRITE)) &&
|
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s->rcnt == 0) {
|
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s->isr |= ENISR_RDC; |
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ne2000_update_irq(s); |
| 343 |
} |
| 344 |
if (val & E8390_TRANS) {
|
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index = (s->tpsr << 8);
|
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/* XXX: next 2 lines are a hack to make netware 3.11 work */
|
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if (index >= NE2000_PMEM_END)
|
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index -= NE2000_PMEM_SIZE; |
| 349 |
/* fail safe: check range on the transmitted length */
|
| 350 |
if (index + s->tcnt <= NE2000_PMEM_END) {
|
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qemu_send_packet(s->vc, s->mem + index, s->tcnt); |
| 352 |
} |
| 353 |
/* signal end of transfer */
|
| 354 |
s->tsr = ENTSR_PTX; |
| 355 |
s->isr |= ENISR_TX; |
| 356 |
s->cmd &= ~E8390_TRANS; |
| 357 |
ne2000_update_irq(s); |
| 358 |
} |
| 359 |
} |
| 360 |
} else {
|
| 361 |
page = s->cmd >> 6;
|
| 362 |
offset = addr | (page << 4);
|
| 363 |
switch(offset) {
|
| 364 |
case EN0_STARTPG:
|
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s->start = val << 8;
|
| 366 |
break;
|
| 367 |
case EN0_STOPPG:
|
| 368 |
s->stop = val << 8;
|
| 369 |
break;
|
| 370 |
case EN0_BOUNDARY:
|
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s->boundary = val; |
| 372 |
break;
|
| 373 |
case EN0_IMR:
|
| 374 |
s->imr = val; |
| 375 |
ne2000_update_irq(s); |
| 376 |
break;
|
| 377 |
case EN0_TPSR:
|
| 378 |
s->tpsr = val; |
| 379 |
break;
|
| 380 |
case EN0_TCNTLO:
|
| 381 |
s->tcnt = (s->tcnt & 0xff00) | val;
|
| 382 |
break;
|
| 383 |
case EN0_TCNTHI:
|
| 384 |
s->tcnt = (s->tcnt & 0x00ff) | (val << 8); |
| 385 |
break;
|
| 386 |
case EN0_RSARLO:
|
| 387 |
s->rsar = (s->rsar & 0xff00) | val;
|
| 388 |
break;
|
| 389 |
case EN0_RSARHI:
|
| 390 |
s->rsar = (s->rsar & 0x00ff) | (val << 8); |
| 391 |
break;
|
| 392 |
case EN0_RCNTLO:
|
| 393 |
s->rcnt = (s->rcnt & 0xff00) | val;
|
| 394 |
break;
|
| 395 |
case EN0_RCNTHI:
|
| 396 |
s->rcnt = (s->rcnt & 0x00ff) | (val << 8); |
| 397 |
break;
|
| 398 |
case EN0_RXCR:
|
| 399 |
s->rxcr = val; |
| 400 |
break;
|
| 401 |
case EN0_DCFG:
|
| 402 |
s->dcfg = val; |
| 403 |
break;
|
| 404 |
case EN0_ISR:
|
| 405 |
s->isr &= ~(val & 0x7f);
|
| 406 |
ne2000_update_irq(s); |
| 407 |
break;
|
| 408 |
case EN1_PHYS ... EN1_PHYS + 5: |
| 409 |
s->phys[offset - EN1_PHYS] = val; |
| 410 |
break;
|
| 411 |
case EN1_CURPAG:
|
| 412 |
s->curpag = val; |
| 413 |
break;
|
| 414 |
case EN1_MULT ... EN1_MULT + 7: |
| 415 |
s->mult[offset - EN1_MULT] = val; |
| 416 |
break;
|
| 417 |
} |
| 418 |
} |
| 419 |
} |
| 420 |
|
| 421 |
static uint32_t ne2000_ioport_read(void *opaque, uint32_t addr) |
| 422 |
{
|
| 423 |
NE2000State *s = opaque; |
| 424 |
int offset, page, ret;
|
| 425 |
|
| 426 |
addr &= 0xf;
|
| 427 |
if (addr == E8390_CMD) {
|
| 428 |
ret = s->cmd; |
| 429 |
} else {
|
| 430 |
page = s->cmd >> 6;
|
| 431 |
offset = addr | (page << 4);
|
| 432 |
switch(offset) {
|
| 433 |
case EN0_TSR:
|
| 434 |
ret = s->tsr; |
| 435 |
break;
|
| 436 |
case EN0_BOUNDARY:
|
| 437 |
ret = s->boundary; |
| 438 |
break;
|
| 439 |
case EN0_ISR:
|
| 440 |
ret = s->isr; |
| 441 |
break;
|
| 442 |
case EN0_RSARLO:
|
| 443 |
ret = s->rsar & 0x00ff;
|
| 444 |
break;
|
| 445 |
case EN0_RSARHI:
|
| 446 |
ret = s->rsar >> 8;
|
| 447 |
break;
|
| 448 |
case EN1_PHYS ... EN1_PHYS + 5: |
| 449 |
ret = s->phys[offset - EN1_PHYS]; |
| 450 |
break;
|
| 451 |
case EN1_CURPAG:
|
| 452 |
ret = s->curpag; |
| 453 |
break;
|
| 454 |
case EN1_MULT ... EN1_MULT + 7: |
| 455 |
ret = s->mult[offset - EN1_MULT]; |
| 456 |
break;
|
| 457 |
case EN0_RSR:
|
| 458 |
ret = s->rsr; |
| 459 |
break;
|
| 460 |
case EN2_STARTPG:
|
| 461 |
ret = s->start >> 8;
|
| 462 |
break;
|
| 463 |
case EN2_STOPPG:
|
| 464 |
ret = s->stop >> 8;
|
| 465 |
break;
|
| 466 |
case EN0_RTL8029ID0:
|
| 467 |
ret = 0x50;
|
| 468 |
break;
|
| 469 |
case EN0_RTL8029ID1:
|
| 470 |
ret = 0x43;
|
| 471 |
break;
|
| 472 |
case EN3_CONFIG0:
|
| 473 |
ret = 0; /* 10baseT media */ |
| 474 |
break;
|
| 475 |
case EN3_CONFIG2:
|
| 476 |
ret = 0x40; /* 10baseT active */ |
| 477 |
break;
|
| 478 |
case EN3_CONFIG3:
|
| 479 |
ret = 0x40; /* Full duplex */ |
| 480 |
break;
|
| 481 |
default:
|
| 482 |
ret = 0x00;
|
| 483 |
break;
|
| 484 |
} |
| 485 |
} |
| 486 |
#ifdef DEBUG_NE2000
|
| 487 |
printf("NE2000: read addr=0x%x val=%02x\n", addr, ret);
|
| 488 |
#endif
|
| 489 |
return ret;
|
| 490 |
} |
| 491 |
|
| 492 |
static inline void ne2000_mem_writeb(NE2000State *s, uint32_t addr, |
| 493 |
uint32_t val) |
| 494 |
{
|
| 495 |
if (addr < 32 || |
| 496 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 497 |
s->mem[addr] = val; |
| 498 |
} |
| 499 |
} |
| 500 |
|
| 501 |
static inline void ne2000_mem_writew(NE2000State *s, uint32_t addr, |
| 502 |
uint32_t val) |
| 503 |
{
|
| 504 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 505 |
if (addr < 32 || |
| 506 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 507 |
*(uint16_t *)(s->mem + addr) = cpu_to_le16(val); |
| 508 |
} |
| 509 |
} |
| 510 |
|
| 511 |
static inline void ne2000_mem_writel(NE2000State *s, uint32_t addr, |
| 512 |
uint32_t val) |
| 513 |
{
|
| 514 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 515 |
if (addr < 32 || |
| 516 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 517 |
cpu_to_le32wu((uint32_t *)(s->mem + addr), val); |
| 518 |
} |
| 519 |
} |
| 520 |
|
| 521 |
static inline uint32_t ne2000_mem_readb(NE2000State *s, uint32_t addr) |
| 522 |
{
|
| 523 |
if (addr < 32 || |
| 524 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 525 |
return s->mem[addr];
|
| 526 |
} else {
|
| 527 |
return 0xff; |
| 528 |
} |
| 529 |
} |
| 530 |
|
| 531 |
static inline uint32_t ne2000_mem_readw(NE2000State *s, uint32_t addr) |
| 532 |
{
|
| 533 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 534 |
if (addr < 32 || |
| 535 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 536 |
return le16_to_cpu(*(uint16_t *)(s->mem + addr));
|
| 537 |
} else {
|
| 538 |
return 0xffff; |
| 539 |
} |
| 540 |
} |
| 541 |
|
| 542 |
static inline uint32_t ne2000_mem_readl(NE2000State *s, uint32_t addr) |
| 543 |
{
|
| 544 |
addr &= ~1; /* XXX: check exact behaviour if not even */ |
| 545 |
if (addr < 32 || |
| 546 |
(addr >= NE2000_PMEM_START && addr < NE2000_MEM_SIZE)) {
|
| 547 |
return le32_to_cpupu((uint32_t *)(s->mem + addr));
|
| 548 |
} else {
|
| 549 |
return 0xffffffff; |
| 550 |
} |
| 551 |
} |
| 552 |
|
| 553 |
static inline void ne2000_dma_update(NE2000State *s, int len) |
| 554 |
{
|
| 555 |
s->rsar += len; |
| 556 |
/* wrap */
|
| 557 |
/* XXX: check what to do if rsar > stop */
|
| 558 |
if (s->rsar == s->stop)
|
| 559 |
s->rsar = s->start; |
| 560 |
|
| 561 |
if (s->rcnt <= len) {
|
| 562 |
s->rcnt = 0;
|
| 563 |
/* signal end of transfer */
|
| 564 |
s->isr |= ENISR_RDC; |
| 565 |
ne2000_update_irq(s); |
| 566 |
} else {
|
| 567 |
s->rcnt -= len; |
| 568 |
} |
| 569 |
} |
| 570 |
|
| 571 |
static void ne2000_asic_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 572 |
{
|
| 573 |
NE2000State *s = opaque; |
| 574 |
|
| 575 |
#ifdef DEBUG_NE2000
|
| 576 |
printf("NE2000: asic write val=0x%04x\n", val);
|
| 577 |
#endif
|
| 578 |
if (s->rcnt == 0) |
| 579 |
return;
|
| 580 |
if (s->dcfg & 0x01) { |
| 581 |
/* 16 bit access */
|
| 582 |
ne2000_mem_writew(s, s->rsar, val); |
| 583 |
ne2000_dma_update(s, 2);
|
| 584 |
} else {
|
| 585 |
/* 8 bit access */
|
| 586 |
ne2000_mem_writeb(s, s->rsar, val); |
| 587 |
ne2000_dma_update(s, 1);
|
| 588 |
} |
| 589 |
} |
| 590 |
|
| 591 |
static uint32_t ne2000_asic_ioport_read(void *opaque, uint32_t addr) |
| 592 |
{
|
| 593 |
NE2000State *s = opaque; |
| 594 |
int ret;
|
| 595 |
|
| 596 |
if (s->dcfg & 0x01) { |
| 597 |
/* 16 bit access */
|
| 598 |
ret = ne2000_mem_readw(s, s->rsar); |
| 599 |
ne2000_dma_update(s, 2);
|
| 600 |
} else {
|
| 601 |
/* 8 bit access */
|
| 602 |
ret = ne2000_mem_readb(s, s->rsar); |
| 603 |
ne2000_dma_update(s, 1);
|
| 604 |
} |
| 605 |
#ifdef DEBUG_NE2000
|
| 606 |
printf("NE2000: asic read val=0x%04x\n", ret);
|
| 607 |
#endif
|
| 608 |
return ret;
|
| 609 |
} |
| 610 |
|
| 611 |
static void ne2000_asic_ioport_writel(void *opaque, uint32_t addr, uint32_t val) |
| 612 |
{
|
| 613 |
NE2000State *s = opaque; |
| 614 |
|
| 615 |
#ifdef DEBUG_NE2000
|
| 616 |
printf("NE2000: asic writel val=0x%04x\n", val);
|
| 617 |
#endif
|
| 618 |
if (s->rcnt == 0) |
| 619 |
return;
|
| 620 |
/* 32 bit access */
|
| 621 |
ne2000_mem_writel(s, s->rsar, val); |
| 622 |
ne2000_dma_update(s, 4);
|
| 623 |
} |
| 624 |
|
| 625 |
static uint32_t ne2000_asic_ioport_readl(void *opaque, uint32_t addr) |
| 626 |
{
|
| 627 |
NE2000State *s = opaque; |
| 628 |
int ret;
|
| 629 |
|
| 630 |
/* 32 bit access */
|
| 631 |
ret = ne2000_mem_readl(s, s->rsar); |
| 632 |
ne2000_dma_update(s, 4);
|
| 633 |
#ifdef DEBUG_NE2000
|
| 634 |
printf("NE2000: asic readl val=0x%04x\n", ret);
|
| 635 |
#endif
|
| 636 |
return ret;
|
| 637 |
} |
| 638 |
|
| 639 |
static void ne2000_reset_ioport_write(void *opaque, uint32_t addr, uint32_t val) |
| 640 |
{
|
| 641 |
/* nothing to do (end of reset pulse) */
|
| 642 |
} |
| 643 |
|
| 644 |
static uint32_t ne2000_reset_ioport_read(void *opaque, uint32_t addr) |
| 645 |
{
|
| 646 |
NE2000State *s = opaque; |
| 647 |
ne2000_reset(s); |
| 648 |
return 0; |
| 649 |
} |
| 650 |
|
| 651 |
static void ne2000_save(QEMUFile* f,void* opaque) |
| 652 |
{
|
| 653 |
NE2000State* s = opaque; |
| 654 |
uint32_t tmp; |
| 655 |
|
| 656 |
if (s->pci_dev)
|
| 657 |
pci_device_save(s->pci_dev, f); |
| 658 |
|
| 659 |
qemu_put_8s(f, &s->rxcr); |
| 660 |
|
| 661 |
qemu_put_8s(f, &s->cmd); |
| 662 |
qemu_put_be32s(f, &s->start); |
| 663 |
qemu_put_be32s(f, &s->stop); |
| 664 |
qemu_put_8s(f, &s->boundary); |
| 665 |
qemu_put_8s(f, &s->tsr); |
| 666 |
qemu_put_8s(f, &s->tpsr); |
| 667 |
qemu_put_be16s(f, &s->tcnt); |
| 668 |
qemu_put_be16s(f, &s->rcnt); |
| 669 |
qemu_put_be32s(f, &s->rsar); |
| 670 |
qemu_put_8s(f, &s->rsr); |
| 671 |
qemu_put_8s(f, &s->isr); |
| 672 |
qemu_put_8s(f, &s->dcfg); |
| 673 |
qemu_put_8s(f, &s->imr); |
| 674 |
qemu_put_buffer(f, s->phys, 6);
|
| 675 |
qemu_put_8s(f, &s->curpag); |
| 676 |
qemu_put_buffer(f, s->mult, 8);
|
| 677 |
tmp = 0;
|
| 678 |
qemu_put_be32s(f, &tmp); /* ignored, was irq */
|
| 679 |
qemu_put_buffer(f, s->mem, NE2000_MEM_SIZE); |
| 680 |
} |
| 681 |
|
| 682 |
static int ne2000_load(QEMUFile* f,void* opaque,int version_id) |
| 683 |
{
|
| 684 |
NE2000State* s = opaque; |
| 685 |
int ret;
|
| 686 |
uint32_t tmp; |
| 687 |
|
| 688 |
if (version_id > 3) |
| 689 |
return -EINVAL;
|
| 690 |
|
| 691 |
if (s->pci_dev && version_id >= 3) { |
| 692 |
ret = pci_device_load(s->pci_dev, f); |
| 693 |
if (ret < 0) |
| 694 |
return ret;
|
| 695 |
} |
| 696 |
|
| 697 |
if (version_id >= 2) { |
| 698 |
qemu_get_8s(f, &s->rxcr); |
| 699 |
} else {
|
| 700 |
s->rxcr = 0x0c;
|
| 701 |
} |
| 702 |
|
| 703 |
qemu_get_8s(f, &s->cmd); |
| 704 |
qemu_get_be32s(f, &s->start); |
| 705 |
qemu_get_be32s(f, &s->stop); |
| 706 |
qemu_get_8s(f, &s->boundary); |
| 707 |
qemu_get_8s(f, &s->tsr); |
| 708 |
qemu_get_8s(f, &s->tpsr); |
| 709 |
qemu_get_be16s(f, &s->tcnt); |
| 710 |
qemu_get_be16s(f, &s->rcnt); |
| 711 |
qemu_get_be32s(f, &s->rsar); |
| 712 |
qemu_get_8s(f, &s->rsr); |
| 713 |
qemu_get_8s(f, &s->isr); |
| 714 |
qemu_get_8s(f, &s->dcfg); |
| 715 |
qemu_get_8s(f, &s->imr); |
| 716 |
qemu_get_buffer(f, s->phys, 6);
|
| 717 |
qemu_get_8s(f, &s->curpag); |
| 718 |
qemu_get_buffer(f, s->mult, 8);
|
| 719 |
qemu_get_be32s(f, &tmp); /* ignored */
|
| 720 |
qemu_get_buffer(f, s->mem, NE2000_MEM_SIZE); |
| 721 |
|
| 722 |
return 0; |
| 723 |
} |
| 724 |
|
| 725 |
static void isa_ne2000_cleanup(VLANClientState *vc) |
| 726 |
{
|
| 727 |
NE2000State *s = vc->opaque; |
| 728 |
|
| 729 |
unregister_savevm("ne2000", s);
|
| 730 |
|
| 731 |
isa_unassign_ioport(s->isa_io_base, 16);
|
| 732 |
isa_unassign_ioport(s->isa_io_base + 0x10, 2); |
| 733 |
isa_unassign_ioport(s->isa_io_base + 0x1f, 1); |
| 734 |
|
| 735 |
qemu_free(s); |
| 736 |
} |
| 737 |
|
| 738 |
void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd) |
| 739 |
{
|
| 740 |
NE2000State *s; |
| 741 |
|
| 742 |
qemu_check_nic_model(nd, "ne2k_isa");
|
| 743 |
|
| 744 |
s = qemu_mallocz(sizeof(NE2000State));
|
| 745 |
|
| 746 |
register_ioport_write(base, 16, 1, ne2000_ioport_write, s); |
| 747 |
register_ioport_read(base, 16, 1, ne2000_ioport_read, s); |
| 748 |
|
| 749 |
register_ioport_write(base + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
| 750 |
register_ioport_read(base + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
| 751 |
register_ioport_write(base + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
| 752 |
register_ioport_read(base + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
| 753 |
|
| 754 |
register_ioport_write(base + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
| 755 |
register_ioport_read(base + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
| 756 |
s->isa_io_base = base; |
| 757 |
s->irq = irq; |
| 758 |
memcpy(s->macaddr, nd->macaddr, 6);
|
| 759 |
|
| 760 |
ne2000_reset(s); |
| 761 |
|
| 762 |
s->vc = nd->vc = qemu_new_vlan_client(nd->vlan, nd->model, nd->name, |
| 763 |
ne2000_can_receive, ne2000_receive, |
| 764 |
NULL, isa_ne2000_cleanup, s);
|
| 765 |
|
| 766 |
qemu_format_nic_info_str(s->vc, s->macaddr); |
| 767 |
|
| 768 |
register_savevm("ne2000", -1, 2, ne2000_save, ne2000_load, s); |
| 769 |
} |
| 770 |
|
| 771 |
/***********************************************************/
|
| 772 |
/* PCI NE2000 definitions */
|
| 773 |
|
| 774 |
typedef struct PCINE2000State { |
| 775 |
PCIDevice dev; |
| 776 |
NE2000State ne2000; |
| 777 |
} PCINE2000State; |
| 778 |
|
| 779 |
static void ne2000_map(PCIDevice *pci_dev, int region_num, |
| 780 |
uint32_t addr, uint32_t size, int type)
|
| 781 |
{
|
| 782 |
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
| 783 |
NE2000State *s = &d->ne2000; |
| 784 |
|
| 785 |
register_ioport_write(addr, 16, 1, ne2000_ioport_write, s); |
| 786 |
register_ioport_read(addr, 16, 1, ne2000_ioport_read, s); |
| 787 |
|
| 788 |
register_ioport_write(addr + 0x10, 1, 1, ne2000_asic_ioport_write, s); |
| 789 |
register_ioport_read(addr + 0x10, 1, 1, ne2000_asic_ioport_read, s); |
| 790 |
register_ioport_write(addr + 0x10, 2, 2, ne2000_asic_ioport_write, s); |
| 791 |
register_ioport_read(addr + 0x10, 2, 2, ne2000_asic_ioport_read, s); |
| 792 |
register_ioport_write(addr + 0x10, 4, 4, ne2000_asic_ioport_writel, s); |
| 793 |
register_ioport_read(addr + 0x10, 4, 4, ne2000_asic_ioport_readl, s); |
| 794 |
|
| 795 |
register_ioport_write(addr + 0x1f, 1, 1, ne2000_reset_ioport_write, s); |
| 796 |
register_ioport_read(addr + 0x1f, 1, 1, ne2000_reset_ioport_read, s); |
| 797 |
} |
| 798 |
|
| 799 |
static void ne2000_cleanup(VLANClientState *vc) |
| 800 |
{
|
| 801 |
NE2000State *s = vc->opaque; |
| 802 |
|
| 803 |
unregister_savevm("ne2000", s);
|
| 804 |
} |
| 805 |
|
| 806 |
static int pci_ne2000_init(PCIDevice *pci_dev) |
| 807 |
{
|
| 808 |
PCINE2000State *d = DO_UPCAST(PCINE2000State, dev, pci_dev); |
| 809 |
NE2000State *s; |
| 810 |
uint8_t *pci_conf; |
| 811 |
|
| 812 |
pci_conf = d->dev.config; |
| 813 |
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK); |
| 814 |
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8029); |
| 815 |
pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET); |
| 816 |
pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
|
| 817 |
pci_conf[0x3d] = 1; // interrupt pin 0 |
| 818 |
|
| 819 |
pci_register_bar(&d->dev, 0, 0x100, |
| 820 |
PCI_ADDRESS_SPACE_IO, ne2000_map); |
| 821 |
s = &d->ne2000; |
| 822 |
s->irq = d->dev.irq[0];
|
| 823 |
s->pci_dev = pci_dev; |
| 824 |
qdev_get_macaddr(&d->dev.qdev, s->macaddr); |
| 825 |
ne2000_reset(s); |
| 826 |
s->vc = qdev_get_vlan_client(&d->dev.qdev, |
| 827 |
ne2000_can_receive, ne2000_receive, NULL,
|
| 828 |
ne2000_cleanup, s); |
| 829 |
|
| 830 |
qemu_format_nic_info_str(s->vc, s->macaddr); |
| 831 |
|
| 832 |
register_savevm("ne2000", -1, 3, ne2000_save, ne2000_load, s); |
| 833 |
return 0; |
| 834 |
} |
| 835 |
|
| 836 |
static PCIDeviceInfo ne2000_info = {
|
| 837 |
.qdev.name = "ne2k_pci",
|
| 838 |
.qdev.size = sizeof(PCINE2000State),
|
| 839 |
.init = pci_ne2000_init, |
| 840 |
}; |
| 841 |
|
| 842 |
static void ne2000_register_devices(void) |
| 843 |
{
|
| 844 |
pci_qdev_register(&ne2000_info); |
| 845 |
} |
| 846 |
|
| 847 |
device_init(ne2000_register_devices) |