Revision 3812ed0b
| b/hw/apb_pci.c | ||
|---|---|---|
| 31 | 31 |
#include "pci_host.h" |
| 32 | 32 |
#include "pci_bridge.h" |
| 33 | 33 |
#include "pci_internals.h" |
| 34 |
#include "rwhandler.h" |
|
| 35 | 34 |
#include "apb_pci.h" |
| 36 | 35 |
#include "sysemu.h" |
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#include "exec-memory.h" |
| ... | ... | |
| 70 | 69 |
typedef struct APBState {
|
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SysBusDevice busdev; |
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PCIBus *bus; |
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ReadWriteHandler pci_config_handler; |
|
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MemoryRegion apb_config; |
|
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MemoryRegion pci_config; |
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MemoryRegion pci_ioport; |
|
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uint32_t iommu[4]; |
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uint32_t pci_control[16]; |
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uint32_t pci_irq_map[8]; |
| ... | ... | |
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} APBState; |
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|
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static void apb_config_writel (void *opaque, target_phys_addr_t addr, |
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uint32_t val)
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uint64_t val, unsigned size)
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{
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APBState *s = opaque; |
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|
| ... | ... | |
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} |
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} |
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static uint32_t apb_config_readl (void *opaque,
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target_phys_addr_t addr) |
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static uint64_t apb_config_readl (void *opaque,
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target_phys_addr_t addr, unsigned size)
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{
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APBState *s = opaque; |
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uint32_t val; |
| ... | ... | |
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return val; |
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} |
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|
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static CPUWriteMemoryFunc * const apb_config_write[] = {
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&apb_config_writel,
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&apb_config_writel,
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&apb_config_writel,
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static const MemoryRegionOps apb_config_ops = {
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.read = apb_config_readl,
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.write = apb_config_writel,
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.endianness = DEVICE_NATIVE_ENDIAN,
|
|
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}; |
| 184 | 185 |
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static CPUReadMemoryFunc * const apb_config_read[] = {
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&apb_config_readl, |
|
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&apb_config_readl, |
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&apb_config_readl, |
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}; |
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|
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static void apb_pci_config_write(ReadWriteHandler *h, pcibus_t addr, |
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uint32_t val, int size) |
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static void apb_pci_config_write(void *opaque, target_phys_addr_t addr, |
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uint64_t val, unsigned size) |
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{
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APBState *s = container_of(h, APBState, pci_config_handler);
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APBState *s = opaque;
|
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val = qemu_bswap_len(val, size); |
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APB_DPRINTF("%s: addr " TARGET_FMT_lx " val %x\n", __func__, addr, val);
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pci_data_write(s->bus, addr, val, size); |
| 199 | 194 |
} |
| 200 | 195 |
|
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static uint32_t apb_pci_config_read(ReadWriteHandler *h, pcibus_t addr,
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int size)
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static uint64_t apb_pci_config_read(void *opaque, target_phys_addr_t addr,
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unsigned size)
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{
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uint32_t ret; |
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APBState *s = container_of(h, APBState, pci_config_handler);
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APBState *s = opaque;
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ret = pci_data_read(s->bus, addr, size); |
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ret = qemu_bswap_len(ret, size); |
| ... | ... | |
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return val; |
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} |
| 254 | 249 |
|
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static CPUWriteMemoryFunc * const pci_apb_iowrite[] = {
|
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&pci_apb_iowriteb, |
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&pci_apb_iowritew, |
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&pci_apb_iowritel, |
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}; |
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|
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static CPUReadMemoryFunc * const pci_apb_ioread[] = {
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&pci_apb_ioreadb, |
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&pci_apb_ioreadw, |
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&pci_apb_ioreadl, |
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static const MemoryRegionOps pci_ioport_ops = {
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.old_mmio = {
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.read = { pci_apb_ioreadb, pci_apb_ioreadw, pci_apb_ioreadl },
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.write = { pci_apb_iowriteb, pci_apb_iowritew, pci_apb_iowritel, },
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}, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
|
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}; |
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|
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/* The APB host has an IRQ line for each IRQ line of each slot. */ |
| ... | ... | |
| 393 | 384 |
} |
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} |
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static const MemoryRegionOps pci_config_ops = {
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.read = apb_pci_config_read, |
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.write = apb_pci_config_write, |
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.endianness = DEVICE_NATIVE_ENDIAN, |
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}; |
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|
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static int pci_pbm_init_device(SysBusDevice *dev) |
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{
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APBState *s; |
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int pci_config, apb_config, pci_ioport; |
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unsigned int i; |
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s = FROM_SYSBUS(APBState, dev); |
| ... | ... | |
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} |
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/* apb_config */ |
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apb_config = cpu_register_io_memory(apb_config_read, |
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apb_config_write, s, |
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DEVICE_NATIVE_ENDIAN); |
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memory_region_init_io(&s->apb_config, &apb_config_ops, s, "apb-config", |
|
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0x10000); |
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/* at region 0 */ |
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sysbus_init_mmio(dev, 0x10000ULL, apb_config);
|
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sysbus_init_mmio_region(dev, &s->apb_config);
|
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/* PCI configuration space */ |
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s->pci_config_handler.read = apb_pci_config_read; |
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s->pci_config_handler.write = apb_pci_config_write; |
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pci_config = cpu_register_io_memory_simple(&s->pci_config_handler, |
|
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DEVICE_NATIVE_ENDIAN); |
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assert(pci_config >= 0); |
|
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memory_region_init_io(&s->pci_config, &pci_config_ops, s, "apb-pci-config", |
|
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0x1000000); |
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/* at region 1 */ |
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sysbus_init_mmio(dev, 0x1000000ULL, pci_config);
|
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sysbus_init_mmio_region(dev, &s->pci_config);
|
|
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|
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/* pci_ioport */ |
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pci_ioport = cpu_register_io_memory(pci_apb_ioread, |
|
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pci_apb_iowrite, s, |
|
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DEVICE_NATIVE_ENDIAN); |
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memory_region_init_io(&s->pci_ioport, &pci_ioport_ops, s, |
|
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"apb-pci-ioport", 0x10000); |
|
| 430 | 420 |
/* at region 2 */ |
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sysbus_init_mmio(dev, 0x10000ULL, pci_ioport);
|
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sysbus_init_mmio_region(dev, &s->pci_ioport);
|
|
| 432 | 422 |
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return 0; |
| 434 | 424 |
} |
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