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1 | fc01f7e7 | bellard | /*
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2 | fc01f7e7 | bellard | * QEMU System Emulator header
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3 | 5fafdf24 | ths | *
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4 | fc01f7e7 | bellard | * Copyright (c) 2003 Fabrice Bellard
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5 | 5fafdf24 | ths | *
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6 | fc01f7e7 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | fc01f7e7 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | fc01f7e7 | bellard | * in the Software without restriction, including without limitation the rights
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9 | fc01f7e7 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | fc01f7e7 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | fc01f7e7 | bellard | * furnished to do so, subject to the following conditions:
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12 | fc01f7e7 | bellard | *
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13 | fc01f7e7 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | fc01f7e7 | bellard | * all copies or substantial portions of the Software.
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15 | fc01f7e7 | bellard | *
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16 | fc01f7e7 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | fc01f7e7 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | fc01f7e7 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | fc01f7e7 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | fc01f7e7 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | fc01f7e7 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | fc01f7e7 | bellard | * THE SOFTWARE.
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23 | fc01f7e7 | bellard | */
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24 | fc01f7e7 | bellard | #ifndef VL_H
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25 | fc01f7e7 | bellard | #define VL_H
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26 | fc01f7e7 | bellard | |
27 | faf07963 | pbrook | #include "qemu-common.h" |
28 | 16f62432 | bellard | |
29 | faf07963 | pbrook | /* FIXME: Remove this. */
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30 | faf07963 | pbrook | #include "block.h" |
31 | ea2384d3 | bellard | |
32 | 67b915a5 | bellard | #ifndef glue
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33 | 67b915a5 | bellard | #define xglue(x, y) x ## y |
34 | 67b915a5 | bellard | #define glue(x, y) xglue(x, y)
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35 | 67b915a5 | bellard | #define stringify(s) tostring(s)
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36 | 67b915a5 | bellard | #define tostring(s) #s |
37 | 67b915a5 | bellard | #endif
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38 | 67b915a5 | bellard | |
39 | 2e03286b | balrog | #ifndef likely
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40 | 2e03286b | balrog | #if __GNUC__ < 3 |
41 | 2e03286b | balrog | #define __builtin_expect(x, n) (x)
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42 | 2e03286b | balrog | #endif
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43 | 2e03286b | balrog | |
44 | 2e03286b | balrog | #define likely(x) __builtin_expect(!!(x), 1) |
45 | 2e03286b | balrog | #define unlikely(x) __builtin_expect(!!(x), 0) |
46 | 2e03286b | balrog | #endif
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47 | 2e03286b | balrog | |
48 | 24236869 | bellard | #ifndef MIN
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49 | 24236869 | bellard | #define MIN(a, b) (((a) < (b)) ? (a) : (b))
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50 | 24236869 | bellard | #endif
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51 | 24236869 | bellard | #ifndef MAX
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52 | 24236869 | bellard | #define MAX(a, b) (((a) > (b)) ? (a) : (b))
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53 | 24236869 | bellard | #endif
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54 | 24236869 | bellard | |
55 | 29f640e2 | j_mayer | #ifndef always_inline
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56 | 8a84de23 | j_mayer | #if (__GNUC__ < 3) || defined(__APPLE__) |
57 | 29f640e2 | j_mayer | #define always_inline inline |
58 | 29f640e2 | j_mayer | #else
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59 | 29f640e2 | j_mayer | #define always_inline __attribute__ (( always_inline )) inline |
60 | 29f640e2 | j_mayer | #endif
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61 | 29f640e2 | j_mayer | #endif
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62 | 29f640e2 | j_mayer | |
63 | 4728efa3 | bellard | #include "audio/audio.h" |
64 | 4728efa3 | bellard | |
65 | 33e3963e | bellard | /* vl.c */
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66 | 80cabfad | bellard | uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c); |
67 | 313aa567 | bellard | |
68 | 80cabfad | bellard | void hw_error(const char *fmt, ...); |
69 | 80cabfad | bellard | |
70 | 80cabfad | bellard | extern const char *bios_dir; |
71 | 1192dad8 | j_mayer | extern const char *bios_name; |
72 | 80cabfad | bellard | |
73 | 8a7ddc38 | bellard | extern int vm_running; |
74 | c35734b2 | ths | extern const char *qemu_name; |
75 | 8a7ddc38 | bellard | |
76 | 0bd48850 | bellard | typedef struct vm_change_state_entry VMChangeStateEntry; |
77 | 0bd48850 | bellard | typedef void VMChangeStateHandler(void *opaque, int running); |
78 | 8a7ddc38 | bellard | typedef void VMStopHandler(void *opaque, int reason); |
79 | 8a7ddc38 | bellard | |
80 | 0bd48850 | bellard | VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb, |
81 | 0bd48850 | bellard | void *opaque);
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82 | 0bd48850 | bellard | void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
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83 | 0bd48850 | bellard | |
84 | 8a7ddc38 | bellard | int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque); |
85 | 8a7ddc38 | bellard | void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque); |
86 | 8a7ddc38 | bellard | |
87 | 8a7ddc38 | bellard | void vm_start(void); |
88 | 8a7ddc38 | bellard | void vm_stop(int reason); |
89 | 8a7ddc38 | bellard | |
90 | bb0c6722 | bellard | typedef void QEMUResetHandler(void *opaque); |
91 | bb0c6722 | bellard | |
92 | bb0c6722 | bellard | void qemu_register_reset(QEMUResetHandler *func, void *opaque); |
93 | bb0c6722 | bellard | void qemu_system_reset_request(void); |
94 | bb0c6722 | bellard | void qemu_system_shutdown_request(void); |
95 | 3475187d | bellard | void qemu_system_powerdown_request(void); |
96 | 3475187d | bellard | #if !defined(TARGET_SPARC)
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97 | 3475187d | bellard | // Please implement a power failure function to signal the OS
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98 | 3475187d | bellard | #define qemu_system_powerdown() do{}while(0) |
99 | 3475187d | bellard | #else
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100 | 3475187d | bellard | void qemu_system_powerdown(void); |
101 | 3475187d | bellard | #endif
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102 | bb0c6722 | bellard | |
103 | ea2384d3 | bellard | void main_loop_wait(int timeout); |
104 | ea2384d3 | bellard | |
105 | 0ced6589 | bellard | extern int ram_size; |
106 | 0ced6589 | bellard | extern int bios_size; |
107 | ee22c2f7 | bellard | extern int rtc_utc; |
108 | 7e0af5d0 | bellard | extern int rtc_start_date; |
109 | 1f04275e | bellard | extern int cirrus_vga_enabled; |
110 | d34cab9f | ths | extern int vmsvga_enabled; |
111 | 28b9b5af | bellard | extern int graphic_width; |
112 | 28b9b5af | bellard | extern int graphic_height; |
113 | 28b9b5af | bellard | extern int graphic_depth; |
114 | 3d11d0eb | bellard | extern const char *keyboard_layout; |
115 | d993e026 | bellard | extern int kqemu_allowed; |
116 | a09db21f | bellard | extern int win2k_install_hack; |
117 | 3780e197 | ths | extern int alt_grab; |
118 | bb36d470 | bellard | extern int usb_enabled; |
119 | 6a00d601 | bellard | extern int smp_cpus; |
120 | 9467cd46 | balrog | extern int cursor_hide; |
121 | a171fe39 | balrog | extern int graphic_rotate; |
122 | 667accab | ths | extern int no_quit; |
123 | 8e71621f | pbrook | extern int semihosting_enabled; |
124 | 3c07f8e8 | pbrook | extern int autostart; |
125 | 2b8f2d41 | balrog | extern int old_param; |
126 | 47d5d01a | ths | extern const char *bootp_filename; |
127 | 0ced6589 | bellard | |
128 | 9ae02555 | ths | #define MAX_OPTION_ROMS 16 |
129 | 9ae02555 | ths | extern const char *option_rom[MAX_OPTION_ROMS]; |
130 | 9ae02555 | ths | extern int nb_option_roms; |
131 | 9ae02555 | ths | |
132 | 66508601 | blueswir1 | #ifdef TARGET_SPARC
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133 | 66508601 | blueswir1 | #define MAX_PROM_ENVS 128 |
134 | 66508601 | blueswir1 | extern const char *prom_envs[MAX_PROM_ENVS]; |
135 | 66508601 | blueswir1 | extern unsigned int nb_prom_envs; |
136 | 66508601 | blueswir1 | #endif
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137 | 66508601 | blueswir1 | |
138 | 0ced6589 | bellard | /* XXX: make it dynamic */
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139 | 970ac5a3 | bellard | #define MAX_BIOS_SIZE (4 * 1024 * 1024) |
140 | 4c823cff | j_mayer | #if defined (TARGET_PPC)
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141 | 4c823cff | j_mayer | #define BIOS_SIZE (1024 * 1024) |
142 | 4c823cff | j_mayer | #elif defined (TARGET_SPARC64)
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143 | d5295253 | bellard | #define BIOS_SIZE ((512 + 32) * 1024) |
144 | 6af0bf9c | bellard | #elif defined(TARGET_MIPS)
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145 | 567daa49 | ths | #define BIOS_SIZE (4 * 1024 * 1024) |
146 | 0ced6589 | bellard | #endif
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147 | aaaa7df6 | bellard | |
148 | 63066f4f | bellard | /* keyboard/mouse support */
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149 | 63066f4f | bellard | |
150 | 63066f4f | bellard | #define MOUSE_EVENT_LBUTTON 0x01 |
151 | 63066f4f | bellard | #define MOUSE_EVENT_RBUTTON 0x02 |
152 | 63066f4f | bellard | #define MOUSE_EVENT_MBUTTON 0x04 |
153 | 63066f4f | bellard | |
154 | 63066f4f | bellard | typedef void QEMUPutKBDEvent(void *opaque, int keycode); |
155 | 63066f4f | bellard | typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state); |
156 | 63066f4f | bellard | |
157 | 455204eb | ths | typedef struct QEMUPutMouseEntry { |
158 | 455204eb | ths | QEMUPutMouseEvent *qemu_put_mouse_event; |
159 | 455204eb | ths | void *qemu_put_mouse_event_opaque;
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160 | 455204eb | ths | int qemu_put_mouse_event_absolute;
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161 | 455204eb | ths | char *qemu_put_mouse_event_name;
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162 | 455204eb | ths | |
163 | 455204eb | ths | /* used internally by qemu for handling mice */
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164 | 455204eb | ths | struct QEMUPutMouseEntry *next;
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165 | 455204eb | ths | } QEMUPutMouseEntry; |
166 | 455204eb | ths | |
167 | 63066f4f | bellard | void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque); |
168 | 455204eb | ths | QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func, |
169 | 455204eb | ths | void *opaque, int absolute, |
170 | 455204eb | ths | const char *name); |
171 | 455204eb | ths | void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
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172 | 63066f4f | bellard | |
173 | 63066f4f | bellard | void kbd_put_keycode(int keycode); |
174 | 63066f4f | bellard | void kbd_mouse_event(int dx, int dy, int dz, int buttons_state); |
175 | 09b26c5e | bellard | int kbd_mouse_is_absolute(void); |
176 | 63066f4f | bellard | |
177 | 455204eb | ths | void do_info_mice(void); |
178 | 455204eb | ths | void do_mouse_set(int index); |
179 | 455204eb | ths | |
180 | 82c643ff | bellard | /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
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181 | 82c643ff | bellard | constants) */
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182 | 82c643ff | bellard | #define QEMU_KEY_ESC1(c) ((c) | 0xe100) |
183 | 82c643ff | bellard | #define QEMU_KEY_BACKSPACE 0x007f |
184 | 82c643ff | bellard | #define QEMU_KEY_UP QEMU_KEY_ESC1('A') |
185 | 82c643ff | bellard | #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B') |
186 | 82c643ff | bellard | #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C') |
187 | 82c643ff | bellard | #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D') |
188 | 82c643ff | bellard | #define QEMU_KEY_HOME QEMU_KEY_ESC1(1) |
189 | 82c643ff | bellard | #define QEMU_KEY_END QEMU_KEY_ESC1(4) |
190 | 82c643ff | bellard | #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5) |
191 | 82c643ff | bellard | #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6) |
192 | 82c643ff | bellard | #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3) |
193 | 82c643ff | bellard | |
194 | 82c643ff | bellard | #define QEMU_KEY_CTRL_UP 0xe400 |
195 | 82c643ff | bellard | #define QEMU_KEY_CTRL_DOWN 0xe401 |
196 | 82c643ff | bellard | #define QEMU_KEY_CTRL_LEFT 0xe402 |
197 | 82c643ff | bellard | #define QEMU_KEY_CTRL_RIGHT 0xe403 |
198 | 82c643ff | bellard | #define QEMU_KEY_CTRL_HOME 0xe404 |
199 | 82c643ff | bellard | #define QEMU_KEY_CTRL_END 0xe405 |
200 | 82c643ff | bellard | #define QEMU_KEY_CTRL_PAGEUP 0xe406 |
201 | 82c643ff | bellard | #define QEMU_KEY_CTRL_PAGEDOWN 0xe407 |
202 | 82c643ff | bellard | |
203 | 82c643ff | bellard | void kbd_put_keysym(int keysym); |
204 | 82c643ff | bellard | |
205 | c20709aa | bellard | /* async I/O support */
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206 | c20709aa | bellard | |
207 | c20709aa | bellard | typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size); |
208 | c20709aa | bellard | typedef int IOCanRWHandler(void *opaque); |
209 | 7c9d8e07 | bellard | typedef void IOHandler(void *opaque); |
210 | c20709aa | bellard | |
211 | 5fafdf24 | ths | int qemu_set_fd_handler2(int fd, |
212 | 5fafdf24 | ths | IOCanRWHandler *fd_read_poll, |
213 | 5fafdf24 | ths | IOHandler *fd_read, |
214 | 5fafdf24 | ths | IOHandler *fd_write, |
215 | 7c9d8e07 | bellard | void *opaque);
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216 | 7c9d8e07 | bellard | int qemu_set_fd_handler(int fd, |
217 | 5fafdf24 | ths | IOHandler *fd_read, |
218 | 7c9d8e07 | bellard | IOHandler *fd_write, |
219 | 7c9d8e07 | bellard | void *opaque);
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220 | c20709aa | bellard | |
221 | f331110f | bellard | /* Polling handling */
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222 | f331110f | bellard | |
223 | f331110f | bellard | /* return TRUE if no sleep should be done afterwards */
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224 | f331110f | bellard | typedef int PollingFunc(void *opaque); |
225 | f331110f | bellard | |
226 | f331110f | bellard | int qemu_add_polling_cb(PollingFunc *func, void *opaque); |
227 | f331110f | bellard | void qemu_del_polling_cb(PollingFunc *func, void *opaque); |
228 | f331110f | bellard | |
229 | a18e524a | bellard | #ifdef _WIN32
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230 | a18e524a | bellard | /* Wait objects handling */
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231 | a18e524a | bellard | typedef void WaitObjectFunc(void *opaque); |
232 | a18e524a | bellard | |
233 | a18e524a | bellard | int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
234 | a18e524a | bellard | void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque); |
235 | a18e524a | bellard | #endif
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236 | a18e524a | bellard | |
237 | 82c643ff | bellard | /* character device */
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238 | 82c643ff | bellard | |
239 | 82c643ff | bellard | #define CHR_EVENT_BREAK 0 /* serial break char */ |
240 | ea2384d3 | bellard | #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */ |
241 | 86e94dea | ths | #define CHR_EVENT_RESET 2 /* new connection established */ |
242 | 2122c51a | bellard | |
243 | 2122c51a | bellard | |
244 | 2122c51a | bellard | #define CHR_IOCTL_SERIAL_SET_PARAMS 1 |
245 | 2122c51a | bellard | typedef struct { |
246 | 2122c51a | bellard | int speed;
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247 | 2122c51a | bellard | int parity;
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248 | 2122c51a | bellard | int data_bits;
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249 | 2122c51a | bellard | int stop_bits;
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250 | 2122c51a | bellard | } QEMUSerialSetParams; |
251 | 2122c51a | bellard | |
252 | 2122c51a | bellard | #define CHR_IOCTL_SERIAL_SET_BREAK 2 |
253 | 2122c51a | bellard | |
254 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_DATA 3 |
255 | 2122c51a | bellard | #define CHR_IOCTL_PP_WRITE_DATA 4 |
256 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_CONTROL 5 |
257 | 2122c51a | bellard | #define CHR_IOCTL_PP_WRITE_CONTROL 6 |
258 | 2122c51a | bellard | #define CHR_IOCTL_PP_READ_STATUS 7 |
259 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_READ_ADDR 8 |
260 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_READ 9 |
261 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10 |
262 | 5867c88a | ths | #define CHR_IOCTL_PP_EPP_WRITE 11 |
263 | 2122c51a | bellard | |
264 | 82c643ff | bellard | typedef void IOEventHandler(void *opaque, int event); |
265 | 82c643ff | bellard | |
266 | 82c643ff | bellard | typedef struct CharDriverState { |
267 | 82c643ff | bellard | int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len); |
268 | e5b0bc44 | pbrook | void (*chr_update_read_handler)(struct CharDriverState *s); |
269 | 2122c51a | bellard | int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg); |
270 | 82c643ff | bellard | IOEventHandler *chr_event; |
271 | e5b0bc44 | pbrook | IOCanRWHandler *chr_can_read; |
272 | e5b0bc44 | pbrook | IOReadHandler *chr_read; |
273 | e5b0bc44 | pbrook | void *handler_opaque;
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274 | eb45f5fe | bellard | void (*chr_send_event)(struct CharDriverState *chr, int event); |
275 | f331110f | bellard | void (*chr_close)(struct CharDriverState *chr); |
276 | 82c643ff | bellard | void *opaque;
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277 | 20d8a3ed | ths | int focus;
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278 | 86e94dea | ths | QEMUBH *bh; |
279 | 82c643ff | bellard | } CharDriverState; |
280 | 82c643ff | bellard | |
281 | 5856de80 | ths | CharDriverState *qemu_chr_open(const char *filename); |
282 | 82c643ff | bellard | void qemu_chr_printf(CharDriverState *s, const char *fmt, ...); |
283 | 82c643ff | bellard | int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len); |
284 | ea2384d3 | bellard | void qemu_chr_send_event(CharDriverState *s, int event); |
285 | 5fafdf24 | ths | void qemu_chr_add_handlers(CharDriverState *s,
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286 | 5fafdf24 | ths | IOCanRWHandler *fd_can_read, |
287 | e5b0bc44 | pbrook | IOReadHandler *fd_read, |
288 | e5b0bc44 | pbrook | IOEventHandler *fd_event, |
289 | e5b0bc44 | pbrook | void *opaque);
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290 | 2122c51a | bellard | int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg); |
291 | 86e94dea | ths | void qemu_chr_reset(CharDriverState *s);
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292 | e5b0bc44 | pbrook | int qemu_chr_can_read(CharDriverState *s);
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293 | e5b0bc44 | pbrook | void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len); |
294 | f8d179e3 | bellard | |
295 | 82c643ff | bellard | /* consoles */
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296 | 82c643ff | bellard | |
297 | 82c643ff | bellard | typedef struct DisplayState DisplayState; |
298 | 82c643ff | bellard | typedef struct TextConsole TextConsole; |
299 | 82c643ff | bellard | |
300 | 4728efa3 | bellard | struct DisplayState {
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301 | 4728efa3 | bellard | uint8_t *data; |
302 | 4728efa3 | bellard | int linesize;
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303 | 4728efa3 | bellard | int depth;
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304 | 4728efa3 | bellard | int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */ |
305 | 4728efa3 | bellard | int width;
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306 | 4728efa3 | bellard | int height;
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307 | 4728efa3 | bellard | void *opaque;
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308 | 4728efa3 | bellard | struct QEMUTimer *gui_timer;
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309 | 4728efa3 | bellard | |
310 | 4728efa3 | bellard | void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h); |
311 | 4728efa3 | bellard | void (*dpy_resize)(struct DisplayState *s, int w, int h); |
312 | 4728efa3 | bellard | void (*dpy_refresh)(struct DisplayState *s); |
313 | 4728efa3 | bellard | void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y, |
314 | 4728efa3 | bellard | int dst_x, int dst_y, int w, int h); |
315 | 4728efa3 | bellard | void (*dpy_fill)(struct DisplayState *s, int x, int y, |
316 | 4728efa3 | bellard | int w, int h, uint32_t c); |
317 | 4728efa3 | bellard | void (*mouse_set)(int x, int y, int on); |
318 | 4728efa3 | bellard | void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y, |
319 | 4728efa3 | bellard | uint8_t *image, uint8_t *mask); |
320 | 4728efa3 | bellard | }; |
321 | 4728efa3 | bellard | |
322 | 4728efa3 | bellard | static inline void dpy_update(DisplayState *s, int x, int y, int w, int h) |
323 | 4728efa3 | bellard | { |
324 | 4728efa3 | bellard | s->dpy_update(s, x, y, w, h); |
325 | 4728efa3 | bellard | } |
326 | 4728efa3 | bellard | |
327 | 4728efa3 | bellard | static inline void dpy_resize(DisplayState *s, int w, int h) |
328 | 4728efa3 | bellard | { |
329 | 4728efa3 | bellard | s->dpy_resize(s, w, h); |
330 | 4728efa3 | bellard | } |
331 | 4728efa3 | bellard | |
332 | 95219897 | pbrook | typedef void (*vga_hw_update_ptr)(void *); |
333 | 95219897 | pbrook | typedef void (*vga_hw_invalidate_ptr)(void *); |
334 | 95219897 | pbrook | typedef void (*vga_hw_screen_dump_ptr)(void *, const char *); |
335 | 95219897 | pbrook | |
336 | 95219897 | pbrook | TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update, |
337 | 95219897 | pbrook | vga_hw_invalidate_ptr invalidate, |
338 | 95219897 | pbrook | vga_hw_screen_dump_ptr screen_dump, |
339 | 95219897 | pbrook | void *opaque);
|
340 | 95219897 | pbrook | void vga_hw_update(void); |
341 | 95219897 | pbrook | void vga_hw_invalidate(void); |
342 | 95219897 | pbrook | void vga_hw_screen_dump(const char *filename); |
343 | 95219897 | pbrook | |
344 | 95219897 | pbrook | int is_graphic_console(void); |
345 | af3a9031 | ths | CharDriverState *text_console_init(DisplayState *ds, const char *p); |
346 | 82c643ff | bellard | void console_select(unsigned int index); |
347 | a528b80c | balrog | void console_color_init(DisplayState *ds);
|
348 | 82c643ff | bellard | |
349 | 8d11df9e | bellard | /* serial ports */
|
350 | 8d11df9e | bellard | |
351 | 8d11df9e | bellard | #define MAX_SERIAL_PORTS 4 |
352 | 8d11df9e | bellard | |
353 | 8d11df9e | bellard | extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
|
354 | 8d11df9e | bellard | |
355 | 6508fe59 | bellard | /* parallel ports */
|
356 | 6508fe59 | bellard | |
357 | 6508fe59 | bellard | #define MAX_PARALLEL_PORTS 3 |
358 | 6508fe59 | bellard | |
359 | 6508fe59 | bellard | extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
|
360 | 6508fe59 | bellard | |
361 | 5867c88a | ths | struct ParallelIOArg {
|
362 | 5867c88a | ths | void *buffer;
|
363 | 5867c88a | ths | int count;
|
364 | 5867c88a | ths | }; |
365 | 5867c88a | ths | |
366 | 7c9d8e07 | bellard | /* VLANs support */
|
367 | 7c9d8e07 | bellard | |
368 | 7c9d8e07 | bellard | typedef struct VLANClientState VLANClientState; |
369 | 7c9d8e07 | bellard | |
370 | 7c9d8e07 | bellard | struct VLANClientState {
|
371 | 7c9d8e07 | bellard | IOReadHandler *fd_read; |
372 | d861b05e | pbrook | /* Packets may still be sent if this returns zero. It's used to
|
373 | d861b05e | pbrook | rate-limit the slirp code. */
|
374 | d861b05e | pbrook | IOCanRWHandler *fd_can_read; |
375 | 7c9d8e07 | bellard | void *opaque;
|
376 | 7c9d8e07 | bellard | struct VLANClientState *next;
|
377 | 7c9d8e07 | bellard | struct VLANState *vlan;
|
378 | 7c9d8e07 | bellard | char info_str[256]; |
379 | 7c9d8e07 | bellard | }; |
380 | 7c9d8e07 | bellard | |
381 | 7c9d8e07 | bellard | typedef struct VLANState { |
382 | 7c9d8e07 | bellard | int id;
|
383 | 7c9d8e07 | bellard | VLANClientState *first_client; |
384 | 7c9d8e07 | bellard | struct VLANState *next;
|
385 | 833c7174 | blueswir1 | unsigned int nb_guest_devs, nb_host_devs; |
386 | 7c9d8e07 | bellard | } VLANState; |
387 | 7c9d8e07 | bellard | |
388 | 7c9d8e07 | bellard | VLANState *qemu_find_vlan(int id);
|
389 | 7c9d8e07 | bellard | VLANClientState *qemu_new_vlan_client(VLANState *vlan, |
390 | d861b05e | pbrook | IOReadHandler *fd_read, |
391 | d861b05e | pbrook | IOCanRWHandler *fd_can_read, |
392 | d861b05e | pbrook | void *opaque);
|
393 | d861b05e | pbrook | int qemu_can_send_packet(VLANClientState *vc);
|
394 | 7c9d8e07 | bellard | void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size); |
395 | d861b05e | pbrook | void qemu_handler_true(void *opaque); |
396 | 7c9d8e07 | bellard | |
397 | 7c9d8e07 | bellard | void do_info_network(void); |
398 | 7c9d8e07 | bellard | |
399 | 7fb843f8 | bellard | /* TAP win32 */
|
400 | 7fb843f8 | bellard | int tap_win32_init(VLANState *vlan, const char *ifname); |
401 | 7fb843f8 | bellard | |
402 | 7c9d8e07 | bellard | /* NIC info */
|
403 | c4b1fcc0 | bellard | |
404 | c4b1fcc0 | bellard | #define MAX_NICS 8 |
405 | c4b1fcc0 | bellard | |
406 | 7c9d8e07 | bellard | typedef struct NICInfo { |
407 | c4b1fcc0 | bellard | uint8_t macaddr[6];
|
408 | a41b2ff2 | pbrook | const char *model; |
409 | 7c9d8e07 | bellard | VLANState *vlan; |
410 | 7c9d8e07 | bellard | } NICInfo; |
411 | c4b1fcc0 | bellard | |
412 | c4b1fcc0 | bellard | extern int nb_nics; |
413 | 7c9d8e07 | bellard | extern NICInfo nd_table[MAX_NICS];
|
414 | 8a7ddc38 | bellard | |
415 | 31a60e22 | blueswir1 | /* SLIRP */
|
416 | 31a60e22 | blueswir1 | void do_info_slirp(void); |
417 | 31a60e22 | blueswir1 | |
418 | 8a7ddc38 | bellard | /* timers */
|
419 | 8a7ddc38 | bellard | |
420 | 8a7ddc38 | bellard | typedef struct QEMUClock QEMUClock; |
421 | 8a7ddc38 | bellard | typedef struct QEMUTimer QEMUTimer; |
422 | 8a7ddc38 | bellard | typedef void QEMUTimerCB(void *opaque); |
423 | 8a7ddc38 | bellard | |
424 | 8a7ddc38 | bellard | /* The real time clock should be used only for stuff which does not
|
425 | 8a7ddc38 | bellard | change the virtual machine state, as it is run even if the virtual
|
426 | 69b91039 | bellard | machine is stopped. The real time clock has a frequency of 1000
|
427 | 8a7ddc38 | bellard | Hz. */
|
428 | 8a7ddc38 | bellard | extern QEMUClock *rt_clock;
|
429 | 8a7ddc38 | bellard | |
430 | e80cfcfc | bellard | /* The virtual clock is only run during the emulation. It is stopped
|
431 | 8a7ddc38 | bellard | when the virtual machine is stopped. Virtual timers use a high
|
432 | 8a7ddc38 | bellard | precision clock, usually cpu cycles (use ticks_per_sec). */
|
433 | 8a7ddc38 | bellard | extern QEMUClock *vm_clock;
|
434 | 8a7ddc38 | bellard | |
435 | 8a7ddc38 | bellard | int64_t qemu_get_clock(QEMUClock *clock); |
436 | 8a7ddc38 | bellard | |
437 | 8a7ddc38 | bellard | QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
|
438 | 8a7ddc38 | bellard | void qemu_free_timer(QEMUTimer *ts);
|
439 | 8a7ddc38 | bellard | void qemu_del_timer(QEMUTimer *ts);
|
440 | 8a7ddc38 | bellard | void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
|
441 | 8a7ddc38 | bellard | int qemu_timer_pending(QEMUTimer *ts);
|
442 | 8a7ddc38 | bellard | |
443 | 8a7ddc38 | bellard | extern int64_t ticks_per_sec;
|
444 | 8a7ddc38 | bellard | |
445 | 1dce7c3c | bellard | int64_t cpu_get_ticks(void);
|
446 | 8a7ddc38 | bellard | void cpu_enable_ticks(void); |
447 | 8a7ddc38 | bellard | void cpu_disable_ticks(void); |
448 | 8a7ddc38 | bellard | |
449 | 8a7ddc38 | bellard | /* VM Load/Save */
|
450 | 8a7ddc38 | bellard | |
451 | faea38e7 | bellard | typedef struct QEMUFile QEMUFile; |
452 | 8a7ddc38 | bellard | |
453 | faea38e7 | bellard | QEMUFile *qemu_fopen(const char *filename, const char *mode); |
454 | faea38e7 | bellard | void qemu_fflush(QEMUFile *f);
|
455 | faea38e7 | bellard | void qemu_fclose(QEMUFile *f);
|
456 | 8a7ddc38 | bellard | void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size); |
457 | 8a7ddc38 | bellard | void qemu_put_byte(QEMUFile *f, int v); |
458 | 8a7ddc38 | bellard | void qemu_put_be16(QEMUFile *f, unsigned int v); |
459 | 8a7ddc38 | bellard | void qemu_put_be32(QEMUFile *f, unsigned int v); |
460 | 8a7ddc38 | bellard | void qemu_put_be64(QEMUFile *f, uint64_t v);
|
461 | 8a7ddc38 | bellard | int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size); |
462 | 8a7ddc38 | bellard | int qemu_get_byte(QEMUFile *f);
|
463 | 8a7ddc38 | bellard | unsigned int qemu_get_be16(QEMUFile *f); |
464 | 8a7ddc38 | bellard | unsigned int qemu_get_be32(QEMUFile *f); |
465 | 8a7ddc38 | bellard | uint64_t qemu_get_be64(QEMUFile *f); |
466 | 8a7ddc38 | bellard | |
467 | 8a7ddc38 | bellard | static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv) |
468 | 8a7ddc38 | bellard | { |
469 | 8a7ddc38 | bellard | qemu_put_be64(f, *pv); |
470 | 8a7ddc38 | bellard | } |
471 | 8a7ddc38 | bellard | |
472 | 8a7ddc38 | bellard | static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv) |
473 | 8a7ddc38 | bellard | { |
474 | 8a7ddc38 | bellard | qemu_put_be32(f, *pv); |
475 | 8a7ddc38 | bellard | } |
476 | 8a7ddc38 | bellard | |
477 | 8a7ddc38 | bellard | static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv) |
478 | 8a7ddc38 | bellard | { |
479 | 8a7ddc38 | bellard | qemu_put_be16(f, *pv); |
480 | 8a7ddc38 | bellard | } |
481 | 8a7ddc38 | bellard | |
482 | 8a7ddc38 | bellard | static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv) |
483 | 8a7ddc38 | bellard | { |
484 | 8a7ddc38 | bellard | qemu_put_byte(f, *pv); |
485 | 8a7ddc38 | bellard | } |
486 | 8a7ddc38 | bellard | |
487 | 8a7ddc38 | bellard | static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv) |
488 | 8a7ddc38 | bellard | { |
489 | 8a7ddc38 | bellard | *pv = qemu_get_be64(f); |
490 | 8a7ddc38 | bellard | } |
491 | 8a7ddc38 | bellard | |
492 | 8a7ddc38 | bellard | static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv) |
493 | 8a7ddc38 | bellard | { |
494 | 8a7ddc38 | bellard | *pv = qemu_get_be32(f); |
495 | 8a7ddc38 | bellard | } |
496 | 8a7ddc38 | bellard | |
497 | 8a7ddc38 | bellard | static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv) |
498 | 8a7ddc38 | bellard | { |
499 | 8a7ddc38 | bellard | *pv = qemu_get_be16(f); |
500 | 8a7ddc38 | bellard | } |
501 | 8a7ddc38 | bellard | |
502 | 8a7ddc38 | bellard | static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv) |
503 | 8a7ddc38 | bellard | { |
504 | 8a7ddc38 | bellard | *pv = qemu_get_byte(f); |
505 | 8a7ddc38 | bellard | } |
506 | 8a7ddc38 | bellard | |
507 | c27004ec | bellard | #if TARGET_LONG_BITS == 64 |
508 | c27004ec | bellard | #define qemu_put_betl qemu_put_be64
|
509 | c27004ec | bellard | #define qemu_get_betl qemu_get_be64
|
510 | c27004ec | bellard | #define qemu_put_betls qemu_put_be64s
|
511 | c27004ec | bellard | #define qemu_get_betls qemu_get_be64s
|
512 | c27004ec | bellard | #else
|
513 | c27004ec | bellard | #define qemu_put_betl qemu_put_be32
|
514 | c27004ec | bellard | #define qemu_get_betl qemu_get_be32
|
515 | c27004ec | bellard | #define qemu_put_betls qemu_put_be32s
|
516 | c27004ec | bellard | #define qemu_get_betls qemu_get_be32s
|
517 | c27004ec | bellard | #endif
|
518 | c27004ec | bellard | |
519 | 8a7ddc38 | bellard | int64_t qemu_ftell(QEMUFile *f); |
520 | 8a7ddc38 | bellard | int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
|
521 | 8a7ddc38 | bellard | |
522 | 8a7ddc38 | bellard | typedef void SaveStateHandler(QEMUFile *f, void *opaque); |
523 | 8a7ddc38 | bellard | typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id); |
524 | 8a7ddc38 | bellard | |
525 | 5fafdf24 | ths | int register_savevm(const char *idstr, |
526 | 5fafdf24 | ths | int instance_id,
|
527 | 8a7ddc38 | bellard | int version_id,
|
528 | 8a7ddc38 | bellard | SaveStateHandler *save_state, |
529 | 8a7ddc38 | bellard | LoadStateHandler *load_state, |
530 | 8a7ddc38 | bellard | void *opaque);
|
531 | 8a7ddc38 | bellard | void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
|
532 | 8a7ddc38 | bellard | void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
|
533 | c4b1fcc0 | bellard | |
534 | 6a00d601 | bellard | void cpu_save(QEMUFile *f, void *opaque); |
535 | 6a00d601 | bellard | int cpu_load(QEMUFile *f, void *opaque, int version_id); |
536 | 6a00d601 | bellard | |
537 | faea38e7 | bellard | void do_savevm(const char *name); |
538 | faea38e7 | bellard | void do_loadvm(const char *name); |
539 | faea38e7 | bellard | void do_delvm(const char *name); |
540 | faea38e7 | bellard | void do_info_snapshots(void); |
541 | faea38e7 | bellard | |
542 | 4728efa3 | bellard | /* monitor.c */
|
543 | 4728efa3 | bellard | void monitor_init(CharDriverState *hd, int show_banner); |
544 | 4728efa3 | bellard | void term_puts(const char *str); |
545 | 4728efa3 | bellard | void term_vprintf(const char *fmt, va_list ap); |
546 | 4728efa3 | bellard | void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2))); |
547 | 4728efa3 | bellard | void term_print_filename(const char *filename); |
548 | 4728efa3 | bellard | void term_flush(void); |
549 | 4728efa3 | bellard | void term_print_help(void); |
550 | 4728efa3 | bellard | void monitor_readline(const char *prompt, int is_password, |
551 | 4728efa3 | bellard | char *buf, int buf_size); |
552 | 4728efa3 | bellard | |
553 | 4728efa3 | bellard | /* readline.c */
|
554 | 4728efa3 | bellard | typedef void ReadLineFunc(void *opaque, const char *str); |
555 | 4728efa3 | bellard | |
556 | 4728efa3 | bellard | extern int completion_index; |
557 | 4728efa3 | bellard | void add_completion(const char *str); |
558 | 4728efa3 | bellard | void readline_handle_byte(int ch); |
559 | 4728efa3 | bellard | void readline_find_completion(const char *cmdline); |
560 | 4728efa3 | bellard | const char *readline_get_history(unsigned int index); |
561 | 4728efa3 | bellard | void readline_start(const char *prompt, int is_password, |
562 | 4728efa3 | bellard | ReadLineFunc *readline_func, void *opaque);
|
563 | 4728efa3 | bellard | |
564 | 4728efa3 | bellard | void kqemu_record_dump(void); |
565 | 4728efa3 | bellard | |
566 | 2a324a26 | bellard | /* sdl.c */
|
567 | 2a324a26 | bellard | void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); |
568 | 2a324a26 | bellard | |
569 | 2a324a26 | bellard | /* cocoa.m */
|
570 | 2a324a26 | bellard | void cocoa_display_init(DisplayState *ds, int full_screen); |
571 | 2a324a26 | bellard | |
572 | 2a324a26 | bellard | /* vnc.c */
|
573 | 2a324a26 | bellard | void vnc_display_init(DisplayState *ds);
|
574 | 2a324a26 | bellard | void vnc_display_close(DisplayState *ds);
|
575 | 2a324a26 | bellard | int vnc_display_open(DisplayState *ds, const char *display); |
576 | 2a324a26 | bellard | int vnc_display_password(DisplayState *ds, const char *password); |
577 | 2a324a26 | bellard | void do_info_vnc(void); |
578 | 2a324a26 | bellard | |
579 | 2a324a26 | bellard | /* x_keymap.c */
|
580 | 2a324a26 | bellard | extern uint8_t _translate_keycode(const int key); |
581 | 2a324a26 | bellard | |
582 | faf07963 | pbrook | #ifdef NEED_CPU_H
|
583 | 54fa5af5 | bellard | |
584 | 5fafdf24 | ths | typedef void QEMUMachineInitFunc(int ram_size, int vga_ram_size, |
585 | 6ac0e82d | balrog | const char *boot_device, |
586 | 54fa5af5 | bellard | DisplayState *ds, const char **fd_filename, int snapshot, |
587 | 54fa5af5 | bellard | const char *kernel_filename, const char *kernel_cmdline, |
588 | 94fc95cd | j_mayer | const char *initrd_filename, const char *cpu_model); |
589 | 54fa5af5 | bellard | |
590 | 54fa5af5 | bellard | typedef struct QEMUMachine { |
591 | 54fa5af5 | bellard | const char *name; |
592 | 54fa5af5 | bellard | const char *desc; |
593 | 54fa5af5 | bellard | QEMUMachineInitFunc *init; |
594 | 54fa5af5 | bellard | struct QEMUMachine *next;
|
595 | 54fa5af5 | bellard | } QEMUMachine; |
596 | 54fa5af5 | bellard | |
597 | 54fa5af5 | bellard | int qemu_register_machine(QEMUMachine *m);
|
598 | 54fa5af5 | bellard | |
599 | 54fa5af5 | bellard | typedef void SetIRQFunc(void *opaque, int irq_num, int level); |
600 | 54fa5af5 | bellard | |
601 | d537cf6c | pbrook | #include "hw/irq.h" |
602 | d537cf6c | pbrook | |
603 | 26aa7d72 | bellard | /* ISA bus */
|
604 | 26aa7d72 | bellard | |
605 | 26aa7d72 | bellard | extern target_phys_addr_t isa_mem_base;
|
606 | 26aa7d72 | bellard | |
607 | 26aa7d72 | bellard | typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data); |
608 | 26aa7d72 | bellard | typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address); |
609 | 26aa7d72 | bellard | |
610 | 5fafdf24 | ths | int register_ioport_read(int start, int length, int size, |
611 | 26aa7d72 | bellard | IOPortReadFunc *func, void *opaque);
|
612 | 5fafdf24 | ths | int register_ioport_write(int start, int length, int size, |
613 | 26aa7d72 | bellard | IOPortWriteFunc *func, void *opaque);
|
614 | 69b91039 | bellard | void isa_unassign_ioport(int start, int length); |
615 | 69b91039 | bellard | |
616 | aef445bd | pbrook | void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
|
617 | aef445bd | pbrook | |
618 | 69b91039 | bellard | /* PCI bus */
|
619 | 69b91039 | bellard | |
620 | 69b91039 | bellard | extern target_phys_addr_t pci_mem_base;
|
621 | 69b91039 | bellard | |
622 | 46e50e9d | bellard | typedef struct PCIBus PCIBus; |
623 | 69b91039 | bellard | typedef struct PCIDevice PCIDevice; |
624 | 69b91039 | bellard | |
625 | 5fafdf24 | ths | typedef void PCIConfigWriteFunc(PCIDevice *pci_dev, |
626 | 69b91039 | bellard | uint32_t address, uint32_t data, int len);
|
627 | 5fafdf24 | ths | typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
|
628 | 69b91039 | bellard | uint32_t address, int len);
|
629 | 5fafdf24 | ths | typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num, |
630 | 69b91039 | bellard | uint32_t addr, uint32_t size, int type);
|
631 | 69b91039 | bellard | |
632 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_MEM 0x00 |
633 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_IO 0x01 |
634 | 69b91039 | bellard | #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08 |
635 | 69b91039 | bellard | |
636 | 69b91039 | bellard | typedef struct PCIIORegion { |
637 | 5768f5ac | bellard | uint32_t addr; /* current PCI mapping address. -1 means not mapped */
|
638 | 69b91039 | bellard | uint32_t size; |
639 | 69b91039 | bellard | uint8_t type; |
640 | 69b91039 | bellard | PCIMapIORegionFunc *map_func; |
641 | 69b91039 | bellard | } PCIIORegion; |
642 | 69b91039 | bellard | |
643 | 8a8696a3 | bellard | #define PCI_ROM_SLOT 6 |
644 | 8a8696a3 | bellard | #define PCI_NUM_REGIONS 7 |
645 | 502a5395 | pbrook | |
646 | 502a5395 | pbrook | #define PCI_DEVICES_MAX 64 |
647 | 502a5395 | pbrook | |
648 | 502a5395 | pbrook | #define PCI_VENDOR_ID 0x00 /* 16 bits */ |
649 | 502a5395 | pbrook | #define PCI_DEVICE_ID 0x02 /* 16 bits */ |
650 | 502a5395 | pbrook | #define PCI_COMMAND 0x04 /* 16 bits */ |
651 | 502a5395 | pbrook | #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */ |
652 | 502a5395 | pbrook | #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */ |
653 | 502a5395 | pbrook | #define PCI_CLASS_DEVICE 0x0a /* Device class */ |
654 | 502a5395 | pbrook | #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */ |
655 | 502a5395 | pbrook | #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */ |
656 | 502a5395 | pbrook | #define PCI_MIN_GNT 0x3e /* 8 bits */ |
657 | 502a5395 | pbrook | #define PCI_MAX_LAT 0x3f /* 8 bits */ |
658 | 502a5395 | pbrook | |
659 | 69b91039 | bellard | struct PCIDevice {
|
660 | 69b91039 | bellard | /* PCI config space */
|
661 | 69b91039 | bellard | uint8_t config[256];
|
662 | 69b91039 | bellard | |
663 | 69b91039 | bellard | /* the following fields are read only */
|
664 | 46e50e9d | bellard | PCIBus *bus; |
665 | 69b91039 | bellard | int devfn;
|
666 | 69b91039 | bellard | char name[64]; |
667 | 8a8696a3 | bellard | PCIIORegion io_regions[PCI_NUM_REGIONS]; |
668 | 3b46e624 | ths | |
669 | 69b91039 | bellard | /* do not access the following fields */
|
670 | 69b91039 | bellard | PCIConfigReadFunc *config_read; |
671 | 69b91039 | bellard | PCIConfigWriteFunc *config_write; |
672 | 502a5395 | pbrook | /* ??? This is a PC-specific hack, and should be removed. */
|
673 | 5768f5ac | bellard | int irq_index;
|
674 | d2b59317 | pbrook | |
675 | d537cf6c | pbrook | /* IRQ objects for the INTA-INTD pins. */
|
676 | d537cf6c | pbrook | qemu_irq *irq; |
677 | d537cf6c | pbrook | |
678 | d2b59317 | pbrook | /* Current IRQ levels. Used internally by the generic PCI code. */
|
679 | d2b59317 | pbrook | int irq_state[4]; |
680 | 69b91039 | bellard | }; |
681 | 69b91039 | bellard | |
682 | 46e50e9d | bellard | PCIDevice *pci_register_device(PCIBus *bus, const char *name, |
683 | 46e50e9d | bellard | int instance_size, int devfn, |
684 | 5fafdf24 | ths | PCIConfigReadFunc *config_read, |
685 | 69b91039 | bellard | PCIConfigWriteFunc *config_write); |
686 | 69b91039 | bellard | |
687 | 5fafdf24 | ths | void pci_register_io_region(PCIDevice *pci_dev, int region_num, |
688 | 5fafdf24 | ths | uint32_t size, int type,
|
689 | 69b91039 | bellard | PCIMapIORegionFunc *map_func); |
690 | 69b91039 | bellard | |
691 | 5fafdf24 | ths | uint32_t pci_default_read_config(PCIDevice *d, |
692 | 5768f5ac | bellard | uint32_t address, int len);
|
693 | 5fafdf24 | ths | void pci_default_write_config(PCIDevice *d,
|
694 | 5768f5ac | bellard | uint32_t address, uint32_t val, int len);
|
695 | 89b6b508 | bellard | void pci_device_save(PCIDevice *s, QEMUFile *f);
|
696 | 89b6b508 | bellard | int pci_device_load(PCIDevice *s, QEMUFile *f);
|
697 | 5768f5ac | bellard | |
698 | d537cf6c | pbrook | typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level); |
699 | d2b59317 | pbrook | typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num); |
700 | d2b59317 | pbrook | PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq, |
701 | d537cf6c | pbrook | qemu_irq *pic, int devfn_min, int nirq); |
702 | 502a5395 | pbrook | |
703 | abcebc7e | ths | void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn); |
704 | 502a5395 | pbrook | void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len); |
705 | 502a5395 | pbrook | uint32_t pci_data_read(void *opaque, uint32_t addr, int len); |
706 | 502a5395 | pbrook | int pci_bus_num(PCIBus *s);
|
707 | 80b3ada7 | pbrook | void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d)); |
708 | 9995c51f | bellard | |
709 | 5768f5ac | bellard | void pci_info(void); |
710 | 80b3ada7 | pbrook | PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
|
711 | 80b3ada7 | pbrook | pci_map_irq_fn map_irq, const char *name); |
712 | 26aa7d72 | bellard | |
713 | 502a5395 | pbrook | /* prep_pci.c */
|
714 | d537cf6c | pbrook | PCIBus *pci_prep_init(qemu_irq *pic); |
715 | 77d4bc34 | bellard | |
716 | 502a5395 | pbrook | /* apb_pci.c */
|
717 | 5b9693dc | blueswir1 | PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, |
718 | d537cf6c | pbrook | qemu_irq *pic); |
719 | 502a5395 | pbrook | |
720 | d537cf6c | pbrook | PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview); |
721 | 502a5395 | pbrook | |
722 | 502a5395 | pbrook | /* piix_pci.c */
|
723 | d537cf6c | pbrook | PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic); |
724 | f00fc47c | bellard | void i440fx_set_smm(PCIDevice *d, int val); |
725 | 8f1c91d8 | ths | int piix3_init(PCIBus *bus, int devfn); |
726 | f00fc47c | bellard | void i440fx_init_memory_mappings(PCIDevice *d);
|
727 | a41b2ff2 | pbrook | |
728 | 5856de80 | ths | int piix4_init(PCIBus *bus, int devfn); |
729 | 5856de80 | ths | |
730 | 28b9b5af | bellard | /* openpic.c */
|
731 | e9df014c | j_mayer | /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
|
732 | 47103572 | j_mayer | enum {
|
733 | e9df014c | j_mayer | OPENPIC_OUTPUT_INT = 0, /* IRQ */ |
734 | e9df014c | j_mayer | OPENPIC_OUTPUT_CINT, /* critical IRQ */
|
735 | e9df014c | j_mayer | OPENPIC_OUTPUT_MCK, /* Machine check event */
|
736 | e9df014c | j_mayer | OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
|
737 | e9df014c | j_mayer | OPENPIC_OUTPUT_RESET, /* Core reset event */
|
738 | e9df014c | j_mayer | OPENPIC_OUTPUT_NB, |
739 | 47103572 | j_mayer | }; |
740 | e9df014c | j_mayer | qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus, |
741 | e9df014c | j_mayer | qemu_irq **irqs, qemu_irq irq_out); |
742 | 28b9b5af | bellard | |
743 | fde7d5bd | ths | /* gt64xxx.c */
|
744 | d537cf6c | pbrook | PCIBus *pci_gt64120_init(qemu_irq *pic); |
745 | fde7d5bd | ths | |
746 | 6a36d84e | bellard | #ifdef HAS_AUDIO
|
747 | 6a36d84e | bellard | struct soundhw {
|
748 | 6a36d84e | bellard | const char *name; |
749 | 6a36d84e | bellard | const char *descr; |
750 | 6a36d84e | bellard | int enabled;
|
751 | 6a36d84e | bellard | int isa;
|
752 | 6a36d84e | bellard | union {
|
753 | d537cf6c | pbrook | int (*init_isa) (AudioState *s, qemu_irq *pic);
|
754 | 6a36d84e | bellard | int (*init_pci) (PCIBus *bus, AudioState *s);
|
755 | 6a36d84e | bellard | } init; |
756 | 6a36d84e | bellard | }; |
757 | 6a36d84e | bellard | |
758 | 6a36d84e | bellard | extern struct soundhw soundhw[]; |
759 | 6a36d84e | bellard | #endif
|
760 | 6a36d84e | bellard | |
761 | 313aa567 | bellard | /* vga.c */
|
762 | 313aa567 | bellard | |
763 | eee0b836 | blueswir1 | #ifndef TARGET_SPARC
|
764 | 74a14f22 | bellard | #define VGA_RAM_SIZE (8192 * 1024) |
765 | eee0b836 | blueswir1 | #else
|
766 | eee0b836 | blueswir1 | #define VGA_RAM_SIZE (9 * 1024 * 1024) |
767 | eee0b836 | blueswir1 | #endif
|
768 | 313aa567 | bellard | |
769 | 5fafdf24 | ths | int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
770 | 89b6b508 | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
771 | 5fafdf24 | ths | int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
772 | 89b6b508 | bellard | unsigned long vga_ram_offset, int vga_ram_size, |
773 | 89b6b508 | bellard | unsigned long vga_bios_offset, int vga_bios_size); |
774 | 2abec30b | ths | int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
|
775 | 2abec30b | ths | unsigned long vga_ram_offset, int vga_ram_size, |
776 | 2abec30b | ths | target_phys_addr_t vram_base, target_phys_addr_t ctrl_base, |
777 | 2abec30b | ths | int it_shift);
|
778 | 313aa567 | bellard | |
779 | d6bfa22f | bellard | /* cirrus_vga.c */
|
780 | 5fafdf24 | ths | void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
781 | d6bfa22f | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
782 | 5fafdf24 | ths | void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
|
783 | d6bfa22f | bellard | unsigned long vga_ram_offset, int vga_ram_size); |
784 | d6bfa22f | bellard | |
785 | d34cab9f | ths | /* vmware_vga.c */
|
786 | d34cab9f | ths | void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
|
787 | d34cab9f | ths | unsigned long vga_ram_offset, int vga_ram_size); |
788 | d34cab9f | ths | |
789 | 5391d806 | bellard | /* ide.c */
|
790 | 5391d806 | bellard | #define MAX_DISKS 4 |
791 | 5391d806 | bellard | |
792 | faea38e7 | bellard | extern BlockDriverState *bs_table[MAX_DISKS + 1]; |
793 | a1bb27b1 | pbrook | extern BlockDriverState *sd_bdrv;
|
794 | 3e3d5815 | balrog | extern BlockDriverState *mtd_bdrv;
|
795 | 5391d806 | bellard | |
796 | d537cf6c | pbrook | void isa_ide_init(int iobase, int iobase2, qemu_irq irq, |
797 | 69b91039 | bellard | BlockDriverState *hd0, BlockDriverState *hd1); |
798 | 54fa5af5 | bellard | void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
|
799 | 54fa5af5 | bellard | int secondary_ide_enabled);
|
800 | d537cf6c | pbrook | void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
801 | d537cf6c | pbrook | qemu_irq *pic); |
802 | afcc3cdf | ths | void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn, |
803 | afcc3cdf | ths | qemu_irq *pic); |
804 | 5391d806 | bellard | |
805 | 2e5d83bb | pbrook | /* cdrom.c */
|
806 | 2e5d83bb | pbrook | int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track); |
807 | 2e5d83bb | pbrook | int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num); |
808 | 2e5d83bb | pbrook | |
809 | 9542611a | ths | /* ds1225y.c */
|
810 | 9542611a | ths | typedef struct ds1225y_t ds1225y_t; |
811 | 71db710f | blueswir1 | ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename); |
812 | 9542611a | ths | |
813 | 1d14ffa9 | bellard | /* es1370.c */
|
814 | c0fe3827 | bellard | int es1370_init (PCIBus *bus, AudioState *s);
|
815 | 1d14ffa9 | bellard | |
816 | fb065187 | bellard | /* sb16.c */
|
817 | d537cf6c | pbrook | int SB16_init (AudioState *s, qemu_irq *pic);
|
818 | fb065187 | bellard | |
819 | fb065187 | bellard | /* adlib.c */
|
820 | d537cf6c | pbrook | int Adlib_init (AudioState *s, qemu_irq *pic);
|
821 | fb065187 | bellard | |
822 | fb065187 | bellard | /* gus.c */
|
823 | d537cf6c | pbrook | int GUS_init (AudioState *s, qemu_irq *pic);
|
824 | 27503323 | bellard | |
825 | 27503323 | bellard | /* dma.c */
|
826 | 85571bc7 | bellard | typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size); |
827 | 27503323 | bellard | int DMA_get_channel_mode (int nchan); |
828 | 85571bc7 | bellard | int DMA_read_memory (int nchan, void *buf, int pos, int size); |
829 | 85571bc7 | bellard | int DMA_write_memory (int nchan, void *buf, int pos, int size); |
830 | 27503323 | bellard | void DMA_hold_DREQ (int nchan); |
831 | 27503323 | bellard | void DMA_release_DREQ (int nchan); |
832 | 16f62432 | bellard | void DMA_schedule(int nchan); |
833 | 27503323 | bellard | void DMA_run (void); |
834 | 28b9b5af | bellard | void DMA_init (int high_page_enable); |
835 | 27503323 | bellard | void DMA_register_channel (int nchan, |
836 | 85571bc7 | bellard | DMA_transfer_handler transfer_handler, |
837 | 85571bc7 | bellard | void *opaque);
|
838 | 7138fcfb | bellard | /* fdc.c */
|
839 | 7138fcfb | bellard | #define MAX_FD 2 |
840 | 7138fcfb | bellard | extern BlockDriverState *fd_table[MAX_FD];
|
841 | 7138fcfb | bellard | |
842 | baca51fa | bellard | typedef struct fdctrl_t fdctrl_t; |
843 | baca51fa | bellard | |
844 | 5fafdf24 | ths | fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped, |
845 | 5dcb6b91 | blueswir1 | target_phys_addr_t io_base, |
846 | baca51fa | bellard | BlockDriverState **fds); |
847 | 741402f9 | blueswir1 | fdctrl_t *sun4m_fdctrl_init (qemu_irq irq, target_phys_addr_t io_base, |
848 | 741402f9 | blueswir1 | BlockDriverState **fds); |
849 | baca51fa | bellard | int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num); |
850 | 7138fcfb | bellard | |
851 | 663e8e51 | ths | /* eepro100.c */
|
852 | 663e8e51 | ths | |
853 | 663e8e51 | ths | void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn); |
854 | 663e8e51 | ths | void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn); |
855 | 663e8e51 | ths | void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn); |
856 | 663e8e51 | ths | |
857 | 80cabfad | bellard | /* ne2000.c */
|
858 | 80cabfad | bellard | |
859 | d537cf6c | pbrook | void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd); |
860 | abcebc7e | ths | void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn); |
861 | 80cabfad | bellard | |
862 | a41b2ff2 | pbrook | /* rtl8139.c */
|
863 | a41b2ff2 | pbrook | |
864 | abcebc7e | ths | void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn); |
865 | a41b2ff2 | pbrook | |
866 | e3c2613f | bellard | /* pcnet.c */
|
867 | e3c2613f | bellard | |
868 | abcebc7e | ths | void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn); |
869 | 70c0de96 | blueswir1 | void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque, |
870 | 2d069bab | blueswir1 | qemu_irq irq, qemu_irq *reset); |
871 | 67e999be | bellard | |
872 | 6bf5b4e8 | ths | /* mipsnet.c */
|
873 | 6bf5b4e8 | ths | void mipsnet_init(int base, qemu_irq irq, NICInfo *nd); |
874 | 6bf5b4e8 | ths | |
875 | 548df2ac | ths | /* vmmouse.c */
|
876 | 548df2ac | ths | void *vmmouse_init(void *m); |
877 | e3c2613f | bellard | |
878 | 591a6d62 | ths | /* vmport.c */
|
879 | 591a6d62 | ths | #ifdef TARGET_I386
|
880 | 591a6d62 | ths | void vmport_init(CPUState *env);
|
881 | 591a6d62 | ths | void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque); |
882 | 591a6d62 | ths | #endif
|
883 | 591a6d62 | ths | |
884 | 80cabfad | bellard | /* pckbd.c */
|
885 | 80cabfad | bellard | |
886 | b92bb99b | ths | void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
|
887 | 71db710f | blueswir1 | void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
|
888 | 71db710f | blueswir1 | target_phys_addr_t base, int it_shift);
|
889 | 80cabfad | bellard | |
890 | 80cabfad | bellard | /* mc146818rtc.c */
|
891 | 80cabfad | bellard | |
892 | 8a7ddc38 | bellard | typedef struct RTCState RTCState; |
893 | 80cabfad | bellard | |
894 | d537cf6c | pbrook | RTCState *rtc_init(int base, qemu_irq irq);
|
895 | 18c6e2ff | ths | RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
|
896 | 8a7ddc38 | bellard | void rtc_set_memory(RTCState *s, int addr, int val); |
897 | 8a7ddc38 | bellard | void rtc_set_date(RTCState *s, const struct tm *tm); |
898 | 80cabfad | bellard | |
899 | 80cabfad | bellard | /* serial.c */
|
900 | 80cabfad | bellard | |
901 | c4b1fcc0 | bellard | typedef struct SerialState SerialState; |
902 | d537cf6c | pbrook | SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
|
903 | 71db710f | blueswir1 | SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
|
904 | d537cf6c | pbrook | qemu_irq irq, CharDriverState *chr, |
905 | a4bc3afc | ths | int ioregister);
|
906 | a4bc3afc | ths | uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
|
907 | a4bc3afc | ths | void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value); |
908 | a4bc3afc | ths | uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
|
909 | a4bc3afc | ths | void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value); |
910 | a4bc3afc | ths | uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
|
911 | a4bc3afc | ths | void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value); |
912 | 80cabfad | bellard | |
913 | 6508fe59 | bellard | /* parallel.c */
|
914 | 6508fe59 | bellard | |
915 | 6508fe59 | bellard | typedef struct ParallelState ParallelState; |
916 | d537cf6c | pbrook | ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
|
917 | d60532ca | ths | ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
|
918 | 6508fe59 | bellard | |
919 | 80cabfad | bellard | /* i8259.c */
|
920 | 80cabfad | bellard | |
921 | 3de388f6 | bellard | typedef struct PicState2 PicState2; |
922 | 3de388f6 | bellard | extern PicState2 *isa_pic;
|
923 | 80cabfad | bellard | void pic_set_irq(int irq, int level); |
924 | 54fa5af5 | bellard | void pic_set_irq_new(void *opaque, int irq, int level); |
925 | d537cf6c | pbrook | qemu_irq *i8259_init(qemu_irq parent_irq); |
926 | d592d303 | bellard | void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
|
927 | d592d303 | bellard | void *alt_irq_opaque);
|
928 | 3de388f6 | bellard | int pic_read_irq(PicState2 *s);
|
929 | 3de388f6 | bellard | void pic_update_irq(PicState2 *s);
|
930 | 3de388f6 | bellard | uint32_t pic_intack_read(PicState2 *s); |
931 | c20709aa | bellard | void pic_info(void); |
932 | 4a0fb71e | bellard | void irq_info(void); |
933 | 80cabfad | bellard | |
934 | c27004ec | bellard | /* APIC */
|
935 | d592d303 | bellard | typedef struct IOAPICState IOAPICState; |
936 | d592d303 | bellard | |
937 | c27004ec | bellard | int apic_init(CPUState *env);
|
938 | 0e21e12b | ths | int apic_accept_pic_intr(CPUState *env);
|
939 | c27004ec | bellard | int apic_get_interrupt(CPUState *env);
|
940 | d592d303 | bellard | IOAPICState *ioapic_init(void);
|
941 | d592d303 | bellard | void ioapic_set_irq(void *opaque, int vector, int level); |
942 | c27004ec | bellard | |
943 | 80cabfad | bellard | /* i8254.c */
|
944 | 80cabfad | bellard | |
945 | 80cabfad | bellard | #define PIT_FREQ 1193182 |
946 | 80cabfad | bellard | |
947 | ec844b96 | bellard | typedef struct PITState PITState; |
948 | ec844b96 | bellard | |
949 | d537cf6c | pbrook | PITState *pit_init(int base, qemu_irq irq);
|
950 | ec844b96 | bellard | void pit_set_gate(PITState *pit, int channel, int val); |
951 | ec844b96 | bellard | int pit_get_gate(PITState *pit, int channel); |
952 | fd06c375 | bellard | int pit_get_initial_count(PITState *pit, int channel); |
953 | fd06c375 | bellard | int pit_get_mode(PITState *pit, int channel); |
954 | ec844b96 | bellard | int pit_get_out(PITState *pit, int channel, int64_t current_time); |
955 | 80cabfad | bellard | |
956 | 31211df1 | ths | /* jazz_led.c */
|
957 | 31211df1 | ths | extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base); |
958 | 31211df1 | ths | |
959 | fd06c375 | bellard | /* pcspk.c */
|
960 | fd06c375 | bellard | void pcspk_init(PITState *);
|
961 | d537cf6c | pbrook | int pcspk_audio_init(AudioState *, qemu_irq *pic);
|
962 | fd06c375 | bellard | |
963 | 0ff596d0 | pbrook | #include "hw/i2c.h" |
964 | 0ff596d0 | pbrook | |
965 | 3fffc223 | ths | #include "hw/smbus.h" |
966 | 3fffc223 | ths | |
967 | 6515b203 | bellard | /* acpi.c */
|
968 | 6515b203 | bellard | extern int acpi_enabled; |
969 | 7b717336 | ths | i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
|
970 | 3fffc223 | ths | void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
|
971 | 6515b203 | bellard | void acpi_bios_init(void); |
972 | 6515b203 | bellard | |
973 | f1ccf904 | ths | /* Axis ETRAX. */
|
974 | f1ccf904 | ths | extern QEMUMachine bareetraxfs_machine;
|
975 | f1ccf904 | ths | |
976 | 80cabfad | bellard | /* pc.c */
|
977 | 54fa5af5 | bellard | extern QEMUMachine pc_machine;
|
978 | 3dbbdc25 | bellard | extern QEMUMachine isapc_machine;
|
979 | 52ca8d6a | bellard | extern int fd_bootchk; |
980 | 80cabfad | bellard | |
981 | 6a00d601 | bellard | void ioport_set_a20(int enable); |
982 | 6a00d601 | bellard | int ioport_get_a20(void); |
983 | 6a00d601 | bellard | |
984 | 26aa7d72 | bellard | /* ppc.c */
|
985 | 54fa5af5 | bellard | extern QEMUMachine prep_machine;
|
986 | 54fa5af5 | bellard | extern QEMUMachine core99_machine;
|
987 | 54fa5af5 | bellard | extern QEMUMachine heathrow_machine;
|
988 | 1a6c0886 | j_mayer | extern QEMUMachine ref405ep_machine;
|
989 | 1a6c0886 | j_mayer | extern QEMUMachine taihu_machine;
|
990 | 54fa5af5 | bellard | |
991 | 6af0bf9c | bellard | /* mips_r4k.c */
|
992 | 6af0bf9c | bellard | extern QEMUMachine mips_machine;
|
993 | 6af0bf9c | bellard | |
994 | 5856de80 | ths | /* mips_malta.c */
|
995 | 5856de80 | ths | extern QEMUMachine mips_malta_machine;
|
996 | 5856de80 | ths | |
997 | ad6fe1d2 | ths | /* mips_pica61.c */
|
998 | ad6fe1d2 | ths | extern QEMUMachine mips_pica61_machine;
|
999 | ad6fe1d2 | ths | |
1000 | 6bf5b4e8 | ths | /* mips_mipssim.c */
|
1001 | 6bf5b4e8 | ths | extern QEMUMachine mips_mipssim_machine;
|
1002 | 6bf5b4e8 | ths | |
1003 | 6bf5b4e8 | ths | /* mips_int.c */
|
1004 | 6bf5b4e8 | ths | extern void cpu_mips_irq_init_cpu(CPUState *env); |
1005 | 6bf5b4e8 | ths | |
1006 | e16fe40c | ths | /* mips_timer.c */
|
1007 | e16fe40c | ths | extern void cpu_mips_clock_init(CPUState *); |
1008 | e16fe40c | ths | extern void cpu_mips_irqctrl_init (void); |
1009 | e16fe40c | ths | |
1010 | 27c7ca7e | bellard | /* shix.c */
|
1011 | 27c7ca7e | bellard | extern QEMUMachine shix_machine;
|
1012 | 27c7ca7e | bellard | |
1013 | 0d78f544 | ths | /* r2d.c */
|
1014 | 0d78f544 | ths | extern QEMUMachine r2d_machine;
|
1015 | 0d78f544 | ths | |
1016 | 8cc43fef | bellard | #ifdef TARGET_PPC
|
1017 | 47103572 | j_mayer | /* PowerPC hardware exceptions management helpers */
|
1018 | 8ecc7913 | j_mayer | typedef void (*clk_setup_cb)(void *opaque, uint32_t freq); |
1019 | 8ecc7913 | j_mayer | typedef struct clk_setup_t clk_setup_t; |
1020 | 8ecc7913 | j_mayer | struct clk_setup_t {
|
1021 | 8ecc7913 | j_mayer | clk_setup_cb cb; |
1022 | 8ecc7913 | j_mayer | void *opaque;
|
1023 | 8ecc7913 | j_mayer | }; |
1024 | 8ecc7913 | j_mayer | static inline void clk_setup (clk_setup_t *clk, uint32_t freq) |
1025 | 8ecc7913 | j_mayer | { |
1026 | 8ecc7913 | j_mayer | if (clk->cb != NULL) |
1027 | 8ecc7913 | j_mayer | (*clk->cb)(clk->opaque, freq); |
1028 | 8ecc7913 | j_mayer | } |
1029 | 8ecc7913 | j_mayer | |
1030 | 8ecc7913 | j_mayer | clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq); |
1031 | 2e719ba3 | j_mayer | /* Embedded PowerPC DCR management */
|
1032 | 2e719ba3 | j_mayer | typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn); |
1033 | 2e719ba3 | j_mayer | typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val); |
1034 | 2e719ba3 | j_mayer | int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn), |
1035 | 2e719ba3 | j_mayer | int (*dcr_write_error)(int dcrn)); |
1036 | 2e719ba3 | j_mayer | int ppc_dcr_register (CPUState *env, int dcrn, void *opaque, |
1037 | 2e719ba3 | j_mayer | dcr_read_cb drc_read, dcr_write_cb dcr_write); |
1038 | 8ecc7913 | j_mayer | clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq); |
1039 | 4a057712 | j_mayer | /* Embedded PowerPC reset */
|
1040 | 4a057712 | j_mayer | void ppc40x_core_reset (CPUState *env);
|
1041 | 4a057712 | j_mayer | void ppc40x_chip_reset (CPUState *env);
|
1042 | 4a057712 | j_mayer | void ppc40x_system_reset (CPUState *env);
|
1043 | 64201201 | bellard | void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1044 | 77d4bc34 | bellard | |
1045 | 77d4bc34 | bellard | extern CPUWriteMemoryFunc *PPC_io_write[];
|
1046 | 77d4bc34 | bellard | extern CPUReadMemoryFunc *PPC_io_read[];
|
1047 | 54fa5af5 | bellard | void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val); |
1048 | 3cbee15b | j_mayer | #endif
|
1049 | 26aa7d72 | bellard | |
1050 | e95c8d51 | bellard | /* sun4m.c */
|
1051 | 6a3b9cc9 | blueswir1 | extern QEMUMachine ss5_machine, ss10_machine, ss600mp_machine;
|
1052 | e95c8d51 | bellard | |
1053 | e95c8d51 | bellard | /* iommu.c */
|
1054 | 7fbfb139 | blueswir1 | void *iommu_init(target_phys_addr_t addr, uint32_t version);
|
1055 | 67e999be | bellard | void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr, |
1056 | a917d384 | pbrook | uint8_t *buf, int len, int is_write); |
1057 | 67e999be | bellard | static inline void sparc_iommu_memory_read(void *opaque, |
1058 | 67e999be | bellard | target_phys_addr_t addr, |
1059 | 67e999be | bellard | uint8_t *buf, int len)
|
1060 | 67e999be | bellard | { |
1061 | 67e999be | bellard | sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
|
1062 | 67e999be | bellard | } |
1063 | e95c8d51 | bellard | |
1064 | 67e999be | bellard | static inline void sparc_iommu_memory_write(void *opaque, |
1065 | 67e999be | bellard | target_phys_addr_t addr, |
1066 | 67e999be | bellard | uint8_t *buf, int len)
|
1067 | 67e999be | bellard | { |
1068 | 67e999be | bellard | sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
|
1069 | 67e999be | bellard | } |
1070 | e95c8d51 | bellard | |
1071 | e95c8d51 | bellard | /* tcx.c */
|
1072 | 5dcb6b91 | blueswir1 | void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
|
1073 | 5dcb6b91 | blueswir1 | unsigned long vram_offset, int vram_size, int width, int height, |
1074 | eee0b836 | blueswir1 | int depth);
|
1075 | e80cfcfc | bellard | |
1076 | e80cfcfc | bellard | /* slavio_intctl.c */
|
1077 | 5dcb6b91 | blueswir1 | void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
|
1078 | d537cf6c | pbrook | const uint32_t *intbit_to_level,
|
1079 | d7edfd27 | blueswir1 | qemu_irq **irq, qemu_irq **cpu_irq, |
1080 | b3a23197 | blueswir1 | qemu_irq **parent_irq, unsigned int cputimer); |
1081 | e80cfcfc | bellard | void slavio_pic_info(void *opaque); |
1082 | e80cfcfc | bellard | void slavio_irq_info(void *opaque); |
1083 | e95c8d51 | bellard | |
1084 | 5fe141fd | bellard | /* loader.c */
|
1085 | 5fe141fd | bellard | int get_image_size(const char *filename); |
1086 | 5fe141fd | bellard | int load_image(const char *filename, uint8_t *addr); |
1087 | 74287114 | ths | int load_elf(const char *filename, int64_t virt_to_phys_addend, |
1088 | 74287114 | ths | uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr); |
1089 | e80cfcfc | bellard | int load_aout(const char *filename, uint8_t *addr); |
1090 | 1c7b3754 | pbrook | int load_uboot(const char *filename, target_ulong *ep, int *is_linux); |
1091 | e80cfcfc | bellard | |
1092 | e80cfcfc | bellard | /* slavio_timer.c */
|
1093 | 81732d19 | blueswir1 | void slavio_timer_init_all(target_phys_addr_t base, qemu_irq master_irq,
|
1094 | 81732d19 | blueswir1 | qemu_irq *cpu_irqs); |
1095 | 8d5f07fa | bellard | |
1096 | e80cfcfc | bellard | /* slavio_serial.c */
|
1097 | 5dcb6b91 | blueswir1 | SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq, |
1098 | 5dcb6b91 | blueswir1 | CharDriverState *chr1, CharDriverState *chr2); |
1099 | 5dcb6b91 | blueswir1 | void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
|
1100 | e95c8d51 | bellard | |
1101 | 3475187d | bellard | /* slavio_misc.c */
|
1102 | 5dcb6b91 | blueswir1 | void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
|
1103 | 5dcb6b91 | blueswir1 | qemu_irq irq); |
1104 | 3475187d | bellard | void slavio_set_power_fail(void *opaque, int power_failing); |
1105 | 3475187d | bellard | |
1106 | 6f7e9aec | bellard | /* esp.c */
|
1107 | fa1fb14c | ths | void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1108 | 5dcb6b91 | blueswir1 | void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
|
1109 | 2d069bab | blueswir1 | void *dma_opaque, qemu_irq irq, qemu_irq *reset);
|
1110 | 67e999be | bellard | |
1111 | 67e999be | bellard | /* sparc32_dma.c */
|
1112 | 70c0de96 | blueswir1 | void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
|
1113 | 2d069bab | blueswir1 | void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
|
1114 | 5fafdf24 | ths | void ledma_memory_read(void *opaque, target_phys_addr_t addr, |
1115 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap); |
1116 | 5fafdf24 | ths | void ledma_memory_write(void *opaque, target_phys_addr_t addr, |
1117 | 9b94dc32 | bellard | uint8_t *buf, int len, int do_bswap); |
1118 | 67e999be | bellard | void espdma_memory_read(void *opaque, uint8_t *buf, int len); |
1119 | 67e999be | bellard | void espdma_memory_write(void *opaque, uint8_t *buf, int len); |
1120 | 6f7e9aec | bellard | |
1121 | b8174937 | bellard | /* cs4231.c */
|
1122 | b8174937 | bellard | void cs_init(target_phys_addr_t base, int irq, void *intctl); |
1123 | b8174937 | bellard | |
1124 | 3475187d | bellard | /* sun4u.c */
|
1125 | 3475187d | bellard | extern QEMUMachine sun4u_machine;
|
1126 | 3475187d | bellard | |
1127 | 64201201 | bellard | /* NVRAM helpers */
|
1128 | 3cbee15b | j_mayer | typedef uint32_t (*nvram_read_t)(void *private, uint32_t addr); |
1129 | 3cbee15b | j_mayer | typedef void (*nvram_write_t)(void *private, uint32_t addr, uint32_t val); |
1130 | 3cbee15b | j_mayer | typedef struct nvram_t { |
1131 | 3cbee15b | j_mayer | void *opaque;
|
1132 | 3cbee15b | j_mayer | nvram_read_t read_fn; |
1133 | 3cbee15b | j_mayer | nvram_write_t write_fn; |
1134 | 3cbee15b | j_mayer | } nvram_t; |
1135 | 3cbee15b | j_mayer | |
1136 | 64201201 | bellard | #include "hw/m48t59.h" |
1137 | 64201201 | bellard | |
1138 | 3cbee15b | j_mayer | void NVRAM_set_byte (nvram_t *nvram, uint32_t addr, uint8_t value);
|
1139 | 3cbee15b | j_mayer | uint8_t NVRAM_get_byte (nvram_t *nvram, uint32_t addr); |
1140 | 3cbee15b | j_mayer | void NVRAM_set_word (nvram_t *nvram, uint32_t addr, uint16_t value);
|
1141 | 3cbee15b | j_mayer | uint16_t NVRAM_get_word (nvram_t *nvram, uint32_t addr); |
1142 | 3cbee15b | j_mayer | void NVRAM_set_lword (nvram_t *nvram, uint32_t addr, uint32_t value);
|
1143 | 3cbee15b | j_mayer | uint32_t NVRAM_get_lword (nvram_t *nvram, uint32_t addr); |
1144 | 3cbee15b | j_mayer | void NVRAM_set_string (nvram_t *nvram, uint32_t addr,
|
1145 | 64201201 | bellard | const unsigned char *str, uint32_t max); |
1146 | 3cbee15b | j_mayer | int NVRAM_get_string (nvram_t *nvram, uint8_t *dst, uint16_t addr, int max); |
1147 | 3cbee15b | j_mayer | void NVRAM_set_crc (nvram_t *nvram, uint32_t addr,
|
1148 | 64201201 | bellard | uint32_t start, uint32_t count); |
1149 | 3cbee15b | j_mayer | int PPC_NVRAM_set_params (nvram_t *nvram, uint16_t NVRAM_size,
|
1150 | 64201201 | bellard | const unsigned char *arch, |
1151 | 64201201 | bellard | uint32_t RAM_size, int boot_device,
|
1152 | 64201201 | bellard | uint32_t kernel_image, uint32_t kernel_size, |
1153 | 28b9b5af | bellard | const char *cmdline, |
1154 | 64201201 | bellard | uint32_t initrd_image, uint32_t initrd_size, |
1155 | 28b9b5af | bellard | uint32_t NVRAM_image, |
1156 | 28b9b5af | bellard | int width, int height, int depth); |
1157 | 64201201 | bellard | |
1158 | 63066f4f | bellard | /* adb.c */
|
1159 | 63066f4f | bellard | |
1160 | 63066f4f | bellard | #define MAX_ADB_DEVICES 16 |
1161 | 63066f4f | bellard | |
1162 | e2733d20 | bellard | #define ADB_MAX_OUT_LEN 16 |
1163 | 63066f4f | bellard | |
1164 | e2733d20 | bellard | typedef struct ADBDevice ADBDevice; |
1165 | 63066f4f | bellard | |
1166 | e2733d20 | bellard | /* buf = NULL means polling */
|
1167 | e2733d20 | bellard | typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out, |
1168 | e2733d20 | bellard | const uint8_t *buf, int len); |
1169 | 12c28fed | bellard | typedef int ADBDeviceReset(ADBDevice *d); |
1170 | 12c28fed | bellard | |
1171 | 63066f4f | bellard | struct ADBDevice {
|
1172 | 63066f4f | bellard | struct ADBBusState *bus;
|
1173 | 63066f4f | bellard | int devaddr;
|
1174 | 63066f4f | bellard | int handler;
|
1175 | e2733d20 | bellard | ADBDeviceRequest *devreq; |
1176 | 12c28fed | bellard | ADBDeviceReset *devreset; |
1177 | 63066f4f | bellard | void *opaque;
|
1178 | 63066f4f | bellard | }; |
1179 | 63066f4f | bellard | |
1180 | 63066f4f | bellard | typedef struct ADBBusState { |
1181 | 63066f4f | bellard | ADBDevice devices[MAX_ADB_DEVICES]; |
1182 | 63066f4f | bellard | int nb_devices;
|
1183 | e2733d20 | bellard | int poll_index;
|
1184 | 63066f4f | bellard | } ADBBusState; |
1185 | 63066f4f | bellard | |
1186 | e2733d20 | bellard | int adb_request(ADBBusState *s, uint8_t *buf_out,
|
1187 | e2733d20 | bellard | const uint8_t *buf, int len); |
1188 | e2733d20 | bellard | int adb_poll(ADBBusState *s, uint8_t *buf_out);
|
1189 | 63066f4f | bellard | |
1190 | 5fafdf24 | ths | ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
|
1191 | 5fafdf24 | ths | ADBDeviceRequest *devreq, |
1192 | 5fafdf24 | ths | ADBDeviceReset *devreset, |
1193 | 63066f4f | bellard | void *opaque);
|
1194 | 63066f4f | bellard | void adb_kbd_init(ADBBusState *bus);
|
1195 | 63066f4f | bellard | void adb_mouse_init(ADBBusState *bus);
|
1196 | 63066f4f | bellard | |
1197 | 63066f4f | bellard | extern ADBBusState adb_bus;
|
1198 | 63066f4f | bellard | |
1199 | bb36d470 | bellard | #include "hw/usb.h" |
1200 | bb36d470 | bellard | |
1201 | a594cfbf | bellard | /* usb ports of the VM */
|
1202 | a594cfbf | bellard | |
1203 | 0d92ed30 | pbrook | void qemu_register_usb_port(USBPort *port, void *opaque, int index, |
1204 | 0d92ed30 | pbrook | usb_attachfn attach); |
1205 | a594cfbf | bellard | |
1206 | 0d92ed30 | pbrook | #define VM_USB_HUB_SIZE 8 |
1207 | a594cfbf | bellard | |
1208 | a594cfbf | bellard | void do_usb_add(const char *devname); |
1209 | a594cfbf | bellard | void do_usb_del(const char *devname); |
1210 | a594cfbf | bellard | void usb_info(void); |
1211 | a594cfbf | bellard | |
1212 | 2e5d83bb | pbrook | /* scsi-disk.c */
|
1213 | 4d611c9a | pbrook | enum scsi_reason {
|
1214 | 4d611c9a | pbrook | SCSI_REASON_DONE, /* Command complete. */
|
1215 | 4d611c9a | pbrook | SCSI_REASON_DATA /* Transfer complete, more data required. */
|
1216 | 4d611c9a | pbrook | }; |
1217 | 4d611c9a | pbrook | |
1218 | 2e5d83bb | pbrook | typedef struct SCSIDevice SCSIDevice; |
1219 | a917d384 | pbrook | typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag, |
1220 | a917d384 | pbrook | uint32_t arg); |
1221 | 2e5d83bb | pbrook | |
1222 | 2e5d83bb | pbrook | SCSIDevice *scsi_disk_init(BlockDriverState *bdrv, |
1223 | a917d384 | pbrook | int tcq,
|
1224 | 2e5d83bb | pbrook | scsi_completionfn completion, |
1225 | 2e5d83bb | pbrook | void *opaque);
|
1226 | 2e5d83bb | pbrook | void scsi_disk_destroy(SCSIDevice *s);
|
1227 | 2e5d83bb | pbrook | |
1228 | 0fc5c15a | pbrook | int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
|
1229 | 4d611c9a | pbrook | /* SCSI data transfers are asynchrnonous. However, unlike the block IO
|
1230 | 4d611c9a | pbrook | layer the completion routine may be called directly by
|
1231 | 4d611c9a | pbrook | scsi_{read,write}_data. */
|
1232 | a917d384 | pbrook | void scsi_read_data(SCSIDevice *s, uint32_t tag);
|
1233 | a917d384 | pbrook | int scsi_write_data(SCSIDevice *s, uint32_t tag);
|
1234 | a917d384 | pbrook | void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
|
1235 | a917d384 | pbrook | uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag); |
1236 | 2e5d83bb | pbrook | |
1237 | 7d8406be | pbrook | /* lsi53c895a.c */
|
1238 | 7d8406be | pbrook | void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id); |
1239 | 7d8406be | pbrook | void *lsi_scsi_init(PCIBus *bus, int devfn); |
1240 | 7d8406be | pbrook | |
1241 | b5ff1b31 | bellard | /* integratorcp.c */
|
1242 | 3371d272 | pbrook | extern QEMUMachine integratorcp_machine;
|
1243 | b5ff1b31 | bellard | |
1244 | cdbdb648 | pbrook | /* versatilepb.c */
|
1245 | cdbdb648 | pbrook | extern QEMUMachine versatilepb_machine;
|
1246 | 16406950 | pbrook | extern QEMUMachine versatileab_machine;
|
1247 | cdbdb648 | pbrook | |
1248 | e69954b9 | pbrook | /* realview.c */
|
1249 | e69954b9 | pbrook | extern QEMUMachine realview_machine;
|
1250 | e69954b9 | pbrook | |
1251 | b00052e4 | balrog | /* spitz.c */
|
1252 | b00052e4 | balrog | extern QEMUMachine akitapda_machine;
|
1253 | b00052e4 | balrog | extern QEMUMachine spitzpda_machine;
|
1254 | b00052e4 | balrog | extern QEMUMachine borzoipda_machine;
|
1255 | b00052e4 | balrog | extern QEMUMachine terrierpda_machine;
|
1256 | b00052e4 | balrog | |
1257 | 05ee37eb | balrog | /* gumstix.c */
|
1258 | 05ee37eb | balrog | extern QEMUMachine connex_machine;
|
1259 | 05ee37eb | balrog | |
1260 | c3d2689d | balrog | /* palm.c */
|
1261 | c3d2689d | balrog | extern QEMUMachine palmte_machine;
|
1262 | c3d2689d | balrog | |
1263 | 9ee6e8bb | pbrook | /* armv7m.c */
|
1264 | 9ee6e8bb | pbrook | qemu_irq *armv7m_init(int flash_size, int sram_size, |
1265 | 9ee6e8bb | pbrook | const char *kernel_filename, const char *cpu_model); |
1266 | 9ee6e8bb | pbrook | |
1267 | 9ee6e8bb | pbrook | /* stellaris.c */
|
1268 | 9ee6e8bb | pbrook | extern QEMUMachine lm3s811evb_machine;
|
1269 | 9ee6e8bb | pbrook | extern QEMUMachine lm3s6965evb_machine;
|
1270 | 9ee6e8bb | pbrook | |
1271 | daa57963 | bellard | /* ps2.c */
|
1272 | daa57963 | bellard | void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg); |
1273 | daa57963 | bellard | void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg); |
1274 | daa57963 | bellard | void ps2_write_mouse(void *, int val); |
1275 | daa57963 | bellard | void ps2_write_keyboard(void *, int val); |
1276 | daa57963 | bellard | uint32_t ps2_read_data(void *);
|
1277 | daa57963 | bellard | void ps2_queue(void *, int b); |
1278 | f94f5d71 | pbrook | void ps2_keyboard_set_translation(void *opaque, int mode); |
1279 | 548df2ac | ths | void ps2_mouse_fake_event(void *opaque); |
1280 | daa57963 | bellard | |
1281 | 80337b66 | bellard | /* smc91c111.c */
|
1282 | d537cf6c | pbrook | void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
|
1283 | 80337b66 | bellard | |
1284 | 7e1543c2 | pbrook | /* pl031.c */
|
1285 | 7e1543c2 | pbrook | void pl031_init(uint32_t base, qemu_irq irq);
|
1286 | 7e1543c2 | pbrook | |
1287 | bdd5003a | pbrook | /* pl110.c */
|
1288 | d537cf6c | pbrook | void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int); |
1289 | bdd5003a | pbrook | |
1290 | cdbdb648 | pbrook | /* pl011.c */
|
1291 | 9ee6e8bb | pbrook | enum pl011_type {
|
1292 | 9ee6e8bb | pbrook | PL011_ARM, |
1293 | 9ee6e8bb | pbrook | PL011_LUMINARY |
1294 | 9ee6e8bb | pbrook | }; |
1295 | 9ee6e8bb | pbrook | |
1296 | 9ee6e8bb | pbrook | void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr,
|
1297 | 9ee6e8bb | pbrook | enum pl011_type type);
|
1298 | 9ee6e8bb | pbrook | |
1299 | 9ee6e8bb | pbrook | /* pl022.c */
|
1300 | 9ee6e8bb | pbrook | void pl022_init(uint32_t base, qemu_irq irq, int (*xfer_cb)(void *, int), |
1301 | 9ee6e8bb | pbrook | void *opaque);
|
1302 | cdbdb648 | pbrook | |
1303 | cdbdb648 | pbrook | /* pl050.c */
|
1304 | d537cf6c | pbrook | void pl050_init(uint32_t base, qemu_irq irq, int is_mouse); |
1305 | cdbdb648 | pbrook | |
1306 | 9ee6e8bb | pbrook | /* pl061.c */
|
1307 | 9ee6e8bb | pbrook | qemu_irq *pl061_init(uint32_t base, qemu_irq irq, qemu_irq **out); |
1308 | 9ee6e8bb | pbrook | |
1309 | cdbdb648 | pbrook | /* pl080.c */
|
1310 | d537cf6c | pbrook | void *pl080_init(uint32_t base, qemu_irq irq, int nchannels); |
1311 | cdbdb648 | pbrook | |
1312 | a1bb27b1 | pbrook | /* pl181.c */
|
1313 | a1bb27b1 | pbrook | void pl181_init(uint32_t base, BlockDriverState *bd,
|
1314 | d537cf6c | pbrook | qemu_irq irq0, qemu_irq irq1); |
1315 | a1bb27b1 | pbrook | |
1316 | cdbdb648 | pbrook | /* pl190.c */
|
1317 | d537cf6c | pbrook | qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq); |
1318 | cdbdb648 | pbrook | |
1319 | cdbdb648 | pbrook | /* arm-timer.c */
|
1320 | d537cf6c | pbrook | void sp804_init(uint32_t base, qemu_irq irq);
|
1321 | d537cf6c | pbrook | void icp_pit_init(uint32_t base, qemu_irq *pic, int irq); |
1322 | cdbdb648 | pbrook | |
1323 | e69954b9 | pbrook | /* arm_sysctl.c */
|
1324 | e69954b9 | pbrook | void arm_sysctl_init(uint32_t base, uint32_t sys_id);
|
1325 | e69954b9 | pbrook | |
1326 | 9ee6e8bb | pbrook | /* realview_gic.c */
|
1327 | 9ee6e8bb | pbrook | qemu_irq *realview_gic_init(uint32_t base, qemu_irq parent_irq); |
1328 | 9ee6e8bb | pbrook | |
1329 | 9ee6e8bb | pbrook | /* mpcore.c */
|
1330 | 9ee6e8bb | pbrook | extern qemu_irq *mpcore_irq_init(qemu_irq *cpu_irq);
|
1331 | e69954b9 | pbrook | |
1332 | 16406950 | pbrook | /* arm_boot.c */
|
1333 | 16406950 | pbrook | |
1334 | daf90626 | pbrook | void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename, |
1335 | 16406950 | pbrook | const char *kernel_cmdline, const char *initrd_filename, |
1336 | 9d551997 | balrog | int board_id, target_phys_addr_t loader_start);
|
1337 | 16406950 | pbrook | |
1338 | 9ee6e8bb | pbrook | /* armv7m_nvic.c */
|
1339 | 9ee6e8bb | pbrook | qemu_irq *armv7m_nvic_init(CPUState *env); |
1340 | 9ee6e8bb | pbrook | |
1341 | 9ee6e8bb | pbrook | /* ssd0303.c */
|
1342 | 9ee6e8bb | pbrook | void ssd0303_init(DisplayState *ds, i2c_bus *bus, int address); |
1343 | 9ee6e8bb | pbrook | |
1344 | 9ee6e8bb | pbrook | /* ssd0323.c */
|
1345 | 9ee6e8bb | pbrook | int ssd0323_xfer_ssi(void *opaque, int data); |
1346 | 9ee6e8bb | pbrook | void *ssd0323_init(DisplayState *ds, qemu_irq *cmd_p);
|
1347 | 9ee6e8bb | pbrook | |
1348 | 27c7ca7e | bellard | /* sh7750.c */
|
1349 | 27c7ca7e | bellard | struct SH7750State;
|
1350 | 27c7ca7e | bellard | |
1351 | 008a8818 | pbrook | struct SH7750State *sh7750_init(CPUState * cpu);
|
1352 | 27c7ca7e | bellard | |
1353 | 27c7ca7e | bellard | typedef struct { |
1354 | 27c7ca7e | bellard | /* The callback will be triggered if any of the designated lines change */
|
1355 | 27c7ca7e | bellard | uint16_t portamask_trigger; |
1356 | 27c7ca7e | bellard | uint16_t portbmask_trigger; |
1357 | 27c7ca7e | bellard | /* Return 0 if no action was taken */
|
1358 | 27c7ca7e | bellard | int (*port_change_cb) (uint16_t porta, uint16_t portb,
|
1359 | 27c7ca7e | bellard | uint16_t * periph_pdtra, |
1360 | 27c7ca7e | bellard | uint16_t * periph_portdira, |
1361 | 27c7ca7e | bellard | uint16_t * periph_pdtrb, |
1362 | 27c7ca7e | bellard | uint16_t * periph_portdirb); |
1363 | 27c7ca7e | bellard | } sh7750_io_device; |
1364 | 27c7ca7e | bellard | |
1365 | 27c7ca7e | bellard | int sh7750_register_io_device(struct SH7750State *s, |
1366 | 27c7ca7e | bellard | sh7750_io_device * device); |
1367 | cd1a3f68 | ths | /* sh_timer.c */
|
1368 | cd1a3f68 | ths | #define TMU012_FEAT_TOCR (1 << 0) |
1369 | cd1a3f68 | ths | #define TMU012_FEAT_3CHAN (1 << 1) |
1370 | cd1a3f68 | ths | #define TMU012_FEAT_EXTCLK (1 << 2) |
1371 | cd1a3f68 | ths | void tmu012_init(uint32_t base, int feat, uint32_t freq); |
1372 | cd1a3f68 | ths | |
1373 | 2f062c72 | ths | /* sh_serial.c */
|
1374 | 2f062c72 | ths | #define SH_SERIAL_FEAT_SCIF (1 << 0) |
1375 | 2f062c72 | ths | void sh_serial_init (target_phys_addr_t base, int feat, |
1376 | 2f062c72 | ths | uint32_t freq, CharDriverState *chr); |
1377 | 2f062c72 | ths | |
1378 | 27c7ca7e | bellard | /* tc58128.c */
|
1379 | 27c7ca7e | bellard | int tc58128_init(struct SH7750State *s, char *zone1, char *zone2); |
1380 | 27c7ca7e | bellard | |
1381 | 29133e9a | bellard | /* NOR flash devices */
|
1382 | 86f55663 | j_mayer | #define MAX_PFLASH 4 |
1383 | 86f55663 | j_mayer | extern BlockDriverState *pflash_table[MAX_PFLASH];
|
1384 | 29133e9a | bellard | typedef struct pflash_t pflash_t; |
1385 | 29133e9a | bellard | |
1386 | 71db710f | blueswir1 | pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off, |
1387 | 29133e9a | bellard | BlockDriverState *bs, |
1388 | 71db710f | blueswir1 | uint32_t sector_len, int nb_blocs, int width, |
1389 | 5fafdf24 | ths | uint16_t id0, uint16_t id1, |
1390 | 29133e9a | bellard | uint16_t id2, uint16_t id3); |
1391 | 29133e9a | bellard | |
1392 | 3e3d5815 | balrog | /* nand.c */
|
1393 | 3e3d5815 | balrog | struct nand_flash_s;
|
1394 | 3e3d5815 | balrog | struct nand_flash_s *nand_init(int manf_id, int chip_id); |
1395 | 3e3d5815 | balrog | void nand_done(struct nand_flash_s *s); |
1396 | 5fafdf24 | ths | void nand_setpins(struct nand_flash_s *s, |
1397 | 3e3d5815 | balrog | int cle, int ale, int ce, int wp, int gnd); |
1398 | 3e3d5815 | balrog | void nand_getpins(struct nand_flash_s *s, int *rb); |
1399 | 3e3d5815 | balrog | void nand_setio(struct nand_flash_s *s, uint8_t value); |
1400 | 3e3d5815 | balrog | uint8_t nand_getio(struct nand_flash_s *s);
|
1401 | 3e3d5815 | balrog | |
1402 | 3e3d5815 | balrog | #define NAND_MFR_TOSHIBA 0x98 |
1403 | 3e3d5815 | balrog | #define NAND_MFR_SAMSUNG 0xec |
1404 | 3e3d5815 | balrog | #define NAND_MFR_FUJITSU 0x04 |
1405 | 3e3d5815 | balrog | #define NAND_MFR_NATIONAL 0x8f |
1406 | 3e3d5815 | balrog | #define NAND_MFR_RENESAS 0x07 |
1407 | 3e3d5815 | balrog | #define NAND_MFR_STMICRO 0x20 |
1408 | 3e3d5815 | balrog | #define NAND_MFR_HYNIX 0xad |
1409 | 3e3d5815 | balrog | #define NAND_MFR_MICRON 0x2c |
1410 | 3e3d5815 | balrog | |
1411 | 9ff6755b | balrog | /* ecc.c */
|
1412 | 9ff6755b | balrog | struct ecc_state_s {
|
1413 | 9ff6755b | balrog | uint8_t cp; /* Column parity */
|
1414 | 9ff6755b | balrog | uint16_t lp[2]; /* Line parity */ |
1415 | 9ff6755b | balrog | uint16_t count; |
1416 | 9ff6755b | balrog | }; |
1417 | 9ff6755b | balrog | |
1418 | 9ff6755b | balrog | uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
|
1419 | 9ff6755b | balrog | void ecc_reset(struct ecc_state_s *s); |
1420 | 9ff6755b | balrog | void ecc_put(QEMUFile *f, struct ecc_state_s *s); |
1421 | 9ff6755b | balrog | void ecc_get(QEMUFile *f, struct ecc_state_s *s); |
1422 | 3e3d5815 | balrog | |
1423 | fd5a3b33 | balrog | /* ads7846.c */
|
1424 | fd5a3b33 | balrog | struct ads7846_state_s;
|
1425 | fd5a3b33 | balrog | uint32_t ads7846_read(void *opaque);
|
1426 | fd5a3b33 | balrog | void ads7846_write(void *opaque, uint32_t value); |
1427 | fd5a3b33 | balrog | struct ads7846_state_s *ads7846_init(qemu_irq penirq);
|
1428 | fd5a3b33 | balrog | |
1429 | c824cacd | balrog | /* max111x.c */
|
1430 | c824cacd | balrog | struct max111x_s;
|
1431 | c824cacd | balrog | uint32_t max111x_read(void *opaque);
|
1432 | c824cacd | balrog | void max111x_write(void *opaque, uint32_t value); |
1433 | c824cacd | balrog | struct max111x_s *max1110_init(qemu_irq cb);
|
1434 | c824cacd | balrog | struct max111x_s *max1111_init(qemu_irq cb);
|
1435 | c824cacd | balrog | void max111x_set_input(struct max111x_s *s, int line, uint8_t value); |
1436 | c824cacd | balrog | |
1437 | 201a51fc | balrog | /* PCMCIA/Cardbus */
|
1438 | 201a51fc | balrog | |
1439 | 201a51fc | balrog | struct pcmcia_socket_s {
|
1440 | 201a51fc | balrog | qemu_irq irq; |
1441 | 201a51fc | balrog | int attached;
|
1442 | 201a51fc | balrog | const char *slot_string; |
1443 | 201a51fc | balrog | const char *card_string; |
1444 | 201a51fc | balrog | }; |
1445 | 201a51fc | balrog | |
1446 | 201a51fc | balrog | void pcmcia_socket_register(struct pcmcia_socket_s *socket); |
1447 | 201a51fc | balrog | void pcmcia_socket_unregister(struct pcmcia_socket_s *socket); |
1448 | 201a51fc | balrog | void pcmcia_info(void); |
1449 | 201a51fc | balrog | |
1450 | 201a51fc | balrog | struct pcmcia_card_s {
|
1451 | 201a51fc | balrog | void *state;
|
1452 | 201a51fc | balrog | struct pcmcia_socket_s *slot;
|
1453 | 201a51fc | balrog | int (*attach)(void *state); |
1454 | 201a51fc | balrog | int (*detach)(void *state); |
1455 | 201a51fc | balrog | const uint8_t *cis;
|
1456 | 201a51fc | balrog | int cis_len;
|
1457 | 201a51fc | balrog | |
1458 | 201a51fc | balrog | /* Only valid if attached */
|
1459 | 9e315fa9 | balrog | uint8_t (*attr_read)(void *state, uint32_t address);
|
1460 | 9e315fa9 | balrog | void (*attr_write)(void *state, uint32_t address, uint8_t value); |
1461 | 9e315fa9 | balrog | uint16_t (*common_read)(void *state, uint32_t address);
|
1462 | 9e315fa9 | balrog | void (*common_write)(void *state, uint32_t address, uint16_t value); |
1463 | 9e315fa9 | balrog | uint16_t (*io_read)(void *state, uint32_t address);
|
1464 | 9e315fa9 | balrog | void (*io_write)(void *state, uint32_t address, uint16_t value); |
1465 | 201a51fc | balrog | }; |
1466 | 201a51fc | balrog | |
1467 | 201a51fc | balrog | #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */ |
1468 | 201a51fc | balrog | #define CISTPL_NO_LINK 0x14 /* No Link Tuple */ |
1469 | 201a51fc | balrog | #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */ |
1470 | 201a51fc | balrog | #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */ |
1471 | 201a51fc | balrog | #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */ |
1472 | 201a51fc | balrog | #define CISTPL_CONFIG 0x1a /* Configuration Tuple */ |
1473 | 201a51fc | balrog | #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */ |
1474 | 201a51fc | balrog | #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */ |
1475 | 201a51fc | balrog | #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */ |
1476 | 201a51fc | balrog | #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */ |
1477 | 201a51fc | balrog | #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */ |
1478 | 201a51fc | balrog | #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */ |
1479 | 201a51fc | balrog | #define CISTPL_FUNCID 0x21 /* Function ID Tuple */ |
1480 | 201a51fc | balrog | #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */ |
1481 | 201a51fc | balrog | #define CISTPL_END 0xff /* Tuple End */ |
1482 | 201a51fc | balrog | #define CISTPL_ENDMARK 0xff |
1483 | 201a51fc | balrog | |
1484 | 201a51fc | balrog | /* dscm1xxxx.c */
|
1485 | 201a51fc | balrog | struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
|
1486 | 201a51fc | balrog | |
1487 | 6963d7af | pbrook | /* ptimer.c */
|
1488 | 6963d7af | pbrook | typedef struct ptimer_state ptimer_state; |
1489 | 6963d7af | pbrook | typedef void (*ptimer_cb)(void *opaque); |
1490 | 6963d7af | pbrook | |
1491 | 6963d7af | pbrook | ptimer_state *ptimer_init(QEMUBH *bh); |
1492 | 6963d7af | pbrook | void ptimer_set_period(ptimer_state *s, int64_t period);
|
1493 | 6963d7af | pbrook | void ptimer_set_freq(ptimer_state *s, uint32_t freq);
|
1494 | 8d05ea8a | blueswir1 | void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload); |
1495 | 8d05ea8a | blueswir1 | uint64_t ptimer_get_count(ptimer_state *s); |
1496 | 8d05ea8a | blueswir1 | void ptimer_set_count(ptimer_state *s, uint64_t count);
|
1497 | 6963d7af | pbrook | void ptimer_run(ptimer_state *s, int oneshot); |
1498 | 6963d7af | pbrook | void ptimer_stop(ptimer_state *s);
|
1499 | 8d05ea8a | blueswir1 | void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
|
1500 | 8d05ea8a | blueswir1 | void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
|
1501 | 6963d7af | pbrook | |
1502 | c1713132 | balrog | #include "hw/pxa.h" |
1503 | c1713132 | balrog | |
1504 | c3d2689d | balrog | #include "hw/omap.h" |
1505 | c3d2689d | balrog | |
1506 | 3efda49d | balrog | /* tsc210x.c */
|
1507 | d8f699cb | balrog | struct uwire_slave_s *tsc2102_init(qemu_irq pint, AudioState *audio);
|
1508 | d8f699cb | balrog | struct i2s_codec_s *tsc210x_codec(struct uwire_slave_s *chip); |
1509 | 3efda49d | balrog | |
1510 | 20dcee94 | pbrook | /* mcf_uart.c */
|
1511 | 20dcee94 | pbrook | uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
|
1512 | 20dcee94 | pbrook | void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val); |
1513 | 20dcee94 | pbrook | void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
|
1514 | 20dcee94 | pbrook | void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
|
1515 | 20dcee94 | pbrook | CharDriverState *chr); |
1516 | 20dcee94 | pbrook | |
1517 | 20dcee94 | pbrook | /* mcf_intc.c */
|
1518 | 20dcee94 | pbrook | qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env); |
1519 | 20dcee94 | pbrook | |
1520 | 7e049b8a | pbrook | /* mcf_fec.c */
|
1521 | 7e049b8a | pbrook | void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
|
1522 | 7e049b8a | pbrook | |
1523 | 0633879f | pbrook | /* mcf5206.c */
|
1524 | 0633879f | pbrook | qemu_irq *mcf5206_init(uint32_t base, CPUState *env); |
1525 | 0633879f | pbrook | |
1526 | 0633879f | pbrook | /* an5206.c */
|
1527 | 0633879f | pbrook | extern QEMUMachine an5206_machine;
|
1528 | 0633879f | pbrook | |
1529 | 20dcee94 | pbrook | /* mcf5208.c */
|
1530 | 20dcee94 | pbrook | extern QEMUMachine mcf5208evb_machine;
|
1531 | 20dcee94 | pbrook | |
1532 | ca02f319 | pbrook | /* dummy_m68k.c */
|
1533 | ca02f319 | pbrook | extern QEMUMachine dummy_m68k_machine;
|
1534 | ca02f319 | pbrook | |
1535 | 4046d913 | pbrook | #include "gdbstub.h" |
1536 | 4046d913 | pbrook | |
1537 | faf07963 | pbrook | #endif /* defined(NEED_CPU_H) */ |
1538 | fc01f7e7 | bellard | #endif /* VL_H */ |