Revision 38641a52 hw/pxa2xx_gpio.c
| b/hw/pxa2xx_gpio.c | ||
|---|---|---|
| 16 | 16 |
qemu_irq *pic; |
| 17 | 17 |
int lines; |
| 18 | 18 |
CPUState *cpu_env; |
| 19 |
qemu_irq *in; |
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| 19 | 20 |
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| 20 | 21 |
/* XXX: GNU C vectors are more suitable */ |
| 21 | 22 |
uint32_t ilevel[PXA2XX_GPIO_BANKS]; |
| ... | ... | |
| 28 | 29 |
uint32_t gafr[PXA2XX_GPIO_BANKS * 2]; |
| 29 | 30 |
|
| 30 | 31 |
uint32_t prev_level[PXA2XX_GPIO_BANKS]; |
| 31 |
struct {
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gpio_handler_t fn; |
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void *opaque; |
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} handler[PXA2XX_GPIO_BANKS * 32]; |
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void (*read_notify)(void *opaque); |
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void *opaque; |
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qemu_irq handler[PXA2XX_GPIO_BANKS * 32]; |
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qemu_irq read_notify; |
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| 38 | 34 |
}; |
| 39 | 35 |
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| 40 | 36 |
static struct {
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| ... | ... | |
| 86 | 82 |
} |
| 87 | 83 |
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/* Bitmap of pins used as standby and sleep wake-up sources. */ |
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const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
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static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
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0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f, |
| 91 | 87 |
}; |
| 92 | 88 |
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void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level)
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static void pxa2xx_gpio_set(void *opaque, int line, int level)
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{
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struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque; |
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| 95 | 92 |
int bank; |
| 96 | 93 |
uint32_t mask; |
| 97 | 94 |
|
| ... | ... | |
| 130 | 127 |
for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
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| 131 | 128 |
bit = ffs(diff) - 1; |
| 132 | 129 |
line = bit + 32 * i; |
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if (s->handler[line].fn) |
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s->handler[line].fn(line, (level >> bit) & 1, |
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s->handler[line].opaque); |
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qemu_set_irq(s->handler[line], (level >> bit) & 1); |
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| 136 | 131 |
} |
| 137 | 132 |
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| 138 | 133 |
s->prev_level[i] = level; |
| ... | ... | |
| 173 | 168 |
case GPLR: /* GPIO Pin-Level registers */ |
| 174 | 169 |
ret = (s->olevel[bank] & s->dir[bank]) | |
| 175 | 170 |
(s->ilevel[bank] & ~s->dir[bank]); |
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if (s->read_notify) |
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s->read_notify(s->opaque); |
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qemu_irq_raise(s->read_notify); |
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| 178 | 172 |
return ret; |
| 179 | 173 |
|
| 180 | 174 |
case GEDR: /* GPIO Edge Detect Status registers */ |
| ... | ... | |
| 312 | 306 |
s->pic = pic; |
| 313 | 307 |
s->lines = lines; |
| 314 | 308 |
s->cpu_env = env; |
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s->in = qemu_allocate_irqs(pxa2xx_gpio_set, s, lines); |
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| 315 | 310 |
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| 316 | 311 |
iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn, |
| 317 | 312 |
pxa2xx_gpio_writefn, s); |
| ... | ... | |
| 323 | 318 |
return s; |
| 324 | 319 |
} |
| 325 | 320 |
|
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void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line, |
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gpio_handler_t handler, void *opaque) {
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qemu_irq *pxa2xx_gpio_in_get(struct pxa2xx_gpio_info_s *s) |
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{
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return s->in; |
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} |
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void pxa2xx_gpio_out_set(struct pxa2xx_gpio_info_s *s, |
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int line, qemu_irq handler) |
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{
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if (line >= s->lines) {
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printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
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return; |
| 331 | 332 |
} |
| 332 | 333 |
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s->handler[line].fn = handler; |
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s->handler[line].opaque = opaque; |
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s->handler[line] = handler; |
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| 335 | 335 |
} |
| 336 | 336 |
|
| 337 | 337 |
/* |
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* Registers a callback to notify on GPLR reads. This normally |
| 339 | 339 |
* shouldn't be needed but it is used for the hack on Spitz machines. |
| 340 | 340 |
*/ |
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void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, |
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void (*handler)(void *opaque), void *opaque) {
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void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s, qemu_irq handler)
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{
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| 343 | 343 |
s->read_notify = handler; |
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s->opaque = opaque; |
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| 345 | 344 |
} |
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