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/*
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 * Tiny Code Generator for QEMU
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 *
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 * Copyright (c) 2008 Fabrice Bellard
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
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 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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#include "tcg.h"
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#ifdef CONFIG_DYNGEN_OP
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/* legacy dyngen operations */
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#include "gen-op.h"
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#endif
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int gen_new_label(void);
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static inline void tcg_gen_op1(int opc, TCGv arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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}
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static inline void tcg_gen_op1i(int opc, TCGArg arg1)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = arg1;
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}
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static inline void tcg_gen_op2(int opc, TCGv arg1, TCGv arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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}
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static inline void tcg_gen_op2i(int opc, TCGv arg1, TCGArg arg2)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = arg2;
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}
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static inline void tcg_gen_op3(int opc, TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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}
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static inline void tcg_gen_op3i(int opc, TCGv arg1, TCGv arg2, TCGArg arg3)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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}
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static inline void tcg_gen_op4(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                               TCGv arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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}
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static inline void tcg_gen_op4i(int opc, TCGv arg1, TCGv arg2, TCGv arg3, 
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                                TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op4ii(int opc, TCGv arg1, TCGv arg2, TCGArg arg3, 
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                                 TCGArg arg4)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = arg3;
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    *gen_opparam_ptr++ = arg4;
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}
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static inline void tcg_gen_op5(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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}
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static inline void tcg_gen_op5i(int opc, TCGv arg1, TCGv arg2, 
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                                TCGv arg3, TCGv arg4,
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                                TCGArg arg5)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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}
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static inline void tcg_gen_op6(int opc, TCGv arg1, TCGv arg2, 
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                               TCGv arg3, TCGv arg4,
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                               TCGv arg5, TCGv arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = GET_TCGV(arg5);
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    *gen_opparam_ptr++ = GET_TCGV(arg6);
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}
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static inline void tcg_gen_op6ii(int opc, TCGv arg1, TCGv arg2, 
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                                 TCGv arg3, TCGv arg4,
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                                 TCGArg arg5, TCGArg arg6)
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{
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    *gen_opc_ptr++ = opc;
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    *gen_opparam_ptr++ = GET_TCGV(arg1);
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    *gen_opparam_ptr++ = GET_TCGV(arg2);
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    *gen_opparam_ptr++ = GET_TCGV(arg3);
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    *gen_opparam_ptr++ = GET_TCGV(arg4);
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    *gen_opparam_ptr++ = arg5;
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    *gen_opparam_ptr++ = arg6;
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}
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static inline void gen_set_label(int n)
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{
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    tcg_gen_op1i(INDEX_op_set_label, n);
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}
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static inline void tcg_gen_br(int label)
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{
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    tcg_gen_op1i(INDEX_op_br, label);
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}
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static inline void tcg_gen_mov_i32(TCGv ret, TCGv arg)
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{
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    if (GET_TCGV(ret) != GET_TCGV(arg))
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        tcg_gen_op2(INDEX_op_mov_i32, ret, arg);
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}
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static inline void tcg_gen_movi_i32(TCGv ret, int32_t arg)
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{
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    tcg_gen_op2i(INDEX_op_movi_i32, ret, arg);
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}
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/* helper calls */
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#define TCG_HELPER_CALL_FLAGS 0
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static inline void tcg_gen_helper_0_0(void *func)
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{
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 0, NULL);
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}
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static inline void tcg_gen_helper_0_1(void *func, TCGv arg)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 1, &arg);
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}
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static inline void tcg_gen_helper_0_2(void *func, TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 2, args);
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}
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static inline void tcg_gen_helper_0_3(void *func,
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                                      TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    TCGv args[3];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 3, args);
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}
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static inline void tcg_gen_helper_0_4(void *func, TCGv arg1, TCGv arg2,
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                                      TCGv arg3, TCGv arg4)
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{
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    TCGv args[4];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 0, NULL, 4, args);
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}
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static inline void tcg_gen_helper_1_0(void *func, TCGv ret)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 0, NULL);
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}
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static inline void tcg_gen_helper_1_1(void *func, TCGv ret, TCGv arg1)
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{
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 1, &arg1);
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}
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static inline void tcg_gen_helper_1_2(void *func, TCGv ret, 
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                                      TCGv arg1, TCGv arg2)
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{
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    TCGv args[2];
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    args[0] = arg1;
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    args[1] = arg2;
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    tcg_gen_call(&tcg_ctx, 
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 2, args);
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}
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static inline void tcg_gen_helper_1_3(void *func, TCGv ret,
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                                      TCGv arg1, TCGv arg2, TCGv arg3)
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{
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    TCGv args[3];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 3, args);
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}
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static inline void tcg_gen_helper_1_4(void *func, TCGv ret,
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                                      TCGv arg1, TCGv arg2, TCGv arg3,
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                                      TCGv arg4)
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{
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    TCGv args[4];
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    args[0] = arg1;
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    args[1] = arg2;
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    args[2] = arg3;
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    args[3] = arg4;
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    tcg_gen_call(&tcg_ctx,
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                 tcg_const_ptr((tcg_target_long)func), TCG_HELPER_CALL_FLAGS,
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                 1, &ret, 4, args);
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}
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/* 32 bit ops */
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static inline void tcg_gen_ld8u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld8s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld8s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16u_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16u_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld16s_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld16s_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_ld_i32(TCGv ret, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_ld_i32, ret, arg2, offset);
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}
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static inline void tcg_gen_st8_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st8_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st16_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st16_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_st_i32(TCGv arg1, TCGv arg2, tcg_target_long offset)
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{
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    tcg_gen_op3i(INDEX_op_st_i32, arg1, arg2, offset);
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}
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static inline void tcg_gen_add_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_add_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_addi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_add_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_sub_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_sub_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_subi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_sub_i32(ret, arg1, tcg_const_i32(arg2));
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    }
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}
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static inline void tcg_gen_and_i32(TCGv ret, TCGv arg1, TCGv arg2)
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{
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    tcg_gen_op3(INDEX_op_and_i32, ret, arg1, arg2);
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}
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static inline void tcg_gen_andi_i32(TCGv ret, TCGv arg1, int32_t arg2)
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{
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    /* some cases can be optimized here */
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    if (arg2 == 0) {
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        tcg_gen_movi_i32(ret, 0);
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    } else if (arg2 == 0xffffffff) {
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        tcg_gen_mov_i32(ret, arg1);
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    } else {
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        tcg_gen_and_i32(ret, arg1, tcg_const_i32(arg2));
365 c896fe29 bellard
    }
366 c896fe29 bellard
}
367 c896fe29 bellard
368 ac56dd48 pbrook
static inline void tcg_gen_or_i32(TCGv ret, TCGv arg1, TCGv arg2)
369 c896fe29 bellard
{
370 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i32, ret, arg1, arg2);
371 c896fe29 bellard
}
372 c896fe29 bellard
373 ac56dd48 pbrook
static inline void tcg_gen_ori_i32(TCGv ret, TCGv arg1, int32_t arg2)
374 c896fe29 bellard
{
375 c896fe29 bellard
    /* some cases can be optimized here */
376 c896fe29 bellard
    if (arg2 == 0xffffffff) {
377 7089442c blueswir1
        tcg_gen_movi_i32(ret, 0xffffffff);
378 c896fe29 bellard
    } else if (arg2 == 0) {
379 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
380 c896fe29 bellard
    } else {
381 c896fe29 bellard
        tcg_gen_or_i32(ret, arg1, tcg_const_i32(arg2));
382 c896fe29 bellard
    }
383 c896fe29 bellard
}
384 c896fe29 bellard
385 ac56dd48 pbrook
static inline void tcg_gen_xor_i32(TCGv ret, TCGv arg1, TCGv arg2)
386 c896fe29 bellard
{
387 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i32, ret, arg1, arg2);
388 c896fe29 bellard
}
389 c896fe29 bellard
390 ac56dd48 pbrook
static inline void tcg_gen_xori_i32(TCGv ret, TCGv arg1, int32_t arg2)
391 c896fe29 bellard
{
392 c896fe29 bellard
    /* some cases can be optimized here */
393 c896fe29 bellard
    if (arg2 == 0) {
394 c896fe29 bellard
        tcg_gen_mov_i32(ret, arg1);
395 c896fe29 bellard
    } else {
396 c896fe29 bellard
        tcg_gen_xor_i32(ret, arg1, tcg_const_i32(arg2));
397 c896fe29 bellard
    }
398 c896fe29 bellard
}
399 c896fe29 bellard
400 ac56dd48 pbrook
static inline void tcg_gen_shl_i32(TCGv ret, TCGv arg1, TCGv arg2)
401 c896fe29 bellard
{
402 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i32, ret, arg1, arg2);
403 c896fe29 bellard
}
404 c896fe29 bellard
405 ac56dd48 pbrook
static inline void tcg_gen_shli_i32(TCGv ret, TCGv arg1, int32_t arg2)
406 c896fe29 bellard
{
407 c896fe29 bellard
    tcg_gen_shl_i32(ret, arg1, tcg_const_i32(arg2));
408 c896fe29 bellard
}
409 c896fe29 bellard
410 ac56dd48 pbrook
static inline void tcg_gen_shr_i32(TCGv ret, TCGv arg1, TCGv arg2)
411 c896fe29 bellard
{
412 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i32, ret, arg1, arg2);
413 c896fe29 bellard
}
414 c896fe29 bellard
415 ac56dd48 pbrook
static inline void tcg_gen_shri_i32(TCGv ret, TCGv arg1, int32_t arg2)
416 c896fe29 bellard
{
417 c896fe29 bellard
    tcg_gen_shr_i32(ret, arg1, tcg_const_i32(arg2));
418 c896fe29 bellard
}
419 c896fe29 bellard
420 ac56dd48 pbrook
static inline void tcg_gen_sar_i32(TCGv ret, TCGv arg1, TCGv arg2)
421 c896fe29 bellard
{
422 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i32, ret, arg1, arg2);
423 c896fe29 bellard
}
424 c896fe29 bellard
425 ac56dd48 pbrook
static inline void tcg_gen_sari_i32(TCGv ret, TCGv arg1, int32_t arg2)
426 c896fe29 bellard
{
427 c896fe29 bellard
    tcg_gen_sar_i32(ret, arg1, tcg_const_i32(arg2));
428 c896fe29 bellard
}
429 c896fe29 bellard
430 ac56dd48 pbrook
static inline void tcg_gen_brcond_i32(int cond, TCGv arg1, TCGv arg2, 
431 c896fe29 bellard
                                      int label_index)
432 c896fe29 bellard
{
433 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i32, arg1, arg2, cond, label_index);
434 c896fe29 bellard
}
435 c896fe29 bellard
436 ac56dd48 pbrook
static inline void tcg_gen_mul_i32(TCGv ret, TCGv arg1, TCGv arg2)
437 c896fe29 bellard
{
438 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i32, ret, arg1, arg2);
439 c896fe29 bellard
}
440 c896fe29 bellard
441 f730fd27 ths
static inline void tcg_gen_muli_i32(TCGv ret, TCGv arg1, int32_t arg2)
442 f730fd27 ths
{
443 f730fd27 ths
    tcg_gen_mul_i32(ret, arg1, tcg_const_i32(arg2));
444 f730fd27 ths
}
445 f730fd27 ths
446 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i32
447 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
448 c896fe29 bellard
{
449 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i32, ret, arg1, arg2);
450 c896fe29 bellard
}
451 c896fe29 bellard
452 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
453 c896fe29 bellard
{
454 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i32, ret, arg1, arg2);
455 c896fe29 bellard
}
456 c896fe29 bellard
457 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
458 c896fe29 bellard
{
459 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i32, ret, arg1, arg2);
460 c896fe29 bellard
}
461 c896fe29 bellard
462 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
463 c896fe29 bellard
{
464 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i32, ret, arg1, arg2);
465 c896fe29 bellard
}
466 c896fe29 bellard
#else
467 ac56dd48 pbrook
static inline void tcg_gen_div_i32(TCGv ret, TCGv arg1, TCGv arg2)
468 c896fe29 bellard
{
469 ac56dd48 pbrook
    TCGv t0;
470 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
471 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
472 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, ret, t0, arg1, t0, arg2);
473 c896fe29 bellard
}
474 c896fe29 bellard
475 ac56dd48 pbrook
static inline void tcg_gen_rem_i32(TCGv ret, TCGv arg1, TCGv arg2)
476 c896fe29 bellard
{
477 ac56dd48 pbrook
    TCGv t0;
478 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
479 c896fe29 bellard
    tcg_gen_sari_i32(t0, arg1, 31);
480 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i32, t0, ret, arg1, t0, arg2);
481 c896fe29 bellard
}
482 c896fe29 bellard
483 ac56dd48 pbrook
static inline void tcg_gen_divu_i32(TCGv ret, TCGv arg1, TCGv arg2)
484 c896fe29 bellard
{
485 ac56dd48 pbrook
    TCGv t0;
486 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
487 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
488 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, ret, t0, arg1, t0, arg2);
489 c896fe29 bellard
}
490 c896fe29 bellard
491 ac56dd48 pbrook
static inline void tcg_gen_remu_i32(TCGv ret, TCGv arg1, TCGv arg2)
492 c896fe29 bellard
{
493 ac56dd48 pbrook
    TCGv t0;
494 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
495 c896fe29 bellard
    tcg_gen_movi_i32(t0, 0);
496 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i32, t0, ret, arg1, t0, arg2);
497 c896fe29 bellard
}
498 c896fe29 bellard
#endif
499 c896fe29 bellard
500 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
501 c896fe29 bellard
502 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
503 c896fe29 bellard
{
504 98156423 pbrook
    if (GET_TCGV(ret) != GET_TCGV(arg)) {
505 4d07272d blueswir1
        tcg_gen_mov_i32(ret, arg);
506 4d07272d blueswir1
        tcg_gen_mov_i32(TCGV_HIGH(ret), TCGV_HIGH(arg));
507 4d07272d blueswir1
    }
508 c896fe29 bellard
}
509 c896fe29 bellard
510 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
511 c896fe29 bellard
{
512 c896fe29 bellard
    tcg_gen_movi_i32(ret, arg);
513 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), arg >> 32);
514 c896fe29 bellard
}
515 c896fe29 bellard
516 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
517 c896fe29 bellard
{
518 c896fe29 bellard
    tcg_gen_ld8u_i32(ret, arg2, offset);
519 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
520 c896fe29 bellard
}
521 c896fe29 bellard
522 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
523 c896fe29 bellard
{
524 c896fe29 bellard
    tcg_gen_ld8s_i32(ret, arg2, offset);
525 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
526 c896fe29 bellard
}
527 c896fe29 bellard
528 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
529 c896fe29 bellard
{
530 c896fe29 bellard
    tcg_gen_ld16u_i32(ret, arg2, offset);
531 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
532 c896fe29 bellard
}
533 c896fe29 bellard
534 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
535 c896fe29 bellard
{
536 c896fe29 bellard
    tcg_gen_ld16s_i32(ret, arg2, offset);
537 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
538 c896fe29 bellard
}
539 c896fe29 bellard
540 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
541 c896fe29 bellard
{
542 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
543 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
544 c896fe29 bellard
}
545 c896fe29 bellard
546 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
547 c896fe29 bellard
{
548 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
549 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
550 c896fe29 bellard
}
551 c896fe29 bellard
552 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
553 c896fe29 bellard
{
554 c896fe29 bellard
    /* since arg2 and ret have different types, they cannot be the
555 c896fe29 bellard
       same temporary */
556 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
557 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset);
558 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset + 4);
559 c896fe29 bellard
#else
560 c896fe29 bellard
    tcg_gen_ld_i32(ret, arg2, offset);
561 ac56dd48 pbrook
    tcg_gen_ld_i32(TCGV_HIGH(ret), arg2, offset + 4);
562 c896fe29 bellard
#endif
563 c896fe29 bellard
}
564 c896fe29 bellard
565 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
566 c896fe29 bellard
{
567 c896fe29 bellard
    tcg_gen_st8_i32(arg1, arg2, offset);
568 c896fe29 bellard
}
569 c896fe29 bellard
570 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
571 c896fe29 bellard
{
572 c896fe29 bellard
    tcg_gen_st16_i32(arg1, arg2, offset);
573 c896fe29 bellard
}
574 c896fe29 bellard
575 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
576 c896fe29 bellard
{
577 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
578 c896fe29 bellard
}
579 c896fe29 bellard
580 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
581 c896fe29 bellard
{
582 c896fe29 bellard
#ifdef TCG_TARGET_WORDS_BIGENDIAN
583 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset);
584 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset + 4);
585 c896fe29 bellard
#else
586 c896fe29 bellard
    tcg_gen_st_i32(arg1, arg2, offset);
587 ac56dd48 pbrook
    tcg_gen_st_i32(TCGV_HIGH(arg1), arg2, offset + 4);
588 c896fe29 bellard
#endif
589 c896fe29 bellard
}
590 c896fe29 bellard
591 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
592 c896fe29 bellard
{
593 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_add2_i32, ret, TCGV_HIGH(ret), 
594 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
595 c896fe29 bellard
}
596 c896fe29 bellard
597 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
598 c896fe29 bellard
{
599 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
600 c896fe29 bellard
}
601 c896fe29 bellard
602 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
603 c896fe29 bellard
{
604 ac56dd48 pbrook
    tcg_gen_op6(INDEX_op_sub2_i32, ret, TCGV_HIGH(ret), 
605 ac56dd48 pbrook
                arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2));
606 c896fe29 bellard
}
607 c896fe29 bellard
608 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
609 c896fe29 bellard
{
610 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
611 c896fe29 bellard
}
612 c896fe29 bellard
613 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
614 c896fe29 bellard
{
615 c896fe29 bellard
    tcg_gen_and_i32(ret, arg1, arg2);
616 ac56dd48 pbrook
    tcg_gen_and_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
617 c896fe29 bellard
}
618 c896fe29 bellard
619 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
620 c896fe29 bellard
{
621 c896fe29 bellard
    tcg_gen_andi_i32(ret, arg1, arg2);
622 ac56dd48 pbrook
    tcg_gen_andi_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
623 c896fe29 bellard
}
624 c896fe29 bellard
625 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
626 c896fe29 bellard
{
627 c896fe29 bellard
    tcg_gen_or_i32(ret, arg1, arg2);
628 ac56dd48 pbrook
    tcg_gen_or_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
629 c896fe29 bellard
}
630 c896fe29 bellard
631 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
632 c896fe29 bellard
{
633 c896fe29 bellard
    tcg_gen_ori_i32(ret, arg1, arg2);
634 ac56dd48 pbrook
    tcg_gen_ori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
635 c896fe29 bellard
}
636 c896fe29 bellard
637 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
638 c896fe29 bellard
{
639 c896fe29 bellard
    tcg_gen_xor_i32(ret, arg1, arg2);
640 ac56dd48 pbrook
    tcg_gen_xor_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), TCGV_HIGH(arg2));
641 c896fe29 bellard
}
642 c896fe29 bellard
643 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
644 c896fe29 bellard
{
645 c896fe29 bellard
    tcg_gen_xori_i32(ret, arg1, arg2);
646 ac56dd48 pbrook
    tcg_gen_xori_i32(TCGV_HIGH(ret), TCGV_HIGH(arg1), arg2 >> 32);
647 c896fe29 bellard
}
648 c896fe29 bellard
649 c896fe29 bellard
/* XXX: use generic code when basic block handling is OK or CPU
650 c896fe29 bellard
   specific code (x86) */
651 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
652 c896fe29 bellard
{
653 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shl_i64, ret, arg1, arg2);
654 c896fe29 bellard
}
655 c896fe29 bellard
656 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
657 c896fe29 bellard
{
658 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 0, 0);
659 c896fe29 bellard
}
660 c896fe29 bellard
661 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
662 c896fe29 bellard
{
663 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_shr_i64, ret, arg1, arg2);
664 c896fe29 bellard
}
665 c896fe29 bellard
666 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
667 c896fe29 bellard
{
668 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 0);
669 c896fe29 bellard
}
670 c896fe29 bellard
671 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
672 c896fe29 bellard
{
673 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_sar_i64, ret, arg1, arg2);
674 c896fe29 bellard
}
675 c896fe29 bellard
676 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
677 c896fe29 bellard
{
678 c896fe29 bellard
    tcg_gen_shifti_i64(ret, arg1, arg2, 1, 1);
679 c896fe29 bellard
}
680 c896fe29 bellard
681 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
682 c896fe29 bellard
                                      int label_index)
683 c896fe29 bellard
{
684 ac56dd48 pbrook
    tcg_gen_op6ii(INDEX_op_brcond2_i32, 
685 ac56dd48 pbrook
                  arg1, TCGV_HIGH(arg1), arg2, TCGV_HIGH(arg2),
686 ac56dd48 pbrook
                  cond, label_index);
687 c896fe29 bellard
}
688 c896fe29 bellard
689 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
690 c896fe29 bellard
{
691 ac56dd48 pbrook
    TCGv t0, t1;
692 c896fe29 bellard
    
693 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
694 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
695 c896fe29 bellard
696 ac56dd48 pbrook
    tcg_gen_op4(INDEX_op_mulu2_i32, t0, TCGV_HIGH(t0), arg1, arg2);
697 c896fe29 bellard
    
698 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, arg1, TCGV_HIGH(arg2));
699 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
700 ac56dd48 pbrook
    tcg_gen_mul_i32(t1, TCGV_HIGH(arg1), arg2);
701 ac56dd48 pbrook
    tcg_gen_add_i32(TCGV_HIGH(t0), TCGV_HIGH(t0), t1);
702 c896fe29 bellard
    
703 c896fe29 bellard
    tcg_gen_mov_i64(ret, t0);
704 c896fe29 bellard
}
705 c896fe29 bellard
706 f730fd27 ths
static inline void tcg_gen_muli_i64(TCGv ret, TCGv arg1, int64_t arg2)
707 f730fd27 ths
{
708 f730fd27 ths
    tcg_gen_mul_i64(ret, arg1, tcg_const_i64(arg2));
709 f730fd27 ths
}
710 f730fd27 ths
711 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
712 c896fe29 bellard
{
713 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_div_i64, ret, arg1, arg2);
714 c896fe29 bellard
}
715 c896fe29 bellard
716 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
717 c896fe29 bellard
{
718 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_rem_i64, ret, arg1, arg2);
719 c896fe29 bellard
}
720 c896fe29 bellard
721 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
722 c896fe29 bellard
{
723 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_divu_i64, ret, arg1, arg2);
724 c896fe29 bellard
}
725 c896fe29 bellard
726 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
727 c896fe29 bellard
{
728 c896fe29 bellard
    tcg_gen_helper_1_2(tcg_helper_remu_i64, ret, arg1, arg2);
729 c896fe29 bellard
}
730 c896fe29 bellard
731 c896fe29 bellard
#else
732 c896fe29 bellard
733 ac56dd48 pbrook
static inline void tcg_gen_mov_i64(TCGv ret, TCGv arg)
734 c896fe29 bellard
{
735 98156423 pbrook
    if (GET_TCGV(ret) != GET_TCGV(arg))
736 4d07272d blueswir1
        tcg_gen_op2(INDEX_op_mov_i64, ret, arg);
737 c896fe29 bellard
}
738 c896fe29 bellard
739 ac56dd48 pbrook
static inline void tcg_gen_movi_i64(TCGv ret, int64_t arg)
740 c896fe29 bellard
{
741 ac56dd48 pbrook
    tcg_gen_op2i(INDEX_op_movi_i64, ret, arg);
742 c896fe29 bellard
}
743 c896fe29 bellard
744 ac56dd48 pbrook
static inline void tcg_gen_ld8u_i64(TCGv ret, TCGv arg2,
745 ac56dd48 pbrook
                                    tcg_target_long offset)
746 c896fe29 bellard
{
747 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8u_i64, ret, arg2, offset);
748 c896fe29 bellard
}
749 c896fe29 bellard
750 ac56dd48 pbrook
static inline void tcg_gen_ld8s_i64(TCGv ret, TCGv arg2,
751 ac56dd48 pbrook
                                    tcg_target_long offset)
752 c896fe29 bellard
{
753 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld8s_i64, ret, arg2, offset);
754 c896fe29 bellard
}
755 c896fe29 bellard
756 ac56dd48 pbrook
static inline void tcg_gen_ld16u_i64(TCGv ret, TCGv arg2,
757 ac56dd48 pbrook
                                     tcg_target_long offset)
758 c896fe29 bellard
{
759 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16u_i64, ret, arg2, offset);
760 c896fe29 bellard
}
761 c896fe29 bellard
762 ac56dd48 pbrook
static inline void tcg_gen_ld16s_i64(TCGv ret, TCGv arg2,
763 ac56dd48 pbrook
                                     tcg_target_long offset)
764 c896fe29 bellard
{
765 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld16s_i64, ret, arg2, offset);
766 c896fe29 bellard
}
767 c896fe29 bellard
768 ac56dd48 pbrook
static inline void tcg_gen_ld32u_i64(TCGv ret, TCGv arg2,
769 ac56dd48 pbrook
                                     tcg_target_long offset)
770 c896fe29 bellard
{
771 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32u_i64, ret, arg2, offset);
772 c896fe29 bellard
}
773 c896fe29 bellard
774 ac56dd48 pbrook
static inline void tcg_gen_ld32s_i64(TCGv ret, TCGv arg2,
775 ac56dd48 pbrook
                                     tcg_target_long offset)
776 c896fe29 bellard
{
777 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld32s_i64, ret, arg2, offset);
778 c896fe29 bellard
}
779 c896fe29 bellard
780 ac56dd48 pbrook
static inline void tcg_gen_ld_i64(TCGv ret, TCGv arg2, tcg_target_long offset)
781 c896fe29 bellard
{
782 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_ld_i64, ret, arg2, offset);
783 c896fe29 bellard
}
784 c896fe29 bellard
785 ac56dd48 pbrook
static inline void tcg_gen_st8_i64(TCGv arg1, TCGv arg2,
786 ac56dd48 pbrook
                                   tcg_target_long offset)
787 c896fe29 bellard
{
788 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st8_i64, arg1, arg2, offset);
789 c896fe29 bellard
}
790 c896fe29 bellard
791 ac56dd48 pbrook
static inline void tcg_gen_st16_i64(TCGv arg1, TCGv arg2,
792 ac56dd48 pbrook
                                    tcg_target_long offset)
793 c896fe29 bellard
{
794 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st16_i64, arg1, arg2, offset);
795 c896fe29 bellard
}
796 c896fe29 bellard
797 ac56dd48 pbrook
static inline void tcg_gen_st32_i64(TCGv arg1, TCGv arg2,
798 ac56dd48 pbrook
                                    tcg_target_long offset)
799 c896fe29 bellard
{
800 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st32_i64, arg1, arg2, offset);
801 c896fe29 bellard
}
802 c896fe29 bellard
803 ac56dd48 pbrook
static inline void tcg_gen_st_i64(TCGv arg1, TCGv arg2, tcg_target_long offset)
804 c896fe29 bellard
{
805 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_st_i64, arg1, arg2, offset);
806 c896fe29 bellard
}
807 c896fe29 bellard
808 ac56dd48 pbrook
static inline void tcg_gen_add_i64(TCGv ret, TCGv arg1, TCGv arg2)
809 c896fe29 bellard
{
810 c896fe29 bellard
    tcg_gen_op3(INDEX_op_add_i64, ret, arg1, arg2);
811 c896fe29 bellard
}
812 c896fe29 bellard
813 ac56dd48 pbrook
static inline void tcg_gen_addi_i64(TCGv ret, TCGv arg1, int64_t arg2)
814 c896fe29 bellard
{
815 c896fe29 bellard
    tcg_gen_add_i64(ret, arg1, tcg_const_i64(arg2));
816 c896fe29 bellard
}
817 c896fe29 bellard
818 ac56dd48 pbrook
static inline void tcg_gen_sub_i64(TCGv ret, TCGv arg1, TCGv arg2)
819 c896fe29 bellard
{
820 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sub_i64, ret, arg1, arg2);
821 c896fe29 bellard
}
822 c896fe29 bellard
823 ac56dd48 pbrook
static inline void tcg_gen_subi_i64(TCGv ret, TCGv arg1, int64_t arg2)
824 c896fe29 bellard
{
825 c896fe29 bellard
    tcg_gen_sub_i64(ret, arg1, tcg_const_i64(arg2));
826 c896fe29 bellard
}
827 c896fe29 bellard
828 ac56dd48 pbrook
static inline void tcg_gen_and_i64(TCGv ret, TCGv arg1, TCGv arg2)
829 c896fe29 bellard
{
830 c896fe29 bellard
    tcg_gen_op3(INDEX_op_and_i64, ret, arg1, arg2);
831 c896fe29 bellard
}
832 c896fe29 bellard
833 ac56dd48 pbrook
static inline void tcg_gen_andi_i64(TCGv ret, TCGv arg1, int64_t arg2)
834 c896fe29 bellard
{
835 c896fe29 bellard
    tcg_gen_and_i64(ret, arg1, tcg_const_i64(arg2));
836 c896fe29 bellard
}
837 c896fe29 bellard
838 ac56dd48 pbrook
static inline void tcg_gen_or_i64(TCGv ret, TCGv arg1, TCGv arg2)
839 c896fe29 bellard
{
840 c896fe29 bellard
    tcg_gen_op3(INDEX_op_or_i64, ret, arg1, arg2);
841 c896fe29 bellard
}
842 c896fe29 bellard
843 ac56dd48 pbrook
static inline void tcg_gen_ori_i64(TCGv ret, TCGv arg1, int64_t arg2)
844 c896fe29 bellard
{
845 c896fe29 bellard
    tcg_gen_or_i64(ret, arg1, tcg_const_i64(arg2));
846 c896fe29 bellard
}
847 c896fe29 bellard
848 ac56dd48 pbrook
static inline void tcg_gen_xor_i64(TCGv ret, TCGv arg1, TCGv arg2)
849 c896fe29 bellard
{
850 c896fe29 bellard
    tcg_gen_op3(INDEX_op_xor_i64, ret, arg1, arg2);
851 c896fe29 bellard
}
852 c896fe29 bellard
853 ac56dd48 pbrook
static inline void tcg_gen_xori_i64(TCGv ret, TCGv arg1, int64_t arg2)
854 c896fe29 bellard
{
855 c896fe29 bellard
    tcg_gen_xor_i64(ret, arg1, tcg_const_i64(arg2));
856 c896fe29 bellard
}
857 c896fe29 bellard
858 ac56dd48 pbrook
static inline void tcg_gen_shl_i64(TCGv ret, TCGv arg1, TCGv arg2)
859 c896fe29 bellard
{
860 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shl_i64, ret, arg1, arg2);
861 c896fe29 bellard
}
862 c896fe29 bellard
863 ac56dd48 pbrook
static inline void tcg_gen_shli_i64(TCGv ret, TCGv arg1, int64_t arg2)
864 c896fe29 bellard
{
865 c896fe29 bellard
    tcg_gen_shl_i64(ret, arg1, tcg_const_i64(arg2));
866 c896fe29 bellard
}
867 c896fe29 bellard
868 ac56dd48 pbrook
static inline void tcg_gen_shr_i64(TCGv ret, TCGv arg1, TCGv arg2)
869 c896fe29 bellard
{
870 c896fe29 bellard
    tcg_gen_op3(INDEX_op_shr_i64, ret, arg1, arg2);
871 c896fe29 bellard
}
872 c896fe29 bellard
873 ac56dd48 pbrook
static inline void tcg_gen_shri_i64(TCGv ret, TCGv arg1, int64_t arg2)
874 c896fe29 bellard
{
875 c896fe29 bellard
    tcg_gen_shr_i64(ret, arg1, tcg_const_i64(arg2));
876 c896fe29 bellard
}
877 c896fe29 bellard
878 ac56dd48 pbrook
static inline void tcg_gen_sar_i64(TCGv ret, TCGv arg1, TCGv arg2)
879 c896fe29 bellard
{
880 c896fe29 bellard
    tcg_gen_op3(INDEX_op_sar_i64, ret, arg1, arg2);
881 c896fe29 bellard
}
882 c896fe29 bellard
883 ac56dd48 pbrook
static inline void tcg_gen_sari_i64(TCGv ret, TCGv arg1, int64_t arg2)
884 c896fe29 bellard
{
885 c896fe29 bellard
    tcg_gen_sar_i64(ret, arg1, tcg_const_i64(arg2));
886 c896fe29 bellard
}
887 c896fe29 bellard
888 ac56dd48 pbrook
static inline void tcg_gen_brcond_i64(int cond, TCGv arg1, TCGv arg2, 
889 c896fe29 bellard
                                      int label_index)
890 c896fe29 bellard
{
891 ac56dd48 pbrook
    tcg_gen_op4ii(INDEX_op_brcond_i64, arg1, arg2, cond, label_index);
892 c896fe29 bellard
}
893 c896fe29 bellard
894 ac56dd48 pbrook
static inline void tcg_gen_mul_i64(TCGv ret, TCGv arg1, TCGv arg2)
895 c896fe29 bellard
{
896 c896fe29 bellard
    tcg_gen_op3(INDEX_op_mul_i64, ret, arg1, arg2);
897 c896fe29 bellard
}
898 c896fe29 bellard
899 f730fd27 ths
static inline void tcg_gen_muli_i64(TCGv ret, TCGv arg1, int64_t arg2)
900 f730fd27 ths
{
901 f730fd27 ths
    tcg_gen_mul_i64(ret, arg1, tcg_const_i64(arg2));
902 f730fd27 ths
}
903 f730fd27 ths
904 c896fe29 bellard
#ifdef TCG_TARGET_HAS_div_i64
905 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
906 c896fe29 bellard
{
907 c896fe29 bellard
    tcg_gen_op3(INDEX_op_div_i64, ret, arg1, arg2);
908 c896fe29 bellard
}
909 c896fe29 bellard
910 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
911 c896fe29 bellard
{
912 c896fe29 bellard
    tcg_gen_op3(INDEX_op_rem_i64, ret, arg1, arg2);
913 c896fe29 bellard
}
914 c896fe29 bellard
915 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
916 c896fe29 bellard
{
917 c896fe29 bellard
    tcg_gen_op3(INDEX_op_divu_i64, ret, arg1, arg2);
918 c896fe29 bellard
}
919 c896fe29 bellard
920 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
921 c896fe29 bellard
{
922 c896fe29 bellard
    tcg_gen_op3(INDEX_op_remu_i64, ret, arg1, arg2);
923 c896fe29 bellard
}
924 c896fe29 bellard
#else
925 ac56dd48 pbrook
static inline void tcg_gen_div_i64(TCGv ret, TCGv arg1, TCGv arg2)
926 c896fe29 bellard
{
927 ac56dd48 pbrook
    TCGv t0;
928 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
929 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
930 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, ret, t0, arg1, t0, arg2);
931 c896fe29 bellard
}
932 c896fe29 bellard
933 ac56dd48 pbrook
static inline void tcg_gen_rem_i64(TCGv ret, TCGv arg1, TCGv arg2)
934 c896fe29 bellard
{
935 ac56dd48 pbrook
    TCGv t0;
936 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
937 c896fe29 bellard
    tcg_gen_sari_i64(t0, arg1, 63);
938 c896fe29 bellard
    tcg_gen_op5(INDEX_op_div2_i64, t0, ret, arg1, t0, arg2);
939 c896fe29 bellard
}
940 c896fe29 bellard
941 ac56dd48 pbrook
static inline void tcg_gen_divu_i64(TCGv ret, TCGv arg1, TCGv arg2)
942 c896fe29 bellard
{
943 ac56dd48 pbrook
    TCGv t0;
944 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
945 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
946 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, ret, t0, arg1, t0, arg2);
947 c896fe29 bellard
}
948 c896fe29 bellard
949 ac56dd48 pbrook
static inline void tcg_gen_remu_i64(TCGv ret, TCGv arg1, TCGv arg2)
950 c896fe29 bellard
{
951 ac56dd48 pbrook
    TCGv t0;
952 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I64);
953 c896fe29 bellard
    tcg_gen_movi_i64(t0, 0);
954 c896fe29 bellard
    tcg_gen_op5(INDEX_op_divu2_i64, t0, ret, arg1, t0, arg2);
955 c896fe29 bellard
}
956 c896fe29 bellard
#endif
957 c896fe29 bellard
958 c896fe29 bellard
#endif
959 c896fe29 bellard
960 c896fe29 bellard
/***************************************/
961 c896fe29 bellard
/* optional operations */
962 c896fe29 bellard
963 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i32(TCGv ret, TCGv arg)
964 c896fe29 bellard
{
965 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i32
966 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i32, ret, arg);
967 c896fe29 bellard
#else
968 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 24);
969 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 24);
970 c896fe29 bellard
#endif
971 c896fe29 bellard
}
972 c896fe29 bellard
973 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i32(TCGv ret, TCGv arg)
974 c896fe29 bellard
{
975 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i32
976 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i32, ret, arg);
977 c896fe29 bellard
#else
978 c896fe29 bellard
    tcg_gen_shli_i32(ret, arg, 16);
979 5ff9d6a4 bellard
    tcg_gen_sari_i32(ret, ret, 16);
980 c896fe29 bellard
#endif
981 c896fe29 bellard
}
982 c896fe29 bellard
983 86831435 pbrook
/* These are currently just for convenience.
984 86831435 pbrook
   We assume a target will recognise these automatically .  */
985 86831435 pbrook
static inline void tcg_gen_ext8u_i32(TCGv ret, TCGv arg)
986 86831435 pbrook
{
987 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffu);
988 86831435 pbrook
}
989 86831435 pbrook
990 86831435 pbrook
static inline void tcg_gen_ext16u_i32(TCGv ret, TCGv arg)
991 86831435 pbrook
{
992 86831435 pbrook
    tcg_gen_andi_i32(ret, arg, 0xffffu);
993 86831435 pbrook
}
994 86831435 pbrook
995 c896fe29 bellard
/* Note: we assume the two high bytes are set to zero */
996 ac56dd48 pbrook
static inline void tcg_gen_bswap16_i32(TCGv ret, TCGv arg)
997 c896fe29 bellard
{
998 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap16_i32
999 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap16_i32, ret, arg);
1000 c896fe29 bellard
#else
1001 ac56dd48 pbrook
    TCGv t0, t1;
1002 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1003 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1004 c896fe29 bellard
    
1005 c896fe29 bellard
    tcg_gen_shri_i32(t0, arg, 8);
1006 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x000000ff);
1007 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1008 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1009 c896fe29 bellard
#endif
1010 c896fe29 bellard
}
1011 c896fe29 bellard
1012 ac56dd48 pbrook
static inline void tcg_gen_bswap_i32(TCGv ret, TCGv arg)
1013 c896fe29 bellard
{
1014 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i32
1015 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i32, ret, arg);
1016 c896fe29 bellard
#else
1017 ac56dd48 pbrook
    TCGv t0, t1;
1018 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1019 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1020 c896fe29 bellard
    
1021 c896fe29 bellard
    tcg_gen_shli_i32(t0, arg, 24);
1022 c896fe29 bellard
    
1023 c896fe29 bellard
    tcg_gen_andi_i32(t1, arg, 0x0000ff00);
1024 c896fe29 bellard
    tcg_gen_shli_i32(t1, t1, 8);
1025 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1026 c896fe29 bellard
    
1027 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 8);
1028 c896fe29 bellard
    tcg_gen_andi_i32(t1, t1, 0x0000ff00);
1029 c896fe29 bellard
    tcg_gen_or_i32(t0, t0, t1);
1030 c896fe29 bellard
    
1031 c896fe29 bellard
    tcg_gen_shri_i32(t1, arg, 24);
1032 c896fe29 bellard
    tcg_gen_or_i32(ret, t0, t1);
1033 c896fe29 bellard
#endif
1034 c896fe29 bellard
}
1035 c896fe29 bellard
1036 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1037 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
1038 c896fe29 bellard
{
1039 c896fe29 bellard
    tcg_gen_ext8s_i32(ret, arg);
1040 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1041 c896fe29 bellard
}
1042 c896fe29 bellard
1043 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
1044 c896fe29 bellard
{
1045 c896fe29 bellard
    tcg_gen_ext16s_i32(ret, arg);
1046 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1047 c896fe29 bellard
}
1048 c896fe29 bellard
1049 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
1050 c896fe29 bellard
{
1051 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1052 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1053 c896fe29 bellard
}
1054 c896fe29 bellard
1055 86831435 pbrook
static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg)
1056 86831435 pbrook
{
1057 86831435 pbrook
    tcg_gen_ext8u_i32(ret, arg);
1058 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1059 86831435 pbrook
}
1060 86831435 pbrook
1061 86831435 pbrook
static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg)
1062 86831435 pbrook
{
1063 86831435 pbrook
    tcg_gen_ext16u_i32(ret, arg);
1064 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1065 86831435 pbrook
}
1066 86831435 pbrook
1067 86831435 pbrook
static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg)
1068 86831435 pbrook
{
1069 86831435 pbrook
    tcg_gen_mov_i32(ret, arg);
1070 86831435 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1071 86831435 pbrook
}
1072 86831435 pbrook
1073 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1074 c896fe29 bellard
{
1075 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1076 c896fe29 bellard
}
1077 c896fe29 bellard
1078 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1079 c896fe29 bellard
{
1080 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1081 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1082 c896fe29 bellard
}
1083 c896fe29 bellard
1084 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1085 c896fe29 bellard
{
1086 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1087 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1088 c896fe29 bellard
}
1089 c896fe29 bellard
1090 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1091 c896fe29 bellard
{
1092 ac56dd48 pbrook
    TCGv t0, t1;
1093 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1094 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1095 c896fe29 bellard
1096 c896fe29 bellard
    tcg_gen_bswap_i32(t0, arg);
1097 ac56dd48 pbrook
    tcg_gen_bswap_i32(t1, TCGV_HIGH(arg));
1098 c896fe29 bellard
    tcg_gen_mov_i32(ret, t1);
1099 ac56dd48 pbrook
    tcg_gen_mov_i32(TCGV_HIGH(ret), t0);
1100 c896fe29 bellard
}
1101 c896fe29 bellard
#else
1102 c896fe29 bellard
1103 ac56dd48 pbrook
static inline void tcg_gen_ext8s_i64(TCGv ret, TCGv arg)
1104 c896fe29 bellard
{
1105 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext8s_i64
1106 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext8s_i64, ret, arg);
1107 c896fe29 bellard
#else
1108 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 56);
1109 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 56);
1110 c896fe29 bellard
#endif
1111 c896fe29 bellard
}
1112 c896fe29 bellard
1113 ac56dd48 pbrook
static inline void tcg_gen_ext16s_i64(TCGv ret, TCGv arg)
1114 c896fe29 bellard
{
1115 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext16s_i64
1116 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext16s_i64, ret, arg);
1117 c896fe29 bellard
#else
1118 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 48);
1119 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 48);
1120 c896fe29 bellard
#endif
1121 c896fe29 bellard
}
1122 c896fe29 bellard
1123 ac56dd48 pbrook
static inline void tcg_gen_ext32s_i64(TCGv ret, TCGv arg)
1124 c896fe29 bellard
{
1125 c896fe29 bellard
#ifdef TCG_TARGET_HAS_ext32s_i64
1126 c896fe29 bellard
    tcg_gen_op2(INDEX_op_ext32s_i64, ret, arg);
1127 c896fe29 bellard
#else
1128 c896fe29 bellard
    tcg_gen_shli_i64(ret, arg, 32);
1129 5ff9d6a4 bellard
    tcg_gen_sari_i64(ret, ret, 32);
1130 c896fe29 bellard
#endif
1131 c896fe29 bellard
}
1132 c896fe29 bellard
1133 86831435 pbrook
static inline void tcg_gen_ext8u_i64(TCGv ret, TCGv arg)
1134 86831435 pbrook
{
1135 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffu);
1136 86831435 pbrook
}
1137 86831435 pbrook
1138 86831435 pbrook
static inline void tcg_gen_ext16u_i64(TCGv ret, TCGv arg)
1139 86831435 pbrook
{
1140 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffu);
1141 86831435 pbrook
}
1142 86831435 pbrook
1143 86831435 pbrook
static inline void tcg_gen_ext32u_i64(TCGv ret, TCGv arg)
1144 86831435 pbrook
{
1145 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1146 86831435 pbrook
}
1147 86831435 pbrook
1148 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1149 ac56dd48 pbrook
   registers.  This will probably break MIPS64 targets.  */
1150 ac56dd48 pbrook
static inline void tcg_gen_trunc_i64_i32(TCGv ret, TCGv arg)
1151 c896fe29 bellard
{
1152 c896fe29 bellard
    tcg_gen_mov_i32(ret, arg);
1153 c896fe29 bellard
}
1154 c896fe29 bellard
1155 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1156 c896fe29 bellard
   registers */
1157 ac56dd48 pbrook
static inline void tcg_gen_extu_i32_i64(TCGv ret, TCGv arg)
1158 c896fe29 bellard
{
1159 86831435 pbrook
    tcg_gen_andi_i64(ret, arg, 0xffffffffu);
1160 c896fe29 bellard
}
1161 c896fe29 bellard
1162 c896fe29 bellard
/* Note: we assume the target supports move between 32 and 64 bit
1163 c896fe29 bellard
   registers */
1164 ac56dd48 pbrook
static inline void tcg_gen_ext_i32_i64(TCGv ret, TCGv arg)
1165 c896fe29 bellard
{
1166 c896fe29 bellard
    tcg_gen_ext32s_i64(ret, arg);
1167 c896fe29 bellard
}
1168 c896fe29 bellard
1169 ac56dd48 pbrook
static inline void tcg_gen_bswap_i64(TCGv ret, TCGv arg)
1170 c896fe29 bellard
{
1171 c896fe29 bellard
#ifdef TCG_TARGET_HAS_bswap_i64
1172 c896fe29 bellard
    tcg_gen_op2(INDEX_op_bswap_i64, ret, arg);
1173 c896fe29 bellard
#else
1174 ac56dd48 pbrook
    TCGv t0, t1;
1175 c896fe29 bellard
    t0 = tcg_temp_new(TCG_TYPE_I32);
1176 c896fe29 bellard
    t1 = tcg_temp_new(TCG_TYPE_I32);
1177 c896fe29 bellard
    
1178 c896fe29 bellard
    tcg_gen_shli_i64(t0, arg, 56);
1179 c896fe29 bellard
    
1180 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x0000ff00);
1181 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 40);
1182 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1183 c896fe29 bellard
    
1184 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0x00ff0000);
1185 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 24);
1186 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1187 c896fe29 bellard
1188 c896fe29 bellard
    tcg_gen_andi_i64(t1, arg, 0xff000000);
1189 c896fe29 bellard
    tcg_gen_shli_i64(t1, t1, 8);
1190 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1191 c896fe29 bellard
1192 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 8);
1193 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0xff000000);
1194 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1195 c896fe29 bellard
    
1196 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 24);
1197 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x00ff0000);
1198 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1199 c896fe29 bellard
1200 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 40);
1201 c896fe29 bellard
    tcg_gen_andi_i64(t1, t1, 0x0000ff00);
1202 c896fe29 bellard
    tcg_gen_or_i64(t0, t0, t1);
1203 c896fe29 bellard
1204 c896fe29 bellard
    tcg_gen_shri_i64(t1, arg, 56);
1205 c896fe29 bellard
    tcg_gen_or_i64(ret, t0, t1);
1206 c896fe29 bellard
#endif
1207 c896fe29 bellard
}
1208 c896fe29 bellard
1209 c896fe29 bellard
#endif
1210 c896fe29 bellard
1211 390efc54 pbrook
static inline void tcg_gen_neg_i32(TCGv ret, TCGv arg)
1212 390efc54 pbrook
{
1213 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i32
1214 390efc54 pbrook
    tcg_gen_op2(INDEX_op_neg_i32, ret, arg);
1215 390efc54 pbrook
#else
1216 390efc54 pbrook
    tcg_gen_sub_i32(ret, tcg_const_i32(0), arg);
1217 390efc54 pbrook
#endif
1218 390efc54 pbrook
}
1219 390efc54 pbrook
1220 390efc54 pbrook
static inline void tcg_gen_neg_i64(TCGv ret, TCGv arg)
1221 390efc54 pbrook
{
1222 390efc54 pbrook
#ifdef TCG_TARGET_HAS_neg_i64
1223 390efc54 pbrook
    tcg_gen_op2(INDEX_op_neg_i64, ret, arg);
1224 390efc54 pbrook
#else
1225 390efc54 pbrook
    tcg_gen_sub_i64(ret, tcg_const_i64(0), arg);
1226 390efc54 pbrook
#endif
1227 390efc54 pbrook
}
1228 390efc54 pbrook
1229 5ff9d6a4 bellard
1230 5ff9d6a4 bellard
static inline void tcg_gen_discard_i32(TCGv arg)
1231 5ff9d6a4 bellard
{
1232 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1233 5ff9d6a4 bellard
}
1234 5ff9d6a4 bellard
1235 5ff9d6a4 bellard
#if TCG_TARGET_REG_BITS == 32
1236 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1237 5ff9d6a4 bellard
{
1238 5ff9d6a4 bellard
    tcg_gen_discard_i32(arg);
1239 5ff9d6a4 bellard
    tcg_gen_discard_i32(TCGV_HIGH(arg));
1240 5ff9d6a4 bellard
}
1241 5ff9d6a4 bellard
#else
1242 5ff9d6a4 bellard
static inline void tcg_gen_discard_i64(TCGv arg)
1243 5ff9d6a4 bellard
{
1244 5ff9d6a4 bellard
    tcg_gen_op1(INDEX_op_discard, arg);
1245 5ff9d6a4 bellard
}
1246 5ff9d6a4 bellard
#endif
1247 5ff9d6a4 bellard
1248 c896fe29 bellard
/***************************************/
1249 ac56dd48 pbrook
static inline void tcg_gen_macro_2(TCGv ret0, TCGv ret1, int macro_id)
1250 c896fe29 bellard
{
1251 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_macro_2, ret0, ret1, macro_id);
1252 c896fe29 bellard
}
1253 c896fe29 bellard
1254 c896fe29 bellard
/***************************************/
1255 c896fe29 bellard
/* QEMU specific operations. Their type depend on the QEMU CPU
1256 c896fe29 bellard
   type. */
1257 c896fe29 bellard
#ifndef TARGET_LONG_BITS
1258 c896fe29 bellard
#error must include QEMU headers
1259 c896fe29 bellard
#endif
1260 c896fe29 bellard
1261 c896fe29 bellard
static inline void tcg_gen_exit_tb(tcg_target_long val)
1262 c896fe29 bellard
{
1263 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_exit_tb, val);
1264 c896fe29 bellard
}
1265 c896fe29 bellard
1266 c896fe29 bellard
static inline void tcg_gen_goto_tb(int idx)
1267 c896fe29 bellard
{
1268 ac56dd48 pbrook
    tcg_gen_op1i(INDEX_op_goto_tb, idx);
1269 c896fe29 bellard
}
1270 c896fe29 bellard
1271 c896fe29 bellard
#if TCG_TARGET_REG_BITS == 32
1272 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1273 c896fe29 bellard
{
1274 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1275 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1276 c896fe29 bellard
#else
1277 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8u, ret, addr, TCGV_HIGH(addr), mem_index);
1278 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1279 c896fe29 bellard
#endif
1280 c896fe29 bellard
}
1281 c896fe29 bellard
1282 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1283 c896fe29 bellard
{
1284 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1285 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1286 c896fe29 bellard
#else
1287 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld8s, ret, addr, TCGV_HIGH(addr), mem_index);
1288 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1289 c896fe29 bellard
#endif
1290 c896fe29 bellard
}
1291 c896fe29 bellard
1292 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1293 c896fe29 bellard
{
1294 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1295 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1296 c896fe29 bellard
#else
1297 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16u, ret, addr, TCGV_HIGH(addr), mem_index);
1298 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1299 c896fe29 bellard
#endif
1300 c896fe29 bellard
}
1301 c896fe29 bellard
1302 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1303 c896fe29 bellard
{
1304 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1305 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1306 c896fe29 bellard
#else
1307 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld16s, ret, addr, TCGV_HIGH(addr), mem_index);
1308 21fc3cfc pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1309 c896fe29 bellard
#endif
1310 c896fe29 bellard
}
1311 c896fe29 bellard
1312 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1313 c896fe29 bellard
{
1314 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1315 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1316 c896fe29 bellard
#else
1317 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1318 ac56dd48 pbrook
    tcg_gen_movi_i32(TCGV_HIGH(ret), 0);
1319 c896fe29 bellard
#endif
1320 c896fe29 bellard
}
1321 c896fe29 bellard
1322 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1323 c896fe29 bellard
{
1324 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1325 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1326 c896fe29 bellard
#else
1327 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld32u, ret, addr, TCGV_HIGH(addr), mem_index);
1328 ac56dd48 pbrook
    tcg_gen_sari_i32(TCGV_HIGH(ret), ret, 31);
1329 c896fe29 bellard
#endif
1330 c896fe29 bellard
}
1331 c896fe29 bellard
1332 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1333 c896fe29 bellard
{
1334 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1335 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret), addr, mem_index);
1336 c896fe29 bellard
#else
1337 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_ld64, ret, TCGV_HIGH(ret),
1338 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1339 c896fe29 bellard
#endif
1340 c896fe29 bellard
}
1341 c896fe29 bellard
1342 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1343 c896fe29 bellard
{
1344 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1345 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1346 c896fe29 bellard
#else
1347 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st8, arg, addr, TCGV_HIGH(addr), mem_index);
1348 c896fe29 bellard
#endif
1349 c896fe29 bellard
}
1350 c896fe29 bellard
1351 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1352 c896fe29 bellard
{
1353 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1354 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1355 c896fe29 bellard
#else
1356 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st16, arg, addr, TCGV_HIGH(addr), mem_index);
1357 c896fe29 bellard
#endif
1358 c896fe29 bellard
}
1359 c896fe29 bellard
1360 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1361 c896fe29 bellard
{
1362 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1363 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1364 c896fe29 bellard
#else
1365 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st32, arg, addr, TCGV_HIGH(addr), mem_index);
1366 c896fe29 bellard
#endif
1367 c896fe29 bellard
}
1368 c896fe29 bellard
1369 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1370 c896fe29 bellard
{
1371 c896fe29 bellard
#if TARGET_LONG_BITS == 32
1372 ac56dd48 pbrook
    tcg_gen_op4i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg), addr, mem_index);
1373 c896fe29 bellard
#else
1374 ac56dd48 pbrook
    tcg_gen_op5i(INDEX_op_qemu_st64, arg, TCGV_HIGH(arg),
1375 ac56dd48 pbrook
                 addr, TCGV_HIGH(addr), mem_index);
1376 c896fe29 bellard
#endif
1377 c896fe29 bellard
}
1378 c896fe29 bellard
1379 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i32
1380 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i32
1381 f8422f52 blueswir1
1382 c896fe29 bellard
#else /* TCG_TARGET_REG_BITS == 32 */
1383 c896fe29 bellard
1384 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8u(TCGv ret, TCGv addr, int mem_index)
1385 c896fe29 bellard
{
1386 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8u, ret, addr, mem_index);
1387 c896fe29 bellard
}
1388 c896fe29 bellard
1389 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld8s(TCGv ret, TCGv addr, int mem_index)
1390 c896fe29 bellard
{
1391 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld8s, ret, addr, mem_index);
1392 c896fe29 bellard
}
1393 c896fe29 bellard
1394 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16u(TCGv ret, TCGv addr, int mem_index)
1395 c896fe29 bellard
{
1396 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16u, ret, addr, mem_index);
1397 c896fe29 bellard
}
1398 c896fe29 bellard
1399 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld16s(TCGv ret, TCGv addr, int mem_index)
1400 c896fe29 bellard
{
1401 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld16s, ret, addr, mem_index);
1402 c896fe29 bellard
}
1403 c896fe29 bellard
1404 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32u(TCGv ret, TCGv addr, int mem_index)
1405 c896fe29 bellard
{
1406 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32u, ret, addr, mem_index);
1407 c896fe29 bellard
}
1408 c896fe29 bellard
1409 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld32s(TCGv ret, TCGv addr, int mem_index)
1410 c896fe29 bellard
{
1411 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld32s, ret, addr, mem_index);
1412 c896fe29 bellard
}
1413 c896fe29 bellard
1414 ac56dd48 pbrook
static inline void tcg_gen_qemu_ld64(TCGv ret, TCGv addr, int mem_index)
1415 c896fe29 bellard
{
1416 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_ld64, ret, addr, mem_index);
1417 c896fe29 bellard
}
1418 c896fe29 bellard
1419 ac56dd48 pbrook
static inline void tcg_gen_qemu_st8(TCGv arg, TCGv addr, int mem_index)
1420 c896fe29 bellard
{
1421 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st8, arg, addr, mem_index);
1422 c896fe29 bellard
}
1423 c896fe29 bellard
1424 ac56dd48 pbrook
static inline void tcg_gen_qemu_st16(TCGv arg, TCGv addr, int mem_index)
1425 c896fe29 bellard
{
1426 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st16, arg, addr, mem_index);
1427 c896fe29 bellard
}
1428 c896fe29 bellard
1429 ac56dd48 pbrook
static inline void tcg_gen_qemu_st32(TCGv arg, TCGv addr, int mem_index)
1430 c896fe29 bellard
{
1431 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st32, arg, addr, mem_index);
1432 c896fe29 bellard
}
1433 c896fe29 bellard
1434 ac56dd48 pbrook
static inline void tcg_gen_qemu_st64(TCGv arg, TCGv addr, int mem_index)
1435 c896fe29 bellard
{
1436 ac56dd48 pbrook
    tcg_gen_op3i(INDEX_op_qemu_st64, arg, addr, mem_index);
1437 c896fe29 bellard
}
1438 c896fe29 bellard
1439 56b8f567 blueswir1
#define tcg_gen_ld_ptr tcg_gen_ld_i64
1440 a768e4b2 blueswir1
#define tcg_gen_discard_ptr tcg_gen_discard_i64
1441 f8422f52 blueswir1
1442 c896fe29 bellard
#endif /* TCG_TARGET_REG_BITS != 32 */
1443 f8422f52 blueswir1
1444 f8422f52 blueswir1
#if TARGET_LONG_BITS == 64
1445 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I64
1446 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i64
1447 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i64
1448 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i64
1449 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i64
1450 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i64
1451 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i64
1452 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld32u_i64
1453 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld32s_i64
1454 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i64
1455 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i64
1456 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i64
1457 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st32_i64
1458 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i64
1459 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i64
1460 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i64
1461 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i64
1462 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i64
1463 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i64
1464 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i64
1465 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i64
1466 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i64
1467 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i64
1468 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i64
1469 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i64
1470 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i64
1471 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i64
1472 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i64
1473 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i64
1474 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i64
1475 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i64
1476 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i64
1477 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i64
1478 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i64
1479 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i64
1480 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_trunc_i64_i32
1481 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_mov_i64
1482 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_extu_i32_i64
1483 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_ext_i32_i64
1484 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_mov_i64
1485 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_mov_i64
1486 a98824ac blueswir1
#define tcg_const_tl tcg_const_i64
1487 f8422f52 blueswir1
#else
1488 f8422f52 blueswir1
#define TCG_TYPE_TL TCG_TYPE_I32
1489 f8422f52 blueswir1
#define tcg_gen_movi_tl tcg_gen_movi_i32
1490 f8422f52 blueswir1
#define tcg_gen_mov_tl tcg_gen_mov_i32
1491 f8422f52 blueswir1
#define tcg_gen_ld8u_tl tcg_gen_ld8u_i32
1492 f8422f52 blueswir1
#define tcg_gen_ld8s_tl tcg_gen_ld8s_i32
1493 f8422f52 blueswir1
#define tcg_gen_ld16u_tl tcg_gen_ld16u_i32
1494 f8422f52 blueswir1
#define tcg_gen_ld16s_tl tcg_gen_ld16s_i32
1495 f8422f52 blueswir1
#define tcg_gen_ld32u_tl tcg_gen_ld_i32
1496 f8422f52 blueswir1
#define tcg_gen_ld32s_tl tcg_gen_ld_i32
1497 f8422f52 blueswir1
#define tcg_gen_ld_tl tcg_gen_ld_i32
1498 f8422f52 blueswir1
#define tcg_gen_st8_tl tcg_gen_st8_i32
1499 f8422f52 blueswir1
#define tcg_gen_st16_tl tcg_gen_st16_i32
1500 f8422f52 blueswir1
#define tcg_gen_st32_tl tcg_gen_st_i32
1501 f8422f52 blueswir1
#define tcg_gen_st_tl tcg_gen_st_i32
1502 f8422f52 blueswir1
#define tcg_gen_add_tl tcg_gen_add_i32
1503 f8422f52 blueswir1
#define tcg_gen_addi_tl tcg_gen_addi_i32
1504 f8422f52 blueswir1
#define tcg_gen_sub_tl tcg_gen_sub_i32
1505 390efc54 pbrook
#define tcg_gen_neg_tl tcg_gen_neg_i32
1506 f8422f52 blueswir1
#define tcg_gen_subi_tl tcg_gen_subi_i32
1507 f8422f52 blueswir1
#define tcg_gen_and_tl tcg_gen_and_i32
1508 f8422f52 blueswir1
#define tcg_gen_andi_tl tcg_gen_andi_i32
1509 f8422f52 blueswir1
#define tcg_gen_or_tl tcg_gen_or_i32
1510 f8422f52 blueswir1
#define tcg_gen_ori_tl tcg_gen_ori_i32
1511 f8422f52 blueswir1
#define tcg_gen_xor_tl tcg_gen_xor_i32
1512 f8422f52 blueswir1
#define tcg_gen_xori_tl tcg_gen_xori_i32
1513 f8422f52 blueswir1
#define tcg_gen_shl_tl tcg_gen_shl_i32
1514 f8422f52 blueswir1
#define tcg_gen_shli_tl tcg_gen_shli_i32
1515 f8422f52 blueswir1
#define tcg_gen_shr_tl tcg_gen_shr_i32
1516 f8422f52 blueswir1
#define tcg_gen_shri_tl tcg_gen_shri_i32
1517 f8422f52 blueswir1
#define tcg_gen_sar_tl tcg_gen_sar_i32
1518 f8422f52 blueswir1
#define tcg_gen_sari_tl tcg_gen_sari_i32
1519 0cf767d6 blueswir1
#define tcg_gen_brcond_tl tcg_gen_brcond_i32
1520 f730fd27 ths
#define tcg_gen_mul_tl tcg_gen_mul_i32
1521 f730fd27 ths
#define tcg_gen_muli_tl tcg_gen_muli_i32
1522 a768e4b2 blueswir1
#define tcg_gen_discard_tl tcg_gen_discard_i32
1523 e429073d blueswir1
#define tcg_gen_trunc_tl_i32 tcg_gen_mov_i32
1524 e429073d blueswir1
#define tcg_gen_trunc_i64_tl tcg_gen_trunc_i64_i32
1525 e429073d blueswir1
#define tcg_gen_extu_i32_tl tcg_gen_mov_i32
1526 e429073d blueswir1
#define tcg_gen_ext_i32_tl tcg_gen_mov_i32
1527 e429073d blueswir1
#define tcg_gen_extu_tl_i64 tcg_gen_extu_i32_i64
1528 e429073d blueswir1
#define tcg_gen_ext_tl_i64 tcg_gen_ext_i32_i64
1529 a98824ac blueswir1
#define tcg_const_tl tcg_const_i32
1530 f8422f52 blueswir1
#endif
1531 6ddbc6e4 pbrook
1532 6ddbc6e4 pbrook
#if TCG_TARGET_REG_BITS == 32
1533 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i32
1534 6ddbc6e4 pbrook
#else /* TCG_TARGET_REG_BITS == 32 */
1535 6ddbc6e4 pbrook
#define tcg_gen_addi_ptr tcg_gen_addi_i64
1536 6ddbc6e4 pbrook
#endif /* TCG_TARGET_REG_BITS != 32 */