root / tcg / tcg-opc.h @ 390efc54
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1 | c896fe29 | bellard | /*
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2 | c896fe29 | bellard | * Tiny Code Generator for QEMU
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3 | c896fe29 | bellard | *
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4 | c896fe29 | bellard | * Copyright (c) 2008 Fabrice Bellard
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5 | c896fe29 | bellard | *
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6 | c896fe29 | bellard | * Permission is hereby granted, free of charge, to any person obtaining a copy
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7 | c896fe29 | bellard | * of this software and associated documentation files (the "Software"), to deal
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8 | c896fe29 | bellard | * in the Software without restriction, including without limitation the rights
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9 | c896fe29 | bellard | * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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10 | c896fe29 | bellard | * copies of the Software, and to permit persons to whom the Software is
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11 | c896fe29 | bellard | * furnished to do so, subject to the following conditions:
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12 | c896fe29 | bellard | *
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13 | c896fe29 | bellard | * The above copyright notice and this permission notice shall be included in
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14 | c896fe29 | bellard | * all copies or substantial portions of the Software.
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15 | c896fe29 | bellard | *
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16 | c896fe29 | bellard | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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17 | c896fe29 | bellard | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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18 | c896fe29 | bellard | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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19 | c896fe29 | bellard | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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20 | c896fe29 | bellard | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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21 | c896fe29 | bellard | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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22 | c896fe29 | bellard | * THE SOFTWARE.
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23 | c896fe29 | bellard | */
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24 | bf6247fb | blueswir1 | #ifdef CONFIG_DYNGEN_OP
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25 | c896fe29 | bellard | #include "dyngen-opc.h" |
26 | cf2be984 | blueswir1 | #endif
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27 | c896fe29 | bellard | |
28 | c896fe29 | bellard | #ifndef DEF2
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29 | c896fe29 | bellard | #define DEF2(name, oargs, iargs, cargs, flags) DEF(name, oargs + iargs + cargs, 0) |
30 | c896fe29 | bellard | #endif
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31 | c896fe29 | bellard | |
32 | c896fe29 | bellard | /* predefined ops */
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33 | c896fe29 | bellard | DEF2(end, 0, 0, 0, 0) /* must be kept first */ |
34 | c896fe29 | bellard | DEF2(nop, 0, 0, 0, 0) |
35 | c896fe29 | bellard | DEF2(nop1, 0, 0, 1, 0) |
36 | c896fe29 | bellard | DEF2(nop2, 0, 0, 2, 0) |
37 | c896fe29 | bellard | DEF2(nop3, 0, 0, 3, 0) |
38 | c896fe29 | bellard | DEF2(nopn, 0, 0, 1, 0) /* variable number of parameters */ |
39 | c896fe29 | bellard | /* macro handling */
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40 | c896fe29 | bellard | DEF2(macro_2, 2, 0, 1, 0) |
41 | c896fe29 | bellard | DEF2(macro_start, 0, 0, 2, 0) |
42 | c896fe29 | bellard | DEF2(macro_end, 0, 0, 2, 0) |
43 | c896fe29 | bellard | DEF2(macro_goto, 0, 0, 3, 0) |
44 | c896fe29 | bellard | |
45 | 5ff9d6a4 | bellard | DEF2(discard, 1, 0, 0, 0) |
46 | 5ff9d6a4 | bellard | |
47 | c896fe29 | bellard | DEF2(set_label, 0, 0, 1, 0) |
48 | 5ff9d6a4 | bellard | DEF2(call, 0, 1, 2, TCG_OPF_SIDE_EFFECTS) /* variable number of parameters */ |
49 | 5ff9d6a4 | bellard | DEF2(jmp, 0, 1, 0, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
50 | 5ff9d6a4 | bellard | DEF2(br, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
51 | c896fe29 | bellard | |
52 | c896fe29 | bellard | DEF2(mov_i32, 1, 1, 0, 0) |
53 | c896fe29 | bellard | DEF2(movi_i32, 1, 0, 1, 0) |
54 | c896fe29 | bellard | /* load/store */
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55 | c896fe29 | bellard | DEF2(ld8u_i32, 1, 1, 1, 0) |
56 | c896fe29 | bellard | DEF2(ld8s_i32, 1, 1, 1, 0) |
57 | c896fe29 | bellard | DEF2(ld16u_i32, 1, 1, 1, 0) |
58 | c896fe29 | bellard | DEF2(ld16s_i32, 1, 1, 1, 0) |
59 | c896fe29 | bellard | DEF2(ld_i32, 1, 1, 1, 0) |
60 | 5ff9d6a4 | bellard | DEF2(st8_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
61 | 5ff9d6a4 | bellard | DEF2(st16_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
62 | 5ff9d6a4 | bellard | DEF2(st_i32, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
63 | c896fe29 | bellard | /* arith */
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64 | c896fe29 | bellard | DEF2(add_i32, 1, 2, 0, 0) |
65 | c896fe29 | bellard | DEF2(sub_i32, 1, 2, 0, 0) |
66 | c896fe29 | bellard | DEF2(mul_i32, 1, 2, 0, 0) |
67 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i32
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68 | c896fe29 | bellard | DEF2(div_i32, 1, 2, 0, 0) |
69 | c896fe29 | bellard | DEF2(divu_i32, 1, 2, 0, 0) |
70 | c896fe29 | bellard | DEF2(rem_i32, 1, 2, 0, 0) |
71 | c896fe29 | bellard | DEF2(remu_i32, 1, 2, 0, 0) |
72 | c896fe29 | bellard | #else
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73 | c896fe29 | bellard | DEF2(div2_i32, 2, 3, 0, 0) |
74 | c896fe29 | bellard | DEF2(divu2_i32, 2, 3, 0, 0) |
75 | c896fe29 | bellard | #endif
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76 | c896fe29 | bellard | DEF2(and_i32, 1, 2, 0, 0) |
77 | c896fe29 | bellard | DEF2(or_i32, 1, 2, 0, 0) |
78 | c896fe29 | bellard | DEF2(xor_i32, 1, 2, 0, 0) |
79 | c896fe29 | bellard | /* shifts */
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80 | c896fe29 | bellard | DEF2(shl_i32, 1, 2, 0, 0) |
81 | c896fe29 | bellard | DEF2(shr_i32, 1, 2, 0, 0) |
82 | c896fe29 | bellard | DEF2(sar_i32, 1, 2, 0, 0) |
83 | c896fe29 | bellard | |
84 | 5ff9d6a4 | bellard | DEF2(brcond_i32, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
85 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
86 | c896fe29 | bellard | DEF2(add2_i32, 2, 4, 0, 0) |
87 | c896fe29 | bellard | DEF2(sub2_i32, 2, 4, 0, 0) |
88 | 5ff9d6a4 | bellard | DEF2(brcond2_i32, 0, 4, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
89 | c896fe29 | bellard | DEF2(mulu2_i32, 2, 2, 0, 0) |
90 | c896fe29 | bellard | #endif
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91 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i32
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92 | c896fe29 | bellard | DEF2(ext8s_i32, 1, 1, 0, 0) |
93 | c896fe29 | bellard | #endif
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94 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i32
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95 | c896fe29 | bellard | DEF2(ext16s_i32, 1, 1, 0, 0) |
96 | c896fe29 | bellard | #endif
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97 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i32
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98 | c896fe29 | bellard | DEF2(bswap_i32, 1, 1, 0, 0) |
99 | c896fe29 | bellard | #endif
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100 | c896fe29 | bellard | |
101 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 64 |
102 | c896fe29 | bellard | DEF2(mov_i64, 1, 1, 0, 0) |
103 | c896fe29 | bellard | DEF2(movi_i64, 1, 0, 1, 0) |
104 | c896fe29 | bellard | /* load/store */
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105 | c896fe29 | bellard | DEF2(ld8u_i64, 1, 1, 1, 0) |
106 | c896fe29 | bellard | DEF2(ld8s_i64, 1, 1, 1, 0) |
107 | c896fe29 | bellard | DEF2(ld16u_i64, 1, 1, 1, 0) |
108 | c896fe29 | bellard | DEF2(ld16s_i64, 1, 1, 1, 0) |
109 | c896fe29 | bellard | DEF2(ld32u_i64, 1, 1, 1, 0) |
110 | c896fe29 | bellard | DEF2(ld32s_i64, 1, 1, 1, 0) |
111 | c896fe29 | bellard | DEF2(ld_i64, 1, 1, 1, 0) |
112 | 5ff9d6a4 | bellard | DEF2(st8_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
113 | 5ff9d6a4 | bellard | DEF2(st16_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
114 | 5ff9d6a4 | bellard | DEF2(st32_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
115 | 5ff9d6a4 | bellard | DEF2(st_i64, 0, 2, 1, TCG_OPF_SIDE_EFFECTS) |
116 | c896fe29 | bellard | /* arith */
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117 | c896fe29 | bellard | DEF2(add_i64, 1, 2, 0, 0) |
118 | c896fe29 | bellard | DEF2(sub_i64, 1, 2, 0, 0) |
119 | c896fe29 | bellard | DEF2(mul_i64, 1, 2, 0, 0) |
120 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_div_i64
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121 | c896fe29 | bellard | DEF2(div_i64, 1, 2, 0, 0) |
122 | c896fe29 | bellard | DEF2(divu_i64, 1, 2, 0, 0) |
123 | c896fe29 | bellard | DEF2(rem_i64, 1, 2, 0, 0) |
124 | c896fe29 | bellard | DEF2(remu_i64, 1, 2, 0, 0) |
125 | c896fe29 | bellard | #else
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126 | c896fe29 | bellard | DEF2(div2_i64, 2, 3, 0, 0) |
127 | c896fe29 | bellard | DEF2(divu2_i64, 2, 3, 0, 0) |
128 | c896fe29 | bellard | #endif
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129 | c896fe29 | bellard | DEF2(and_i64, 1, 2, 0, 0) |
130 | c896fe29 | bellard | DEF2(or_i64, 1, 2, 0, 0) |
131 | c896fe29 | bellard | DEF2(xor_i64, 1, 2, 0, 0) |
132 | c896fe29 | bellard | /* shifts */
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133 | c896fe29 | bellard | DEF2(shl_i64, 1, 2, 0, 0) |
134 | c896fe29 | bellard | DEF2(shr_i64, 1, 2, 0, 0) |
135 | c896fe29 | bellard | DEF2(sar_i64, 1, 2, 0, 0) |
136 | c896fe29 | bellard | |
137 | 5ff9d6a4 | bellard | DEF2(brcond_i64, 0, 2, 2, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
138 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext8s_i64
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139 | c896fe29 | bellard | DEF2(ext8s_i64, 1, 1, 0, 0) |
140 | c896fe29 | bellard | #endif
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141 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext16s_i64
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142 | c896fe29 | bellard | DEF2(ext16s_i64, 1, 1, 0, 0) |
143 | c896fe29 | bellard | #endif
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144 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_ext32s_i64
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145 | c896fe29 | bellard | DEF2(ext32s_i64, 1, 1, 0, 0) |
146 | c896fe29 | bellard | #endif
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147 | c896fe29 | bellard | #ifdef TCG_TARGET_HAS_bswap_i64
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148 | c896fe29 | bellard | DEF2(bswap_i64, 1, 1, 0, 0) |
149 | c896fe29 | bellard | #endif
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150 | c896fe29 | bellard | #endif
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151 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i32
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152 | 390efc54 | pbrook | DEF2(neg_i32, 1, 1, 0, 0) |
153 | 390efc54 | pbrook | #endif
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154 | 390efc54 | pbrook | #ifdef TCG_TARGET_HAS_neg_i64
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155 | 390efc54 | pbrook | DEF2(neg_i64, 1, 1, 0, 0) |
156 | 390efc54 | pbrook | #endif
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157 | c896fe29 | bellard | |
158 | c896fe29 | bellard | /* QEMU specific */
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159 | 5ff9d6a4 | bellard | DEF2(exit_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
160 | 5ff9d6a4 | bellard | DEF2(goto_tb, 0, 0, 1, TCG_OPF_BB_END | TCG_OPF_SIDE_EFFECTS) |
161 | c896fe29 | bellard | /* Note: even if TARGET_LONG_BITS is not defined, the INDEX_op
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162 | c896fe29 | bellard | constants must be defined */
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163 | c896fe29 | bellard | #if TCG_TARGET_REG_BITS == 32 |
164 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
165 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
166 | c896fe29 | bellard | #else
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167 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
168 | c896fe29 | bellard | #endif
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169 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
170 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
171 | c896fe29 | bellard | #else
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172 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
173 | c896fe29 | bellard | #endif
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174 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
175 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
176 | c896fe29 | bellard | #else
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177 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
178 | c896fe29 | bellard | #endif
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179 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
180 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
181 | c896fe29 | bellard | #else
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182 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
183 | c896fe29 | bellard | #endif
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184 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
185 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
186 | c896fe29 | bellard | #else
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187 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
188 | c896fe29 | bellard | #endif
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189 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
190 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
191 | c896fe29 | bellard | #else
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192 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
193 | c896fe29 | bellard | #endif
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194 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
195 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
196 | c896fe29 | bellard | #else
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197 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 2, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
198 | c896fe29 | bellard | #endif
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199 | c896fe29 | bellard | |
200 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
201 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
202 | c896fe29 | bellard | #else
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203 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
204 | c896fe29 | bellard | #endif
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205 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
206 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
207 | c896fe29 | bellard | #else
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208 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
209 | c896fe29 | bellard | #endif
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210 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
211 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
212 | c896fe29 | bellard | #else
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213 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
214 | c896fe29 | bellard | #endif
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215 | c896fe29 | bellard | #if TARGET_LONG_BITS == 32 |
216 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 3, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
217 | c896fe29 | bellard | #else
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218 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 4, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
219 | c896fe29 | bellard | #endif
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220 | c896fe29 | bellard | |
221 | c896fe29 | bellard | #else /* TCG_TARGET_REG_BITS == 32 */ |
222 | c896fe29 | bellard | |
223 | 5ff9d6a4 | bellard | DEF2(qemu_ld8u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
224 | 5ff9d6a4 | bellard | DEF2(qemu_ld8s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
225 | 5ff9d6a4 | bellard | DEF2(qemu_ld16u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
226 | 5ff9d6a4 | bellard | DEF2(qemu_ld16s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
227 | 5ff9d6a4 | bellard | DEF2(qemu_ld32u, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
228 | 5ff9d6a4 | bellard | DEF2(qemu_ld32s, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
229 | 5ff9d6a4 | bellard | DEF2(qemu_ld64, 1, 1, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
230 | c896fe29 | bellard | |
231 | 5ff9d6a4 | bellard | DEF2(qemu_st8, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
232 | 5ff9d6a4 | bellard | DEF2(qemu_st16, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
233 | 5ff9d6a4 | bellard | DEF2(qemu_st32, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
234 | 5ff9d6a4 | bellard | DEF2(qemu_st64, 0, 2, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) |
235 | c896fe29 | bellard | |
236 | c896fe29 | bellard | #endif /* TCG_TARGET_REG_BITS != 32 */ |
237 | c896fe29 | bellard | |
238 | c896fe29 | bellard | #undef DEF2 |