tcg-ia64: Provide default GUEST_BASE.
Fix compilation error when GUEST_BASE is not defined.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Edgar E. Iglesias <edgar@axis.com>
tcg-ia64: Implement qemu_ld32.
The port was not properly merged following86feb1c860dc38e9c89e787c5210e8191800385e
tcg-ia64: Fix tlb read error for 32-bit targets.
Use ld4 not ld8 for reading the tlb of 32-bit targets.
tcg-ia64: Fix address compilation in qemu_st.
A typo in the usermode address calculation path; R3 used where R2 needed.
tcg-ia64: Fix warning in qemu_ld.
The usermode version of qemu_ld doesn't used mem_index,leading to set-but-not-used warnings.
tcg: Fix default definition of divu_i32 and remu_i32.
The arguments to tcg_gen_helper32 for these functions were notupdated correctly in rev 2bece2c88331f024a46527634e3dd91c71d22141.
tcg: Use fprintf_function (format checking)
fprintf_function uses format checking with GCC_FMT_ATTR.
Cc: Blue Swirl <blauwirbel@gmail.com>Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg: Fix compiler error (comparison of unsigned expression)
When qemu is configured with --enable-debug-tcg,gcc throws this warning (or error with -Werror):
tcg/tcg.c:1030: error: comparison of unsigned expression >= 0 is always true
Fix it by removing the >= 0 part....
TCG: Revert ppc64 tcg_out_movi32 change
3b6dac34161bc0a342336072643c2f6d17e0ec45 apparently broke the ppc64 TCG targetcompilation in the code path without guest base.
Reverting this line fixes the build.
Signed-off-by: Andreas F?rber <andreas.faerber@web.de>...
TCG: Fix Darwin/ppc calling convention recognition
5da79c86a3744e3a901c7986c109dd06951befd2 broke compilation on Mac OS X v10.5 ppc.Apple's GCC 4.0.1 does not define _CALL_DARWIN. Recognize APPLE again as well.
tcg-s390: new TCG Target
Original patch from Ulrich Hecht, further work from Alexander Grafand Richard Henderson.
Cc: Ulrich Hecht <uli@suse.de>Cc: Alexander Graf <agraf@suse.de>Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-ppc: Conditionally reserve TCG_GUEST_BASE_REG.
We need not reserve the register unless we're going to use it.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: malc <av1474@comtv.ru>
tcg: Optionally sign-extend 32-bit arguments for 64-bit hosts.
Some hosts (amd64, ia64) have an ABI that ignores the high bitsof the 64-bit register when passing 32-bit arguments. Othersrequire the value to be properly sign-extended for the type.I.e. "int32_t" must be sign-extended and "uint32_t" must be...
tcg: fix DEF macro after commit c61aaf7a388c4ad95d8b546fdb9267dc01183317
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-s390: Icache flush is a no-op.
Before gcc 4.2, builtin_clear_cache doesn't exist, andafterward the gcc s390 backend implements it as nothing.
Signed-off-by: Richard Henderson <rth@twiddle.net>Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
tcg-i386: fix andi r, r, 0xff
tcg-i386: remove use of _Bool that slipped code review
tcg-i386: Merge 64-bit generation.
tcg: get rid of copy_size in TCGOpDef
copy_size is a left-over from the dyngen era, remove it.
tcg: get rid of DEF2 in tcg-opc.h
Now that tcg-opc.h is only used in TCG code, get rid of DEF2 intcg-opc.h.
tcg: Make some tcg-target.c routines static.
Both tcg_target_init and tcg_target_qemu_prologueare unused outside of tcg.c.
tcg: Add TYPE parameter to tcg_out_mov.
Mirror tcg_out_movi in having a TYPE parameter. This allows x86_64to perform the move at the proper width, which may elide a REX prefix.
Introduce a TCG_TYPE_REG enumerator to represent the "native width" of the host register, and to distinguish the usage from "pointer data"...
tcg-i386: fix a typo
Fix a typo introduced by c28b14c694d759f39fe3ae4f8d03b567da5b93f8.
tcg-i386: declare tcg_out_tlb_load() inline
Declare tcg_out_tlb_load() inline so that we don't loose optimisationswith commit 8516a04467cb7954cdc32e8b79b4b7df56dccb16.
tcg-i386: Remove some ifdefs in qemu_ld/st.
Tidy some code by replacing ifdefs by C ifs.
tcg-i386: Tidy data16 prefixes.
Include it in the opcode as an extension, as with P_EXTor the REX bits in the x86-64 port.
tcg-i386: Split out TLB Hit path from qemu_ld/st.
Splitting out these functions will allow further cleanups.
tcg-i386: Swap order of TLB hit and miss paths.
Make fallthru be TLB hit and branch be TLB miss. Doing thisboth improves branch prediction and will allow further cleanup.
tcg-i386: Split out tlb load function.
Share some code between qemu_ld and qemu_st.
tcg: Use INDEX_op_qemu_ld32 for 32-bit results.
tcg: Initialize the prologue after GUEST_BASE is fixed.
This will allow backends to make intelligent choices about howto implement GUEST_BASE.
tcg-hppa: Load GUEST_BASE as an immediate.
Now that the prologue is generated after GUEST_BASE is fixed,we can load it as an immediate, and also avoid reserving theregister if it isn't necessary.
tcg-ia64: Fix some register usage issues.
(1) The output registers were not marked call-clobbered, even though they can be modified by called functions.(2) The thread pointer was not marked reserved.(3) R4-R6 are call-saved, but not saved by the prologue. Rather than...
tcg-ia64: Load GUEST_BASE into a register.
Saves one bundle per memory operation.
tcg-i386: Use lea for three-operand add.
The result is shorter than the mov+add that TCG wouldotherwise generate for us.
tcg-i386: Nuke trailing whitespace.
tcg-i386: Tidy ext8u and ext16u operations.
Define OPC_MOVZBL and OPC_MOVZWL. Factor opcode emission toseparate functions.
tcg-i386: Tidy ext8s and ext16s operations.
Define OPC_MOVSBL and OPC_MOVSWL. Factor opcode emission toseparate functions.
tcg-i386: Tidy immediate arithmetic operations.
Define OPC_ARITH_EvI[bz]; use throughout. Use tcg_out_ext8udirectly in setcond. Use tgen_arithi in qemu_ld/st.
tcg-i386: Tidy non-immediate arithmetic operations.
Add more OPC values, and tgen_arithr. Use the later throughout.
Note that normal reg/reg arithmetic now uses the Gv,Ev opcode forminstead of the Ev,Gv opcode form used previously. Both formsdisassemble properly, and so there's no visible change when diffing...
tcg-i386: Tidy movi.
Define and use OPC_MOVL_Iv.
tcg-i386: Tidy push/pop.
Move tcg_out_push/pop up in the file so that they can be usedby qemu_ld/st. Define a tcg_out_pushi to be used as well.
tcg-i386: Tidy calls.
Define OPC_CALL_Jz, generated by tcg_out_calli; use the laterthroughout. Unify the calls within qemu_st; adjust the stackwith a single pop if applicable.
Define and use EXT_CALLN_Ev for indirect calls.
Signed-off-by: Richard Henderson <rth@twiddle.net>...
tcg-i386: Tidy ret.
Define and use OPC_RET.
tcg-i386: Tidy setcc.
Define and use OPC_SETCC.
tcg-i386: Tidy unary arithmetic.
Define OPC_GRP3 and EXT3_FOO to match. Use them instead ofbare constants.
Define OPC_GRP5 and rename the existing EXT_BAR to EXT5_BAR tomake it clear which extension should be used with which opcode.
tcg-i386: Tidy multiply.
Define and use OPC_IMUL_GvEv{,Ib,Iz}.
tcg-i386: Tidy xchg.
Define and use OPC_XCHG_ax_r32.
tcg-i386: Tidy lea.
Implement full modrm+sib addressing mode processing.Use that in qemu_ld/st to output the LEA.
tcg-i386: Tidy jumps.
Define OPC_JCC*, OC_JMP*, and EXT_JMPN_Ev. Use them throughout.
tcg-i386: Eliminate extra move from qemu_ld64.
If the address register overlaps one of the output registerssimply issue the clobbering load last, rather than emittingan extra move of the address register.
tcg-i386: Tidy move operations.
Define OPC_MOVB* and OPC_MOVL*; use them throughout.Use tcg_out_ld/st instead of bare tcg_out_modrm_offsetwhen it makes sense.
tcg-i386: Tidy shift operations.
Define OPC_SHIFT_{1,Ib,cl}. Factor opcode emission to a function.
tcg-i386: Tidy bswap operations.
Define OPC_BSWAP. Factor opcode emission to separate functions.
tcg-i386: Allocate call-saved registers first.
tcg-i386: Tidy initialization of tcg_target_call_clobber_regs.
Setting the registers one by one is easier to read, and getsoptimized by the compiler just the same.
tcg: Add missing 'static' attribute
tcg_out_reloc is only used locally (in */target.c which isincluded in tcg.c).
Signed-off-by: Stefan Weil <weil@mail.berlios.de>Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg-hppa: Remove automatically implemented opcodes.
Remove neg, ext8u, ext16u, as requested.
tcg-hppa: Constrain immediate inputs to and_i32, or_i32, andc_i32.
Define "M" constraint for and_mask_p and "O" constraint for or_mask_p.Assume that inputs are correct in tcg_out_ori and tcg_out_andi.
tcg-hppa: Fix GUEST_BASE initialization in prologue.
Load from the guest_base variable rather than embed a constant.Always reserve TCG_GUEST_BASE_REG if guest base support enabled.
tcg-hppa: Fix softmmu loads and stores.
Along the tlb hit path, we were modifying the variables holding the inputregister numbers, which lead to incorrect expansion of the tlb miss path.Fix this by extracting the tlb hit path to separate functions with their...
tcg-hppa: Schedule the address masking after the TLB load.
Issue the tlb load as early as possible and perform the addressmasking while the load is completing.
tcg-hppa: Fix branch offset during retranslation.
Branch offsets should only be overwritten during relocation,to support partial retranslation.
Remove dead assignments in various common files, spotted by clang analyzer
Value stored is never read.
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
tcg/arm: fix condition in zero/sign extension functions
tcg/arm: remove conditional argument for qemu_ld/st
While it make sense to pass a conditional argument to tcg_out_*()functions as the ARM architecture allows that, it doesn't make sensefor qemu_ld/st functions. These functions use comparison instructions...
tcg/arm: use ext* ops in qemu_ld
tcg/arm: bswap arguments in qemu_ld/st if needed
On big endian targets, data arguments of qemu_ld/st ops have to bebyte swapped. Two temporary registers are needed for qemu_st to dothe bswap. r0 and r1 are used in system mode, do the same in usermode, which implies reworking the constraints....
tcg/arm: remove useless register tests in qemu_ld/st
addr_reg, data_reg and data_reg2 can't be register r0 or r1 du to theconstraints. Don't check if they equals these registers.
tcg/arm: fix argument alignment in qemu_st64
64-bit arguments should be aligned on an even register as specifiedby the "Procedure Call Standard for the ARM Architecture".
tcg/arm: optimize register allocation order
The beginning of the register allocation order list on the TCG armtarget matches the list of clobbered registers. This means that when anhelper is called, there is almost always clobbered registers that haveto be spilled....
tcg/arm: don't try to load constants using pc
There is statistically almost 0 chances to use this code, soremove it.
tcg/arm: sxtb and sxth are available starting with ARMv6
tcg/arm: use the blx instruction when possible
tcg/arm: add rotation ops
tcg/arm: add ext16u op
Add an ext16u op, either using the uxth instruction on ARMv6+ or twoshifts on previous ARM versions. In both cases the result use the samenumber or less instructions than the pure TCG version.
Also move all sign extension code to separate functions, so that they...
tcg/arm: add bswap ops
Add an bswap16 and bswap32 ops, either using the rev and rev16instructions on ARMv6+ or shifts and logical operations on previousARM versions. In both cases the result use less instructions thanthe pure TCG version.
These ops are also needed by the qemu_ld/st functions....
tcg/arm: remove SAVE_LR code
There is no need to save the LR register (r14) before a call to asubroutine. According to the "Procedure Call Standard for the ARMArchitecture", it is the job of the callee to save this register.Moreover, this register is already saved in the prologue/epilogue....
tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that areclobbered or reserved one by one. This makes the code easier to read.
Also declare all the 16 registers to TCG, and mark pc as reserved....
tcg/arm: remove store signed functions
Store signed functions doesn't make sense, and are not used. Removethem.
tcg/arm: replace integer values by registers enum
The TCG ARM backends uses integer values to refer to both immediatevalues and register number. This makes the code difficult to read.
The patch below replaces all (if I haven't miss any ;-) integer values...
tcg/arm: align 64-bit arguments in function calls
As specified by the "Procedure Call Standard for the ARM Architecture".
tcg/arm: add variables to define the allowed instructions set
Use a set of variables to define the allowed ARM instructions, dependingon the ARM_ARCH_* GCC defines.
tcg/ppc: Remove redundant comparison from brcond2
Signed-off-by: malc <av1474@comtv.ru>
Fix --enable-profiler compilation.
There's a header file inclusion ordering problem between cpu-all.hand qemu-timer.h, such that cpu_get_real_ticks is not defined whenwe attempt to use it in profile_getclock.
tcg: Add missing static qualifier
Build breaks otherwise when USE_LIVENESS_ANALYSIS is not defined.
tcg/ppc: Fix signed versions of brcond2
Thanks to: Alexander Graff, Thomas Gleixner and Andreas Faerber.
tcp/mips: Change TCG_AREG0 (fp -> s0)
Register fp (frame pointer) is a bad choice for compilationswithout optimisation, because the compiler makes heavy useof this register (so the resulting code crashes).
Register s0 had been used for TCG_AREG1 in earlier releases,...
tcg/README: improve description of bswap*
tcg-hppa: Don't try to calls to non-constant addresses.
PA-RISC uses procedure descriptors. We'd need to emit a call tothe millicode routine $$dyncall. However, this situation doesn'tactually arise, since we always have the descriptor available atTCG code generation time....
tcg-hppa: Fix in/out register overlap in add2/sub2.
Handle the output log part overlapping the input high parts.Also, improve sub2 to handle some constants the second input low part.
tcg/ia64: fix tlb addend read
tcg-hppa: Finish the port.
Delete inline functions from tcg-target.h that don't need to be there,move the others to tcg-target.c. Add 'Z', 'I', 'J' constraints for0, signed 11-bit, and signed 5-bit respectively. Add GUEST_BASE supportsimilar to ppc64, with the value stored in a register. Add missing...
tcg/ppc64: Fix typo
tcg/ppc: Fix typo
tcg/ppc: Implment bswap16/32
tcg/mips: fix 64-bit linux-user on big endian MIPS
tcg/mips: use seb/seh instructions on MIPS32R2
tcg/ppc: Implement eqv, nand and nor
Split TLB addend and target_phys_addr_t
Historically the qemu tlb "addend" field was used for both RAM and IO accesses,so needed to be able to hold both host addresses (unsigned long) and guestphysical addresses (target_phys_addr_t). However since the introduction of...