Revision 3953d786 target-mips/translate.c
| b/target-mips/translate.c | ||
|---|---|---|
| 5292 | 5292 |
env->CP0_Wired = 0; |
| 5293 | 5293 |
/* SMP not implemented */ |
| 5294 | 5294 |
env->CP0_EBase = 0x80000000; |
| 5295 |
env->CP0_Config2 = MIPS_CONFIG2; |
|
| 5296 |
env->CP0_Config3 = MIPS_CONFIG3; |
|
| 5297 | 5295 |
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); |
| 5298 | 5296 |
env->CP0_WatchLo = 0; |
| 5299 | 5297 |
env->hflags = MIPS_HFLAG_ERL; |
| ... | ... | |
| 5305 | 5303 |
env->hflags |= MIPS_HFLAG_UM; |
| 5306 | 5304 |
env->user_mode_only = 1; |
| 5307 | 5305 |
#endif |
| 5308 |
env->fcr0 = MIPS_FCR0; |
|
| 5309 | 5306 |
/* XXX some guesswork here, values are CPU specific */ |
| 5310 | 5307 |
env->SYNCI_Step = 16; |
| 5311 | 5308 |
env->CCRes = 2; |
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