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1
/*
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 * Tiny Code Generator for QEMU
3
 *
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 * Copyright (c) 2008 Andrzej Zaborowski
5
 *
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 * Permission is hereby granted, free of charge, to any person obtaining a copy
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 * of this software and associated documentation files (the "Software"), to deal
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 * in the Software without restriction, including without limitation the rights
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 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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 * copies of the Software, and to permit persons to whom the Software is
11
 * furnished to do so, subject to the following conditions:
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 *
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 * The above copyright notice and this permission notice shall be included in
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 * all copies or substantial portions of the Software.
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 *
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 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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 * THE SOFTWARE.
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 */
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const char *tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
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    "%r0",
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    "%r1",
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    "%r2",
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    "%r3",
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    "%r4",
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    "%r5",
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    "%r6",
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    "%r7",
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    "%r8",
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    "%r9",
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    "%r10",
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    "%r11",
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    "%r12",
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    "%r13",
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    "%r14",
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};
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42
int tcg_target_reg_alloc_order[] = {
43
    TCG_REG_R0,
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    TCG_REG_R1,
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    TCG_REG_R2,
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    TCG_REG_R3,
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    TCG_REG_R4,
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    TCG_REG_R5,
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    TCG_REG_R6,
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    TCG_REG_R7,
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    TCG_REG_R8,
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    TCG_REG_R9,
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    TCG_REG_R10,
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    TCG_REG_R11,
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    TCG_REG_R12,
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    TCG_REG_R13,
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    TCG_REG_R14,
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};
59

    
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const int tcg_target_call_iarg_regs[4] = {
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    TCG_REG_R0, TCG_REG_R1, TCG_REG_R2, TCG_REG_R3
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};
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const int tcg_target_call_oarg_regs[2] = {
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    TCG_REG_R0, TCG_REG_R1
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};
66

    
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static void patch_reloc(uint8_t *code_ptr, int type,
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                tcg_target_long value, tcg_target_long addend)
69
{
70
    switch (type) {
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    case R_ARM_ABS32:
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        *(uint32_t *) code_ptr = value;
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        break;
74

    
75
    case R_ARM_CALL:
76
    case R_ARM_JUMP24:
77
    default:
78
        tcg_abort();
79

    
80
    case R_ARM_PC24:
81
        *(uint32_t *) code_ptr |= (*(uint32_t *) code_ptr & 0xff000000) |
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                (((value - ((tcg_target_long) code_ptr + 8)) >> 2) & 0xffffff);
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        break;
84
    }
85
}
86

    
87
/* maximum number of register used for input function arguments */
88
static inline int tcg_target_get_call_iarg_regs_count(int flags)
89
{
90
    return 4;
91
}
92

    
93
/* parse target specific constraints */
94
int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
95
{
96
    const char *ct_str;
97

    
98
    ct_str = *pct_str;
99
    switch (ct_str[0]) {
100
    case 'r':
101
#ifndef CONFIG_SOFTMMU
102
    case 'd':
103
    case 'D':
104
    case 'x':
105
    case 'X':
106
#endif
107
        ct->ct |= TCG_CT_REG;
108
        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
109
        break;
110

    
111
#ifdef CONFIG_SOFTMMU
112
    /* qemu_ld/st inputs (unless 'd', 'D' or 'X') */
113
    case 'x':
114
        ct->ct |= TCG_CT_REG;
115
        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
116
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
117
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
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        break;
119

    
120
    /* qemu_ld/st64 data_reg2 */
121
    case 'D':
122
        ct->ct |= TCG_CT_REG;
123
        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
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        /* r0, r1 and optionally r2 will be overwritten by the address
125
         * and the low word of data, so don't use these.  */
126
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
127
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
128
# if TARGET_LONG_BITS == 64
129
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2);
130
# endif
131
        break;
132

    
133
# if TARGET_LONG_BITS == 64
134
    /* qemu_ld/st addr_reg2 */
135
    case 'X':
136
        ct->ct |= TCG_CT_REG;
137
        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
138
        /* r0 will be overwritten by the low word of base, so don't use it.  */
139
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
140
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
141
        break;
142
# endif
143
#endif
144

    
145
    case '1':
146
        ct->ct |= TCG_CT_REG;
147
        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
148
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
149
        break;
150

    
151
    case '2':
152
        ct->ct |= TCG_CT_REG;
153
        tcg_regset_set32(ct->u.regs, 0, (1 << TCG_TARGET_NB_REGS) - 1);
154
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0);
155
        tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1);
156
        break;
157

    
158
    default:
159
        return -1;
160
    }
161
    ct_str++;
162
    *pct_str = ct_str;
163

    
164
    return 0;
165
}
166

    
167
/* Test if a constant matches the constraint.
168
 * TODO: define constraints for:
169
 *
170
 * ldr/str offset:   between -0xfff and 0xfff
171
 * ldrh/strh offset: between -0xff and 0xff
172
 * mov operand2:     values represented with x << (2 * y), x < 0x100
173
 * add, sub, eor...: ditto
174
 */
175
static inline int tcg_target_const_match(tcg_target_long val,
176
                const TCGArgConstraint *arg_ct)
177
{
178
    int ct;
179
    ct = arg_ct->ct;
180
    if (ct & TCG_CT_CONST)
181
        return 1;
182
    else
183
        return 0;
184
}
185

    
186
enum arm_data_opc_e {
187
    ARITH_AND = 0x0,
188
    ARITH_EOR = 0x1,
189
    ARITH_SUB = 0x2,
190
    ARITH_RSB = 0x3,
191
    ARITH_ADD = 0x4,
192
    ARITH_ADC = 0x5,
193
    ARITH_SBC = 0x6,
194
    ARITH_RSC = 0x7,
195
    ARITH_TST = 0x8,
196
    ARITH_CMP = 0xa,
197
    ARITH_CMN = 0xb,
198
    ARITH_ORR = 0xc,
199
    ARITH_MOV = 0xd,
200
    ARITH_BIC = 0xe,
201
    ARITH_MVN = 0xf,
202
};
203

    
204
#define TO_CPSR(opc) \
205
  ((opc == ARITH_CMP || opc == ARITH_CMN || opc == ARITH_TST) << 20)
206

    
207
#define SHIFT_IMM_LSL(im)        (((im) << 7) | 0x00)
208
#define SHIFT_IMM_LSR(im)        (((im) << 7) | 0x20)
209
#define SHIFT_IMM_ASR(im)        (((im) << 7) | 0x40)
210
#define SHIFT_IMM_ROR(im)        (((im) << 7) | 0x60)
211
#define SHIFT_REG_LSL(rs)        (((rs) << 8) | 0x10)
212
#define SHIFT_REG_LSR(rs)        (((rs) << 8) | 0x30)
213
#define SHIFT_REG_ASR(rs)        (((rs) << 8) | 0x50)
214
#define SHIFT_REG_ROR(rs)        (((rs) << 8) | 0x70)
215

    
216
enum arm_cond_code_e {
217
    COND_EQ = 0x0,
218
    COND_NE = 0x1,
219
    COND_CS = 0x2,        /* Unsigned greater or equal */
220
    COND_CC = 0x3,        /* Unsigned less than */
221
    COND_MI = 0x4,        /* Negative */
222
    COND_PL = 0x5,        /* Zero or greater */
223
    COND_VS = 0x6,        /* Overflow */
224
    COND_VC = 0x7,        /* No overflow */
225
    COND_HI = 0x8,        /* Unsigned greater than */
226
    COND_LS = 0x9,        /* Unsigned less or equal */
227
    COND_GE = 0xa,
228
    COND_LT = 0xb,
229
    COND_GT = 0xc,
230
    COND_LE = 0xd,
231
    COND_AL = 0xe,
232
};
233

    
234
static const uint8_t tcg_cond_to_arm_cond[10] = {
235
    [TCG_COND_EQ] = COND_EQ,
236
    [TCG_COND_NE] = COND_NE,
237
    [TCG_COND_LT] = COND_LT,
238
    [TCG_COND_GE] = COND_GE,
239
    [TCG_COND_LE] = COND_LE,
240
    [TCG_COND_GT] = COND_GT,
241
    /* unsigned */
242
    [TCG_COND_LTU] = COND_CC,
243
    [TCG_COND_GEU] = COND_CS,
244
    [TCG_COND_LEU] = COND_LS,
245
    [TCG_COND_GTU] = COND_HI,
246
};
247

    
248
static inline void tcg_out_bx(TCGContext *s, int cond, int rn)
249
{
250
    tcg_out32(s, (cond << 28) | 0x012fff10 | rn);
251
}
252

    
253
static inline void tcg_out_b(TCGContext *s, int cond, int32_t offset)
254
{
255
    tcg_out32(s, (cond << 28) | 0x0a000000 |
256
                    (((offset - 8) >> 2) & 0x00ffffff));
257
}
258

    
259
static inline void tcg_out_b_noaddr(TCGContext *s, int cond)
260
{
261
#ifdef WORDS_BIGENDIAN
262
    tcg_out8(s, (cond << 4) | 0x0a);
263
    s->code_ptr += 3;
264
#else
265
    s->code_ptr += 3;
266
    tcg_out8(s, (cond << 4) | 0x0a);
267
#endif
268
}
269

    
270
static inline void tcg_out_bl(TCGContext *s, int cond, int32_t offset)
271
{
272
    tcg_out32(s, (cond << 28) | 0x0b000000 |
273
                    (((offset - 8) >> 2) & 0x00ffffff));
274
}
275

    
276
static inline void tcg_out_dat_reg(TCGContext *s,
277
                int cond, int opc, int rd, int rn, int rm, int shift)
278
{
279
    tcg_out32(s, (cond << 28) | (0 << 25) | (opc << 21) | TO_CPSR(opc) |
280
                    (rn << 16) | (rd << 12) | shift | rm);
281
}
282

    
283
static inline void tcg_out_dat_reg2(TCGContext *s,
284
                int cond, int opc0, int opc1, int rd0, int rd1,
285
                int rn0, int rn1, int rm0, int rm1, int shift)
286
{
287
    tcg_out32(s, (cond << 28) | (0 << 25) | (opc0 << 21) | (1 << 20) |
288
                    (rn0 << 16) | (rd0 << 12) | shift | rm0);
289
    tcg_out32(s, (cond << 28) | (0 << 25) | (opc1 << 21) |
290
                    (rn1 << 16) | (rd1 << 12) | shift | rm1);
291
}
292

    
293
static inline void tcg_out_dat_imm(TCGContext *s,
294
                int cond, int opc, int rd, int rn, int im)
295
{
296
    tcg_out32(s, (cond << 28) | (1 << 25) | (opc << 21) | TO_CPSR(opc) |
297
                    (rn << 16) | (rd << 12) | im);
298
}
299

    
300
static inline void tcg_out_movi32(TCGContext *s,
301
                int cond, int rd, int32_t arg)
302
{
303
    int offset = (uint32_t) arg - ((uint32_t) s->code_ptr + 8);
304

    
305
    /* TODO: This is very suboptimal, we can easily have a constant
306
     * pool somewhere after all the instructions.  */
307

    
308
    if (arg < 0 && arg > -0x100)
309
        return tcg_out_dat_imm(s, cond, ARITH_MVN, rd, 0, (~arg) & 0xff);
310

    
311
    if (offset < 0x100 && offset > -0x100)
312
        return offset >= 0 ?
313
                tcg_out_dat_imm(s, cond, ARITH_ADD, rd, 15, offset) :
314
                tcg_out_dat_imm(s, cond, ARITH_SUB, rd, 15, -offset);
315

    
316
    tcg_out_dat_imm(s, cond, ARITH_MOV, rd, 0, arg & 0xff);
317
    if (arg & 0x0000ff00)
318
        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
319
                        ((arg >>  8) & 0xff) | 0xc00);
320
    if (arg & 0x00ff0000)
321
        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
322
                        ((arg >> 16) & 0xff) | 0x800);
323
    if (arg & 0xff000000)
324
        tcg_out_dat_imm(s, cond, ARITH_ORR, rd, rd,
325
                        ((arg >> 24) & 0xff) | 0x400);
326
}
327

    
328
static inline void tcg_out_mul32(TCGContext *s,
329
                int cond, int rd, int rs, int rm)
330
{
331
    if (rd != rm)
332
        tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
333
                        (rs << 8) | 0x90 | rm);
334
    else if (rd != rs)
335
        tcg_out32(s, (cond << 28) | (rd << 16) | (0 << 12) |
336
                        (rm << 8) | 0x90 | rs);
337
    else {
338
        tcg_out32(s, (cond << 28) | ( 8 << 16) | (0 << 12) |
339
                        (rs << 8) | 0x90 | rm);
340
        tcg_out_dat_reg(s, cond, ARITH_MOV,
341
                        rd, 0, 8, SHIFT_IMM_LSL(0));
342
    }
343
}
344

    
345
static inline void tcg_out_umull32(TCGContext *s,
346
                int cond, int rd0, int rd1, int rs, int rm)
347
{
348
    if (rd0 != rm && rd1 != rm)
349
        tcg_out32(s, (cond << 28) | 0x800090 |
350
                        (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
351
    else if (rd0 != rs && rd1 != rs)
352
        tcg_out32(s, (cond << 28) | 0x800090 |
353
                        (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
354
    else {
355
        tcg_out_dat_reg(s, cond, ARITH_MOV,
356
                        TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
357
        tcg_out32(s, (cond << 28) | 0x800098 |
358
                        (rd1 << 16) | (rd0 << 12) | (rs << 8));
359
    }
360
}
361

    
362
static inline void tcg_out_smull32(TCGContext *s,
363
                int cond, int rd0, int rd1, int rs, int rm)
364
{
365
    if (rd0 != rm && rd1 != rm)
366
        tcg_out32(s, (cond << 28) | 0xc00090 |
367
                        (rd1 << 16) | (rd0 << 12) | (rs << 8) | rm);
368
    else if (rd0 != rs && rd1 != rs)
369
        tcg_out32(s, (cond << 28) | 0xc00090 |
370
                        (rd1 << 16) | (rd0 << 12) | (rm << 8) | rs);
371
    else {
372
        tcg_out_dat_reg(s, cond, ARITH_MOV,
373
                        TCG_REG_R8, 0, rm, SHIFT_IMM_LSL(0));
374
        tcg_out32(s, (cond << 28) | 0xc00098 |
375
                        (rd1 << 16) | (rd0 << 12) | (rs << 8));
376
    }
377
}
378

    
379
static inline void tcg_out_ld32_12(TCGContext *s, int cond,
380
                int rd, int rn, tcg_target_long im)
381
{
382
    if (im >= 0)
383
        tcg_out32(s, (cond << 28) | 0x05900000 |
384
                        (rn << 16) | (rd << 12) | (im & 0xfff));
385
    else
386
        tcg_out32(s, (cond << 28) | 0x05100000 |
387
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
388
}
389

    
390
static inline void tcg_out_st32_12(TCGContext *s, int cond,
391
                int rd, int rn, tcg_target_long im)
392
{
393
    if (im >= 0)
394
        tcg_out32(s, (cond << 28) | 0x05800000 |
395
                        (rn << 16) | (rd << 12) | (im & 0xfff));
396
    else
397
        tcg_out32(s, (cond << 28) | 0x05000000 |
398
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
399
}
400

    
401
static inline void tcg_out_ld32_r(TCGContext *s, int cond,
402
                int rd, int rn, int rm)
403
{
404
    tcg_out32(s, (cond << 28) | 0x07900000 |
405
                    (rn << 16) | (rd << 12) | rm);
406
}
407

    
408
static inline void tcg_out_st32_r(TCGContext *s, int cond,
409
                int rd, int rn, int rm)
410
{
411
    tcg_out32(s, (cond << 28) | 0x07800000 |
412
                    (rn << 16) | (rd << 12) | rm);
413
}
414

    
415
/* Register pre-increment with base writeback.  */
416
static inline void tcg_out_ld32_rwb(TCGContext *s, int cond,
417
                int rd, int rn, int rm)
418
{
419
    tcg_out32(s, (cond << 28) | 0x07b00000 |
420
                    (rn << 16) | (rd << 12) | rm);
421
}
422

    
423
static inline void tcg_out_st32_rwb(TCGContext *s, int cond,
424
                int rd, int rn, int rm)
425
{
426
    tcg_out32(s, (cond << 28) | 0x07a00000 |
427
                    (rn << 16) | (rd << 12) | rm);
428
}
429

    
430
static inline void tcg_out_ld16u_8(TCGContext *s, int cond,
431
                int rd, int rn, tcg_target_long im)
432
{
433
    if (im >= 0)
434
        tcg_out32(s, (cond << 28) | 0x01d000b0 |
435
                        (rn << 16) | (rd << 12) |
436
                        ((im & 0xf0) << 4) | (im & 0xf));
437
    else
438
        tcg_out32(s, (cond << 28) | 0x015000b0 |
439
                        (rn << 16) | (rd << 12) |
440
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
441
}
442

    
443
static inline void tcg_out_st16u_8(TCGContext *s, int cond,
444
                int rd, int rn, tcg_target_long im)
445
{
446
    if (im >= 0)
447
        tcg_out32(s, (cond << 28) | 0x01c000b0 |
448
                        (rn << 16) | (rd << 12) |
449
                        ((im & 0xf0) << 4) | (im & 0xf));
450
    else
451
        tcg_out32(s, (cond << 28) | 0x014000b0 |
452
                        (rn << 16) | (rd << 12) |
453
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
454
}
455

    
456
static inline void tcg_out_ld16u_r(TCGContext *s, int cond,
457
                int rd, int rn, int rm)
458
{
459
    tcg_out32(s, (cond << 28) | 0x019000b0 |
460
                    (rn << 16) | (rd << 12) | rm);
461
}
462

    
463
static inline void tcg_out_st16u_r(TCGContext *s, int cond,
464
                int rd, int rn, int rm)
465
{
466
    tcg_out32(s, (cond << 28) | 0x018000b0 |
467
                    (rn << 16) | (rd << 12) | rm);
468
}
469

    
470
static inline void tcg_out_ld16s_8(TCGContext *s, int cond,
471
                int rd, int rn, tcg_target_long im)
472
{
473
    if (im >= 0)
474
        tcg_out32(s, (cond << 28) | 0x01d000f0 |
475
                        (rn << 16) | (rd << 12) |
476
                        ((im & 0xf0) << 4) | (im & 0xf));
477
    else
478
        tcg_out32(s, (cond << 28) | 0x015000f0 |
479
                        (rn << 16) | (rd << 12) |
480
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
481
}
482

    
483
static inline void tcg_out_st16s_8(TCGContext *s, int cond,
484
                int rd, int rn, tcg_target_long im)
485
{
486
    if (im >= 0)
487
        tcg_out32(s, (cond << 28) | 0x01c000f0 |
488
                        (rn << 16) | (rd << 12) |
489
                        ((im & 0xf0) << 4) | (im & 0xf));
490
    else
491
        tcg_out32(s, (cond << 28) | 0x014000f0 |
492
                        (rn << 16) | (rd << 12) |
493
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
494
}
495

    
496
static inline void tcg_out_ld16s_r(TCGContext *s, int cond,
497
                int rd, int rn, int rm)
498
{
499
    tcg_out32(s, (cond << 28) | 0x019000f0 |
500
                    (rn << 16) | (rd << 12) | rm);
501
}
502

    
503
static inline void tcg_out_st16s_r(TCGContext *s, int cond,
504
                int rd, int rn, int rm)
505
{
506
    tcg_out32(s, (cond << 28) | 0x018000f0 |
507
                    (rn << 16) | (rd << 12) | rm);
508
}
509

    
510
static inline void tcg_out_ld8_12(TCGContext *s, int cond,
511
                int rd, int rn, tcg_target_long im)
512
{
513
    if (im >= 0)
514
        tcg_out32(s, (cond << 28) | 0x05d00000 |
515
                        (rn << 16) | (rd << 12) | (im & 0xfff));
516
    else
517
        tcg_out32(s, (cond << 28) | 0x05500000 |
518
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
519
}
520

    
521
static inline void tcg_out_st8_12(TCGContext *s, int cond,
522
                int rd, int rn, tcg_target_long im)
523
{
524
    if (im >= 0)
525
        tcg_out32(s, (cond << 28) | 0x05c00000 |
526
                        (rn << 16) | (rd << 12) | (im & 0xfff));
527
    else
528
        tcg_out32(s, (cond << 28) | 0x05400000 |
529
                        (rn << 16) | (rd << 12) | ((-im) & 0xfff));
530
}
531

    
532
static inline void tcg_out_ld8_r(TCGContext *s, int cond,
533
                int rd, int rn, int rm)
534
{
535
    tcg_out32(s, (cond << 28) | 0x07d00000 |
536
                    (rn << 16) | (rd << 12) | rm);
537
}
538

    
539
static inline void tcg_out_st8_r(TCGContext *s, int cond,
540
                int rd, int rn, int rm)
541
{
542
    tcg_out32(s, (cond << 28) | 0x07c00000 |
543
                    (rn << 16) | (rd << 12) | rm);
544
}
545

    
546
static inline void tcg_out_ld8s_8(TCGContext *s, int cond,
547
                int rd, int rn, tcg_target_long im)
548
{
549
    if (im >= 0)
550
        tcg_out32(s, (cond << 28) | 0x01d000d0 |
551
                        (rn << 16) | (rd << 12) |
552
                        ((im & 0xf0) << 4) | (im & 0xf));
553
    else
554
        tcg_out32(s, (cond << 28) | 0x015000d0 |
555
                        (rn << 16) | (rd << 12) |
556
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
557
}
558

    
559
static inline void tcg_out_st8s_8(TCGContext *s, int cond,
560
                int rd, int rn, tcg_target_long im)
561
{
562
    if (im >= 0)
563
        tcg_out32(s, (cond << 28) | 0x01c000d0 |
564
                        (rn << 16) | (rd << 12) |
565
                        ((im & 0xf0) << 4) | (im & 0xf));
566
    else
567
        tcg_out32(s, (cond << 28) | 0x014000d0 |
568
                        (rn << 16) | (rd << 12) |
569
                        (((-im) & 0xf0) << 4) | ((-im) & 0xf));
570
}
571

    
572
static inline void tcg_out_ld8s_r(TCGContext *s, int cond,
573
                int rd, int rn, int rm)
574
{
575
    tcg_out32(s, (cond << 28) | 0x019000d0 |
576
                    (rn << 16) | (rd << 12) | rm);
577
}
578

    
579
static inline void tcg_out_st8s_r(TCGContext *s, int cond,
580
                int rd, int rn, int rm)
581
{
582
    tcg_out32(s, (cond << 28) | 0x018000d0 |
583
                    (rn << 16) | (rd << 12) | rm);
584
}
585

    
586
static inline void tcg_out_ld32u(TCGContext *s, int cond,
587
                int rd, int rn, int32_t offset)
588
{
589
    if (offset > 0xfff || offset < -0xfff) {
590
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
591
        tcg_out_ld32_r(s, cond, rd, rn, TCG_REG_R8);
592
    } else
593
        tcg_out_ld32_12(s, cond, rd, rn, offset);
594
}
595

    
596
static inline void tcg_out_st32(TCGContext *s, int cond,
597
                int rd, int rn, int32_t offset)
598
{
599
    if (offset > 0xfff || offset < -0xfff) {
600
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
601
        tcg_out_st32_r(s, cond, rd, rn, TCG_REG_R8);
602
    } else
603
        tcg_out_st32_12(s, cond, rd, rn, offset);
604
}
605

    
606
static inline void tcg_out_ld16u(TCGContext *s, int cond,
607
                int rd, int rn, int32_t offset)
608
{
609
    if (offset > 0xff || offset < -0xff) {
610
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
611
        tcg_out_ld16u_r(s, cond, rd, rn, TCG_REG_R8);
612
    } else
613
        tcg_out_ld16u_8(s, cond, rd, rn, offset);
614
}
615

    
616
static inline void tcg_out_ld16s(TCGContext *s, int cond,
617
                int rd, int rn, int32_t offset)
618
{
619
    if (offset > 0xff || offset < -0xff) {
620
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
621
        tcg_out_ld16s_r(s, cond, rd, rn, TCG_REG_R8);
622
    } else
623
        tcg_out_ld16s_8(s, cond, rd, rn, offset);
624
}
625

    
626
static inline void tcg_out_st16u(TCGContext *s, int cond,
627
                int rd, int rn, int32_t offset)
628
{
629
    if (offset > 0xff || offset < -0xff) {
630
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
631
        tcg_out_st16u_r(s, cond, rd, rn, TCG_REG_R8);
632
    } else
633
        tcg_out_st16u_8(s, cond, rd, rn, offset);
634
}
635

    
636
static inline void tcg_out_ld8u(TCGContext *s, int cond,
637
                int rd, int rn, int32_t offset)
638
{
639
    if (offset > 0xfff || offset < -0xfff) {
640
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
641
        tcg_out_ld8_r(s, cond, rd, rn, TCG_REG_R8);
642
    } else
643
        tcg_out_ld8_12(s, cond, rd, rn, offset);
644
}
645

    
646
static inline void tcg_out_ld8s(TCGContext *s, int cond,
647
                int rd, int rn, int32_t offset)
648
{
649
    if (offset > 0xff || offset < -0xff) {
650
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
651
        tcg_out_ld8s_r(s, cond, rd, rn, TCG_REG_R8);
652
    } else
653
        tcg_out_ld8s_8(s, cond, rd, rn, offset);
654
}
655

    
656
static inline void tcg_out_st8u(TCGContext *s, int cond,
657
                int rd, int rn, int32_t offset)
658
{
659
    if (offset > 0xfff || offset < -0xfff) {
660
        tcg_out_movi32(s, cond, TCG_REG_R8, offset);
661
        tcg_out_st8_r(s, cond, rd, rn, TCG_REG_R8);
662
    } else
663
        tcg_out_st8_12(s, cond, rd, rn, offset);
664
}
665

    
666
static inline void tcg_out_goto(TCGContext *s, int cond, uint32_t addr)
667
{
668
    int32_t val;
669

    
670
    val = addr - (tcg_target_long) s->code_ptr;
671
    if (val - 8 < 0x01fffffd && val - 8 > -0x01fffffd)
672
        tcg_out_b(s, cond, val);
673
    else {
674
#if 1
675
        tcg_abort();
676
#else
677
        if (cond == COND_AL) {
678
            tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
679
            tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
680
        } else {
681
            tcg_out_movi32(s, cond, TCG_REG_R8, val - 8);
682
            tcg_out_dat_reg(s, cond, ARITH_ADD,
683
                            15, 15, TCG_REG_R8, SHIFT_IMM_LSL(0));
684
        }
685
#endif
686
    }
687
}
688

    
689
static inline void tcg_out_call(TCGContext *s, int cond, uint32_t addr)
690
{
691
    int32_t val;
692

    
693
#ifdef SAVE_LR
694
    tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
695
#endif
696

    
697
    val = addr - (tcg_target_long) s->code_ptr;
698
    if (val < 0x01fffffd && val > -0x01fffffd)
699
        tcg_out_bl(s, cond, val);
700
    else {
701
#if 1
702
        tcg_abort();
703
#else
704
        if (cond == COND_AL) {
705
            tcg_out_dat_imm(s, cond, ARITH_ADD, 14, 15, 4);
706
            tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
707
            tcg_out32(s, addr); /* XXX: This is l->u.value, can we use it? */
708
        } else {
709
            tcg_out_movi32(s, cond, TCG_REG_R9, addr);
710
            tcg_out_dat_imm(s, cond, ARITH_MOV, 14, 0, 15);
711
            tcg_out_bx(s, cond, TCG_REG_R9);
712
        }
713
#endif
714
    }
715

    
716
#ifdef SAVE_LR
717
    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
718
#endif
719
}
720

    
721
static inline void tcg_out_callr(TCGContext *s, int cond, int arg)
722
{
723
#ifdef SAVE_LR
724
    tcg_out_dat_reg(s, cond, ARITH_MOV, TCG_REG_R8, 0, 14, SHIFT_IMM_LSL(0));
725
#endif
726
    /* TODO: on ARMv5 and ARMv6 replace with tcg_out_blx(s, cond, arg);  */
727
    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 15, SHIFT_IMM_LSL(0));
728
    tcg_out_bx(s, cond, arg);
729
#ifdef SAVE_LR
730
    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, TCG_REG_R8, SHIFT_IMM_LSL(0));
731
#endif
732
}
733

    
734
static inline void tcg_out_goto_label(TCGContext *s, int cond, int label_index)
735
{
736
    TCGLabel *l = &s->labels[label_index];
737

    
738
    if (l->has_value)
739
        tcg_out_goto(s, cond, l->u.value);
740
    else if (cond == COND_AL) {
741
        tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
742
        tcg_out_reloc(s, s->code_ptr, R_ARM_ABS32, label_index, 31337);
743
        s->code_ptr += 4;
744
    } else {
745
        /* Probably this should be preferred even for COND_AL... */
746
        tcg_out_reloc(s, s->code_ptr, R_ARM_PC24, label_index, 31337);
747
        tcg_out_b_noaddr(s, cond);
748
    }
749
}
750

    
751
static void tcg_out_div_helper(TCGContext *s, int cond, const TCGArg *args,
752
                void *helper_div, void *helper_rem, int shift)
753
{
754
    int div_reg = args[0];
755
    int rem_reg = args[1];
756

    
757
    /* stmdb sp!, { r0 - r3, ip, lr } */
758
    /* (Note that we need an even number of registers as per EABI) */
759
    tcg_out32(s, (cond << 28) | 0x092d500f);
760

    
761
    tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
762
    tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
763
    tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
764
    tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
765

    
766
    tcg_out_call(s, cond, (uint32_t) helper_div);
767
    tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 0, SHIFT_IMM_LSL(0));
768

    
769
    /* ldmia sp, { r0 - r3, fp, lr } */
770
    tcg_out32(s, (cond << 28) | 0x089d500f);
771

    
772
    tcg_out_dat_reg(s, cond, ARITH_MOV, 0, 0, args[2], SHIFT_IMM_LSL(0));
773
    tcg_out_dat_reg(s, cond, ARITH_MOV, 1, 0, args[3], SHIFT_IMM_LSL(0));
774
    tcg_out_dat_reg(s, cond, ARITH_MOV, 2, 0, args[4], SHIFT_IMM_LSL(0));
775
    tcg_out_dat_reg(s, cond, ARITH_MOV, 3, 0, 2, shift);
776

    
777
    tcg_out_call(s, cond, (uint32_t) helper_rem);
778

    
779
    tcg_out_dat_reg(s, cond, ARITH_MOV, rem_reg, 0, 0, SHIFT_IMM_LSL(0));
780
    tcg_out_dat_reg(s, cond, ARITH_MOV, div_reg, 0, 8, SHIFT_IMM_LSL(0));
781

    
782
    /* ldr r0, [sp], #4 */
783
    if (rem_reg != 0 && div_reg != 0)
784
        tcg_out32(s, (cond << 28) | 0x04bd0004);
785
    /* ldr r1, [sp], #4 */
786
    if (rem_reg != 1 && div_reg != 1)
787
        tcg_out32(s, (cond << 28) | 0x04bd1004);
788
    /* ldr r2, [sp], #4 */
789
    if (rem_reg != 2 && div_reg != 2)
790
        tcg_out32(s, (cond << 28) | 0x04bd2004);
791
    /* ldr r3, [sp], #4 */
792
    if (rem_reg != 3 && div_reg != 3)
793
        tcg_out32(s, (cond << 28) | 0x04bd3004);
794
    /* ldr ip, [sp], #4 */
795
    if (rem_reg != 12 && div_reg != 12)
796
        tcg_out32(s, (cond << 28) | 0x04bdc004);
797
    /* ldr lr, [sp], #4 */
798
    if (rem_reg != 14 && div_reg != 14)
799
        tcg_out32(s, (cond << 28) | 0x04bde004);
800
}
801

    
802
#ifdef CONFIG_SOFTMMU
803
extern void __ldb_mmu(void);
804
extern void __ldw_mmu(void);
805
extern void __ldl_mmu(void);
806
extern void __ldq_mmu(void);
807

    
808
extern void __stb_mmu(void);
809
extern void __stw_mmu(void);
810
extern void __stl_mmu(void);
811
extern void __stq_mmu(void);
812

    
813
static void *qemu_ld_helpers[4] = {
814
    __ldb_mmu,
815
    __ldw_mmu,
816
    __ldl_mmu,
817
    __ldq_mmu,
818
};
819

    
820
static void *qemu_st_helpers[4] = {
821
    __stb_mmu,
822
    __stw_mmu,
823
    __stl_mmu,
824
    __stq_mmu,
825
};
826
#endif
827

    
828
#define TLB_SHIFT        (CPU_TLB_ENTRY_BITS + CPU_TLB_BITS)
829

    
830
static inline void tcg_out_qemu_ld(TCGContext *s, int cond,
831
                const TCGArg *args, int opc)
832
{
833
    int addr_reg, data_reg, data_reg2;
834
#ifdef CONFIG_SOFTMMU
835
    int mem_index, s_bits;
836
# if TARGET_LONG_BITS == 64
837
    int addr_reg2;
838
# endif
839
    uint32_t *label_ptr;
840
#endif
841

    
842
    data_reg = *args++;
843
    if (opc == 3)
844
        data_reg2 = *args++;
845
    else
846
        data_reg2 = 0; /* surpress warning */
847
    addr_reg = *args++;
848
#if TARGET_LONG_BITS == 64
849
    addr_reg2 = *args++;
850
#endif
851
#ifdef CONFIG_SOFTMMU
852
    mem_index = *args;
853
    s_bits = opc & 3;
854

    
855
    /* Should generate something like the following:
856
     *  shr r8, addr_reg, #TARGET_PAGE_BITS
857
     *  and r0, r8, #(CPU_TLB_SIZE - 1)   @ Assumption: CPU_TLB_BITS <= 8
858
     *  add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
859
     */
860
#  if CPU_TLB_BITS > 8
861
#   error
862
#  endif
863
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
864
                    8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
865
    tcg_out_dat_imm(s, COND_AL, ARITH_AND,
866
                    0, 8, CPU_TLB_SIZE - 1);
867
    tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
868
                    0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
869
    /* In the
870
     *  ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_read))]
871
     * below, the offset is likely to exceed 12 bits if mem_index != 0 and
872
     * not exceed otherwise, so use an
873
     *  add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
874
     * before.
875
     */
876
    if (mem_index)
877
        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
878
                        (mem_index << (TLB_SHIFT & 1)) |
879
                        ((16 - (TLB_SHIFT >> 1)) << 8));
880
    tcg_out_ld32_12(s, COND_AL, 1, 0,
881
                    offsetof(CPUState, tlb_table[0][0].addr_read));
882
    tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
883
                    0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
884
    /* Check alignment.  */
885
    if (s_bits)
886
        tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
887
                        0, addr_reg, (1 << s_bits) - 1);
888
#  if TARGET_LONG_BITS == 64
889
    /* XXX: possibly we could use a block data load or writeback in
890
     * the first access.  */
891
    tcg_out_ld32_12(s, COND_EQ, 1, 0,
892
                    offsetof(CPUState, tlb_table[0][0].addr_read) + 4);
893
    tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
894
                    0, 1, addr_reg2, SHIFT_IMM_LSL(0));
895
#  endif
896
    tcg_out_ld32_12(s, COND_EQ, 1, 0,
897
                    offsetof(CPUState, tlb_table[0][0].addend));
898

    
899
    switch (opc) {
900
    case 0:
901
        tcg_out_ld8_r(s, COND_EQ, data_reg, addr_reg, 1);
902
        break;
903
    case 0 | 4:
904
        tcg_out_ld8s_r(s, COND_EQ, data_reg, addr_reg, 1);
905
        break;
906
    case 1:
907
        tcg_out_ld16u_r(s, COND_EQ, data_reg, addr_reg, 1);
908
        break;
909
    case 1 | 4:
910
        tcg_out_ld16s_r(s, COND_EQ, data_reg, addr_reg, 1);
911
        break;
912
    case 2:
913
    default:
914
        tcg_out_ld32_r(s, COND_EQ, data_reg, addr_reg, 1);
915
        break;
916
    case 3:
917
        tcg_out_ld32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
918
        tcg_out_ld32_12(s, COND_EQ, data_reg2, 1, 4);
919
        break;
920
    }
921

    
922
    label_ptr = (void *) s->code_ptr;
923
    tcg_out_b(s, COND_EQ, 8);
924

    
925
# ifdef SAVE_LR
926
    tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
927
# endif
928

    
929
    /* TODO: move this code to where the constants pool will be */
930
    if (addr_reg)
931
        tcg_out_dat_reg(s, cond, ARITH_MOV,
932
                        0, 0, addr_reg, SHIFT_IMM_LSL(0));
933
# if TARGET_LONG_BITS == 32
934
    tcg_out_dat_imm(s, cond, ARITH_MOV, 1, 0, mem_index);
935
# else
936
    if (addr_reg2 != 1)
937
        tcg_out_dat_reg(s, cond, ARITH_MOV,
938
                        1, 0, addr_reg2, SHIFT_IMM_LSL(0));
939
    tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
940
# endif
941
    tcg_out_bl(s, cond, (tcg_target_long) qemu_ld_helpers[s_bits] -
942
                    (tcg_target_long) s->code_ptr);
943

    
944
    switch (opc) {
945
    case 0 | 4:
946
        tcg_out_dat_reg(s, cond, ARITH_MOV,
947
                        0, 0, 0, SHIFT_IMM_LSL(24));
948
        tcg_out_dat_reg(s, cond, ARITH_MOV,
949
                        data_reg, 0, 0, SHIFT_IMM_ASR(24));
950
        break;
951
    case 1 | 4:
952
        tcg_out_dat_reg(s, cond, ARITH_MOV,
953
                        0, 0, 0, SHIFT_IMM_LSL(16));
954
        tcg_out_dat_reg(s, cond, ARITH_MOV,
955
                        data_reg, 0, 0, SHIFT_IMM_ASR(16));
956
        break;
957
    case 0:
958
    case 1:
959
    case 2:
960
    default:
961
        if (data_reg)
962
            tcg_out_dat_reg(s, cond, ARITH_MOV,
963
                            data_reg, 0, 0, SHIFT_IMM_LSL(0));
964
        break;
965
    case 3:
966
        tcg_out_dat_reg(s, cond, ARITH_MOV,
967
                        data_reg, 0, 0, SHIFT_IMM_LSL(0));
968
        if (data_reg2 != 1)
969
            tcg_out_dat_reg(s, cond, ARITH_MOV,
970
                            data_reg2, 0, 1, SHIFT_IMM_LSL(0));
971
        break;
972
    }
973

    
974
# ifdef SAVE_LR
975
    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
976
# endif
977

    
978
    *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
979
#else
980
    switch (opc) {
981
    case 0:
982
        tcg_out_ld8_12(s, COND_AL, data_reg, addr_reg, 0);
983
        break;
984
    case 0 | 4:
985
        tcg_out_ld8s_8(s, COND_AL, data_reg, addr_reg, 0);
986
        break;
987
    case 1:
988
        tcg_out_ld16u_8(s, COND_AL, data_reg, addr_reg, 0);
989
        break;
990
    case 1 | 4:
991
        tcg_out_ld16s_8(s, COND_AL, data_reg, addr_reg, 0);
992
        break;
993
    case 2:
994
    default:
995
        tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
996
        break;
997
    case 3:
998
        /* TODO: use block load */
999
        tcg_out_ld32_12(s, COND_AL, data_reg, addr_reg, 0);
1000
        tcg_out_ld32_12(s, COND_AL, data_reg2, addr_reg, 4);
1001
        break;
1002
    }
1003
#endif
1004
}
1005

    
1006
static inline void tcg_out_qemu_st(TCGContext *s, int cond,
1007
                const TCGArg *args, int opc)
1008
{
1009
    int addr_reg, data_reg, data_reg2;
1010
#ifdef CONFIG_SOFTMMU
1011
    int mem_index, s_bits;
1012
# if TARGET_LONG_BITS == 64
1013
    int addr_reg2;
1014
# endif
1015
    uint32_t *label_ptr;
1016
#endif
1017

    
1018
    data_reg = *args++;
1019
    if (opc == 3)
1020
        data_reg2 = *args++;
1021
    else
1022
        data_reg2 = 0; /* surpress warning */
1023
    addr_reg = *args++;
1024
#if TARGET_LONG_BITS == 64
1025
    addr_reg2 = *args++;
1026
#endif
1027
#ifdef CONFIG_SOFTMMU
1028
    mem_index = *args;
1029
    s_bits = opc & 3;
1030

    
1031
    /* Should generate something like the following:
1032
     *  shr r8, addr_reg, #TARGET_PAGE_BITS
1033
     *  and r0, r8, #(CPU_TLB_SIZE - 1)   @ Assumption: CPU_TLB_BITS <= 8
1034
     *  add r0, env, r0 lsl #CPU_TLB_ENTRY_BITS
1035
     */
1036
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1037
                    8, 0, addr_reg, SHIFT_IMM_LSR(TARGET_PAGE_BITS));
1038
    tcg_out_dat_imm(s, COND_AL, ARITH_AND,
1039
                    0, 8, CPU_TLB_SIZE - 1);
1040
    tcg_out_dat_reg(s, COND_AL, ARITH_ADD,
1041
                    0, TCG_AREG0, 0, SHIFT_IMM_LSL(CPU_TLB_ENTRY_BITS));
1042
    /* In the
1043
     *  ldr r1 [r0, #(offsetof(CPUState, tlb_table[mem_index][0].addr_write))]
1044
     * below, the offset is likely to exceed 12 bits if mem_index != 0 and
1045
     * not exceed otherwise, so use an
1046
     *  add r0, r0, #(mem_index * sizeof *CPUState.tlb_table)
1047
     * before.
1048
     */
1049
    if (mem_index)
1050
        tcg_out_dat_imm(s, COND_AL, ARITH_ADD, 0, 0,
1051
                        (mem_index << (TLB_SHIFT & 1)) |
1052
                        ((16 - (TLB_SHIFT >> 1)) << 8));
1053
    tcg_out_ld32_12(s, COND_AL, 1, 0,
1054
                    offsetof(CPUState, tlb_table[0][0].addr_write));
1055
    tcg_out_dat_reg(s, COND_AL, ARITH_CMP,
1056
                    0, 1, 8, SHIFT_IMM_LSL(TARGET_PAGE_BITS));
1057
    /* Check alignment.  */
1058
    if (s_bits)
1059
        tcg_out_dat_imm(s, COND_EQ, ARITH_TST,
1060
                        0, addr_reg, (1 << s_bits) - 1);
1061
#  if TARGET_LONG_BITS == 64
1062
    /* XXX: possibly we could use a block data load or writeback in
1063
     * the first access.  */
1064
    tcg_out_ld32_12(s, COND_EQ, 1, 0,
1065
                    offsetof(CPUState, tlb_table[0][0].addr_write)
1066
                    + 4);
1067
    tcg_out_dat_reg(s, COND_EQ, ARITH_CMP,
1068
                    0, 1, addr_reg2, SHIFT_IMM_LSL(0));
1069
#  endif
1070
    tcg_out_ld32_12(s, COND_EQ, 1, 0,
1071
                    offsetof(CPUState, tlb_table[0][0].addend));
1072

    
1073
    switch (opc) {
1074
    case 0:
1075
        tcg_out_st8_r(s, COND_EQ, data_reg, addr_reg, 1);
1076
        break;
1077
    case 0 | 4:
1078
        tcg_out_st8s_r(s, COND_EQ, data_reg, addr_reg, 1);
1079
        break;
1080
    case 1:
1081
        tcg_out_st16u_r(s, COND_EQ, data_reg, addr_reg, 1);
1082
        break;
1083
    case 1 | 4:
1084
        tcg_out_st16s_r(s, COND_EQ, data_reg, addr_reg, 1);
1085
        break;
1086
    case 2:
1087
    default:
1088
        tcg_out_st32_r(s, COND_EQ, data_reg, addr_reg, 1);
1089
        break;
1090
    case 3:
1091
        tcg_out_st32_rwb(s, COND_EQ, data_reg, 1, addr_reg);
1092
        tcg_out_st32_12(s, COND_EQ, data_reg2, 1, 4);
1093
        break;
1094
    }
1095

    
1096
    label_ptr = (void *) s->code_ptr;
1097
    tcg_out_b(s, COND_EQ, 8);
1098

    
1099
    /* TODO: move this code to where the constants pool will be */
1100
    if (addr_reg)
1101
        tcg_out_dat_reg(s, cond, ARITH_MOV,
1102
                        0, 0, addr_reg, SHIFT_IMM_LSL(0));
1103
# if TARGET_LONG_BITS == 32
1104
    switch (opc) {
1105
    case 0:
1106
        tcg_out_dat_imm(s, cond, ARITH_AND, 1, data_reg, 0xff);
1107
        tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1108
        break;
1109
    case 1:
1110
        tcg_out_dat_reg(s, cond, ARITH_MOV,
1111
                        1, 0, data_reg, SHIFT_IMM_LSL(16));
1112
        tcg_out_dat_reg(s, cond, ARITH_MOV,
1113
                        1, 0, 1, SHIFT_IMM_LSR(16));
1114
        tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1115
        break;
1116
    case 2:
1117
        if (data_reg != 1)
1118
            tcg_out_dat_reg(s, cond, ARITH_MOV,
1119
                            1, 0, data_reg, SHIFT_IMM_LSL(0));
1120
        tcg_out_dat_imm(s, cond, ARITH_MOV, 2, 0, mem_index);
1121
        break;
1122
    case 3:
1123
        if (data_reg != 1)
1124
            tcg_out_dat_reg(s, cond, ARITH_MOV,
1125
                            1, 0, data_reg, SHIFT_IMM_LSL(0));
1126
        if (data_reg2 != 2)
1127
            tcg_out_dat_reg(s, cond, ARITH_MOV,
1128
                            2, 0, data_reg2, SHIFT_IMM_LSL(0));
1129
        tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1130
        break;
1131
    }
1132
# else
1133
    if (addr_reg2 != 1)
1134
        tcg_out_dat_reg(s, cond, ARITH_MOV,
1135
                        1, 0, addr_reg2, SHIFT_IMM_LSL(0));
1136
    switch (opc) {
1137
    case 0:
1138
        tcg_out_dat_imm(s, cond, ARITH_AND, 2, data_reg, 0xff);
1139
        tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1140
        break;
1141
    case 1:
1142
        tcg_out_dat_reg(s, cond, ARITH_MOV,
1143
                        2, 0, data_reg, SHIFT_IMM_LSL(16));
1144
        tcg_out_dat_reg(s, cond, ARITH_MOV,
1145
                        2, 0, 2, SHIFT_IMM_LSR(16));
1146
        tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1147
        break;
1148
    case 2:
1149
        if (data_reg != 2)
1150
            tcg_out_dat_reg(s, cond, ARITH_MOV,
1151
                            2, 0, data_reg, SHIFT_IMM_LSL(0));
1152
        tcg_out_dat_imm(s, cond, ARITH_MOV, 3, 0, mem_index);
1153
        break;
1154
    case 3:
1155
        tcg_out_dat_imm(s, cond, ARITH_MOV, 8, 0, mem_index);
1156
        tcg_out32(s, (cond << 28) | 0x052d8010); /* str r8, [sp, #-0x10]! */
1157
        if (data_reg != 2)
1158
            tcg_out_dat_reg(s, cond, ARITH_MOV,
1159
                            2, 0, data_reg, SHIFT_IMM_LSL(0));
1160
        if (data_reg2 != 3)
1161
            tcg_out_dat_reg(s, cond, ARITH_MOV,
1162
                            3, 0, data_reg2, SHIFT_IMM_LSL(0));
1163
        break;
1164
    }
1165
# endif
1166

    
1167
# ifdef SAVE_LR
1168
    tcg_out_dat_reg(s, cond, ARITH_MOV, 8, 0, 14, SHIFT_IMM_LSL(0));
1169
# endif
1170

    
1171
    tcg_out_bl(s, cond, (tcg_target_long) qemu_st_helpers[s_bits] -
1172
                    (tcg_target_long) s->code_ptr);
1173

    
1174
# if TARGET_LONG_BITS == 64
1175
    if (opc == 3)
1176
        tcg_out_dat_imm(s, cond, ARITH_ADD, 13, 13, 0x10);
1177
# endif
1178

    
1179
# ifdef SAVE_LR
1180
    tcg_out_dat_reg(s, cond, ARITH_MOV, 14, 0, 8, SHIFT_IMM_LSL(0));
1181
# endif
1182

    
1183
    *label_ptr += ((void *) s->code_ptr - (void *) label_ptr - 8) >> 2;
1184
#else
1185
    switch (opc) {
1186
    case 0:
1187
        tcg_out_st8_12(s, COND_AL, data_reg, addr_reg, 0);
1188
        break;
1189
    case 0 | 4:
1190
        tcg_out_st8s_8(s, COND_AL, data_reg, addr_reg, 0);
1191
        break;
1192
    case 1:
1193
        tcg_out_st16u_8(s, COND_AL, data_reg, addr_reg, 0);
1194
        break;
1195
    case 1 | 4:
1196
        tcg_out_st16s_8(s, COND_AL, data_reg, addr_reg, 0);
1197
        break;
1198
    case 2:
1199
    default:
1200
        tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1201
        break;
1202
    case 3:
1203
        /* TODO: use block store */
1204
        tcg_out_st32_12(s, COND_AL, data_reg, addr_reg, 0);
1205
        tcg_out_st32_12(s, COND_AL, data_reg2, addr_reg, 4);
1206
        break;
1207
    }
1208
#endif
1209
}
1210

    
1211
static uint8_t *tb_ret_addr;
1212

    
1213
static inline void tcg_out_op(TCGContext *s, int opc,
1214
                const TCGArg *args, const int *const_args)
1215
{
1216
    int c;
1217

    
1218
    switch (opc) {
1219
    case INDEX_op_exit_tb:
1220
#ifdef SAVE_LR
1221
        if (args[0] >> 8)
1222
            tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1223
        else
1224
            tcg_out_dat_imm(s, COND_AL, ARITH_MOV, TCG_REG_R0, 0, args[0]);
1225
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV, 15, 0, 14, SHIFT_IMM_LSL(0));
1226
        if (args[0] >> 8)
1227
            tcg_out32(s, args[0]);
1228
#else
1229
        if (args[0] >> 8)
1230
            tcg_out_ld32_12(s, COND_AL, 0, 15, 0);
1231
        else
1232
            tcg_out_dat_imm(s, COND_AL, ARITH_MOV, 0, 0, args[0]);
1233
        tcg_out_goto(s, COND_AL, (tcg_target_ulong) tb_ret_addr);
1234
        if (args[0] >> 8)
1235
            tcg_out32(s, args[0]);
1236
#endif
1237
        break;
1238
    case INDEX_op_goto_tb:
1239
        if (s->tb_jmp_offset) {
1240
            /* Direct jump method */
1241
#if 1
1242
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1243
            tcg_out_b(s, COND_AL, 8);
1244
#else
1245
            tcg_out_ld32_12(s, COND_AL, 15, 15, -4);
1246
            s->tb_jmp_offset[args[0]] = s->code_ptr - s->code_buf;
1247
            tcg_out32(s, 0);
1248
#endif
1249
        } else {
1250
            /* Indirect jump method */
1251
#if 1
1252
            c = (int) (s->tb_next + args[0]) - ((int) s->code_ptr + 8);
1253
            if (c > 0xfff || c < -0xfff) {
1254
                tcg_out_movi32(s, COND_AL, TCG_REG_R0,
1255
                                (tcg_target_long) (s->tb_next + args[0]));
1256
                tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1257
            } else
1258
                tcg_out_ld32_12(s, COND_AL, 15, 15, c);
1259
#else
1260
            tcg_out_ld32_12(s, COND_AL, TCG_REG_R0, 15, 0);
1261
            tcg_out_ld32_12(s, COND_AL, 15, TCG_REG_R0, 0);
1262
            tcg_out32(s, (tcg_target_long) (s->tb_next + args[0]));
1263
#endif
1264
        }
1265
        s->tb_next_offset[args[0]] = s->code_ptr - s->code_buf;
1266
        break;
1267
    case INDEX_op_call:
1268
        if (const_args[0])
1269
            tcg_out_call(s, COND_AL, args[0]);
1270
        else
1271
            tcg_out_callr(s, COND_AL, args[0]);
1272
        break;
1273
    case INDEX_op_jmp:
1274
        if (const_args[0])
1275
            tcg_out_goto(s, COND_AL, args[0]);
1276
        else
1277
            tcg_out_bx(s, COND_AL, args[0]);
1278
        break;
1279
    case INDEX_op_br:
1280
        tcg_out_goto_label(s, COND_AL, args[0]);
1281
        break;
1282

    
1283
    case INDEX_op_ld8u_i32:
1284
        tcg_out_ld8u(s, COND_AL, args[0], args[1], args[2]);
1285
        break;
1286
    case INDEX_op_ld8s_i32:
1287
        tcg_out_ld8s(s, COND_AL, args[0], args[1], args[2]);
1288
        break;
1289
    case INDEX_op_ld16u_i32:
1290
        tcg_out_ld16u(s, COND_AL, args[0], args[1], args[2]);
1291
        break;
1292
    case INDEX_op_ld16s_i32:
1293
        tcg_out_ld16s(s, COND_AL, args[0], args[1], args[2]);
1294
        break;
1295
    case INDEX_op_ld_i32:
1296
        tcg_out_ld32u(s, COND_AL, args[0], args[1], args[2]);
1297
        break;
1298
    case INDEX_op_st8_i32:
1299
        tcg_out_st8u(s, COND_AL, args[0], args[1], args[2]);
1300
        break;
1301
    case INDEX_op_st16_i32:
1302
        tcg_out_st16u(s, COND_AL, args[0], args[1], args[2]);
1303
        break;
1304
    case INDEX_op_st_i32:
1305
        tcg_out_st32(s, COND_AL, args[0], args[1], args[2]);
1306
        break;
1307

    
1308
    case INDEX_op_mov_i32:
1309
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1310
                        args[0], 0, args[1], SHIFT_IMM_LSL(0));
1311
        break;
1312
    case INDEX_op_movi_i32:
1313
        tcg_out_movi32(s, COND_AL, args[0], args[1]);
1314
        break;
1315
    case INDEX_op_add_i32:
1316
        c = ARITH_ADD;
1317
        goto gen_arith;
1318
    case INDEX_op_sub_i32:
1319
        c = ARITH_SUB;
1320
        goto gen_arith;
1321
    case INDEX_op_and_i32:
1322
        c = ARITH_AND;
1323
        goto gen_arith;
1324
    case INDEX_op_or_i32:
1325
        c = ARITH_ORR;
1326
        goto gen_arith;
1327
    case INDEX_op_xor_i32:
1328
        c = ARITH_EOR;
1329
        /* Fall through.  */
1330
    gen_arith:
1331
        tcg_out_dat_reg(s, COND_AL, c,
1332
                        args[0], args[1], args[2], SHIFT_IMM_LSL(0));
1333
        break;
1334
    case INDEX_op_add2_i32:
1335
        tcg_out_dat_reg2(s, COND_AL, ARITH_ADD, ARITH_ADC,
1336
                        args[0], args[1], args[2], args[3],
1337
                        args[4], args[5], SHIFT_IMM_LSL(0));
1338
        break;
1339
    case INDEX_op_sub2_i32:
1340
        tcg_out_dat_reg2(s, COND_AL, ARITH_SUB, ARITH_SBC,
1341
                        args[0], args[1], args[2], args[3],
1342
                        args[4], args[5], SHIFT_IMM_LSL(0));
1343
        break;
1344
    case INDEX_op_neg_i32:
1345
        tcg_out_dat_imm(s, COND_AL, ARITH_RSB, args[0], args[1], 0);
1346
        break;
1347
    case INDEX_op_mul_i32:
1348
        tcg_out_mul32(s, COND_AL, args[0], args[1], args[2]);
1349
        break;
1350
    case INDEX_op_mulu2_i32:
1351
        tcg_out_umull32(s, COND_AL, args[0], args[1], args[2], args[3]);
1352
        break;
1353
    case INDEX_op_div2_i32:
1354
        tcg_out_div_helper(s, COND_AL, args,
1355
                        tcg_helper_div_i64, tcg_helper_rem_i64,
1356
                        SHIFT_IMM_ASR(31));
1357
        break;
1358
    case INDEX_op_divu2_i32:
1359
        tcg_out_div_helper(s, COND_AL, args,
1360
                        tcg_helper_divu_i64, tcg_helper_remu_i64,
1361
                        SHIFT_IMM_LSR(31));
1362
        break;
1363
    /* XXX: Perhaps args[2] & 0x1f is wrong */
1364
    case INDEX_op_shl_i32:
1365
        c = const_args[2] ?
1366
                SHIFT_IMM_LSL(args[2] & 0x1f) : SHIFT_REG_LSL(args[2]);
1367
        goto gen_shift32;
1368
    case INDEX_op_shr_i32:
1369
        c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_LSR(args[2] & 0x1f) :
1370
                SHIFT_IMM_LSL(0) : SHIFT_REG_LSR(args[2]);
1371
        goto gen_shift32;
1372
    case INDEX_op_sar_i32:
1373
        c = const_args[2] ? (args[2] & 0x1f) ? SHIFT_IMM_ASR(args[2] & 0x1f) :
1374
                SHIFT_IMM_LSL(0) : SHIFT_REG_ASR(args[2]);
1375
        /* Fall through.  */
1376
    gen_shift32:
1377
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV, args[0], 0, args[1], c);
1378
        break;
1379

    
1380
    case INDEX_op_brcond_i32:
1381
        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1382
                        args[0], args[1], SHIFT_IMM_LSL(0));
1383
        tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[2]], args[3]);
1384
        break;
1385
    case INDEX_op_brcond2_i32:
1386
        /* The resulting conditions are:
1387
         * TCG_COND_EQ    -->  a0 == a2 && a1 == a3,
1388
         * TCG_COND_NE    --> (a0 != a2 && a1 == a3) ||  a1 != a3,
1389
         * TCG_COND_LT(U) --> (a0 <  a2 && a1 == a3) ||  a1 <  a3,
1390
         * TCG_COND_GE(U) --> (a0 >= a2 && a1 == a3) || (a1 >= a3 && a1 != a3),
1391
         * TCG_COND_LE(U) --> (a0 <= a2 && a1 == a3) || (a1 <= a3 && a1 != a3),
1392
         * TCG_COND_GT(U) --> (a0 >  a2 && a1 == a3) ||  a1 >  a3,
1393
         */
1394
        tcg_out_dat_reg(s, COND_AL, ARITH_CMP, 0,
1395
                        args[1], args[3], SHIFT_IMM_LSL(0));
1396
        tcg_out_dat_reg(s, COND_EQ, ARITH_CMP, 0,
1397
                        args[0], args[2], SHIFT_IMM_LSL(0));
1398
        tcg_out_goto_label(s, tcg_cond_to_arm_cond[args[4]], args[5]);
1399
        break;
1400

    
1401
    case INDEX_op_qemu_ld8u:
1402
        tcg_out_qemu_ld(s, COND_AL, args, 0);
1403
        break;
1404
    case INDEX_op_qemu_ld8s:
1405
        tcg_out_qemu_ld(s, COND_AL, args, 0 | 4);
1406
        break;
1407
    case INDEX_op_qemu_ld16u:
1408
        tcg_out_qemu_ld(s, COND_AL, args, 1);
1409
        break;
1410
    case INDEX_op_qemu_ld16s:
1411
        tcg_out_qemu_ld(s, COND_AL, args, 1 | 4);
1412
        break;
1413
    case INDEX_op_qemu_ld32u:
1414
        tcg_out_qemu_ld(s, COND_AL, args, 2);
1415
        break;
1416
    case INDEX_op_qemu_ld64:
1417
        tcg_out_qemu_ld(s, COND_AL, args, 3);
1418
        break;
1419

    
1420
    case INDEX_op_qemu_st8:
1421
        tcg_out_qemu_st(s, COND_AL, args, 0);
1422
        break;
1423
    case INDEX_op_qemu_st16:
1424
        tcg_out_qemu_st(s, COND_AL, args, 1);
1425
        break;
1426
    case INDEX_op_qemu_st32:
1427
        tcg_out_qemu_st(s, COND_AL, args, 2);
1428
        break;
1429
    case INDEX_op_qemu_st64:
1430
        tcg_out_qemu_st(s, COND_AL, args, 3);
1431
        break;
1432

    
1433
    case INDEX_op_ext8s_i32:
1434
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1435
                        args[0], 0, args[1], SHIFT_IMM_LSL(24));
1436
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1437
                        args[0], 0, args[0], SHIFT_IMM_ASR(24));
1438
        break;
1439
    case INDEX_op_ext16s_i32:
1440
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1441
                        args[0], 0, args[1], SHIFT_IMM_LSL(16));
1442
        tcg_out_dat_reg(s, COND_AL, ARITH_MOV,
1443
                        args[0], 0, args[0], SHIFT_IMM_ASR(16));
1444
        break;
1445

    
1446
    default:
1447
        tcg_abort();
1448
    }
1449
}
1450

    
1451
static const TCGTargetOpDef arm_op_defs[] = {
1452
    { INDEX_op_exit_tb, { } },
1453
    { INDEX_op_goto_tb, { } },
1454
    { INDEX_op_call, { "ri" } },
1455
    { INDEX_op_jmp, { "ri" } },
1456
    { INDEX_op_br, { } },
1457

    
1458
    { INDEX_op_mov_i32, { "r", "r" } },
1459
    { INDEX_op_movi_i32, { "r" } },
1460

    
1461
    { INDEX_op_ld8u_i32, { "r", "r" } },
1462
    { INDEX_op_ld8s_i32, { "r", "r" } },
1463
    { INDEX_op_ld16u_i32, { "r", "r" } },
1464
    { INDEX_op_ld16s_i32, { "r", "r" } },
1465
    { INDEX_op_ld_i32, { "r", "r" } },
1466
    { INDEX_op_st8_i32, { "r", "r" } },
1467
    { INDEX_op_st16_i32, { "r", "r" } },
1468
    { INDEX_op_st_i32, { "r", "r" } },
1469

    
1470
    /* TODO: "r", "r", "ri" */
1471
    { INDEX_op_add_i32, { "r", "r", "r" } },
1472
    { INDEX_op_sub_i32, { "r", "r", "r" } },
1473
    { INDEX_op_mul_i32, { "r", "r", "r" } },
1474
    { INDEX_op_mulu2_i32, { "r", "r", "r", "r" } },
1475
    { INDEX_op_div2_i32, { "r", "r", "r", "1", "2" } },
1476
    { INDEX_op_divu2_i32, { "r", "r", "r", "1", "2" } },
1477
    { INDEX_op_and_i32, { "r", "r", "r" } },
1478
    { INDEX_op_or_i32, { "r", "r", "r" } },
1479
    { INDEX_op_xor_i32, { "r", "r", "r" } },
1480
    { INDEX_op_neg_i32, { "r", "r" } },
1481

    
1482
    { INDEX_op_shl_i32, { "r", "r", "ri" } },
1483
    { INDEX_op_shr_i32, { "r", "r", "ri" } },
1484
    { INDEX_op_sar_i32, { "r", "r", "ri" } },
1485

    
1486
    { INDEX_op_brcond_i32, { "r", "r" } },
1487

    
1488
    /* TODO: "r", "r", "r", "r", "ri", "ri" */
1489
    { INDEX_op_add2_i32, { "r", "r", "r", "r", "r", "r" } },
1490
    { INDEX_op_sub2_i32, { "r", "r", "r", "r", "r", "r" } },
1491
    { INDEX_op_brcond2_i32, { "r", "r", "r", "r" } },
1492

    
1493
    { INDEX_op_qemu_ld8u, { "r", "x", "X" } },
1494
    { INDEX_op_qemu_ld8s, { "r", "x", "X" } },
1495
    { INDEX_op_qemu_ld16u, { "r", "x", "X" } },
1496
    { INDEX_op_qemu_ld16s, { "r", "x", "X" } },
1497
    { INDEX_op_qemu_ld32u, { "r", "x", "X" } },
1498
    { INDEX_op_qemu_ld64, { "x", "r", "x", "X" } },
1499

    
1500
    { INDEX_op_qemu_st8, { "x", "x", "X" } },
1501
    { INDEX_op_qemu_st16, { "x", "x", "X" } },
1502
    { INDEX_op_qemu_st32, { "x", "x", "X" } },
1503
    { INDEX_op_qemu_st64, { "x", "D", "x", "X" } },
1504

    
1505
    { INDEX_op_ext8s_i32, { "r", "r" } },
1506
    { INDEX_op_ext16s_i32, { "r", "r" } },
1507

    
1508
    { -1 },
1509
};
1510

    
1511
void tcg_target_init(TCGContext *s)
1512
{
1513
    /* fail safe */
1514
    if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry))
1515
        tcg_abort();
1516

    
1517
    tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
1518
                    ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8));
1519
    tcg_regset_set32(tcg_target_call_clobber_regs, 0,
1520
                    ((2 << TCG_REG_R3) - 1) |
1521
                    (1 << TCG_REG_R12) | (1 << TCG_REG_R14));
1522

    
1523
    tcg_regset_clear(s->reserved_regs);
1524
#ifdef SAVE_LR
1525
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_R14);
1526
#endif
1527
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
1528
    tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8);
1529

    
1530
    tcg_add_target_add_op_defs(arm_op_defs);
1531
}
1532

    
1533
static inline void tcg_out_ld(TCGContext *s, TCGType type, int arg,
1534
                int arg1, tcg_target_long arg2)
1535
{
1536
    tcg_out_ld32u(s, COND_AL, arg, arg1, arg2);
1537
}
1538

    
1539
static inline void tcg_out_st(TCGContext *s, TCGType type, int arg,
1540
                int arg1, tcg_target_long arg2)
1541
{
1542
    tcg_out_st32(s, COND_AL, arg, arg1, arg2);
1543
}
1544

    
1545
void tcg_out_addi(TCGContext *s, int reg, tcg_target_long val)
1546
{
1547
    if (val > 0)
1548
        if (val < 0x100)
1549
            tcg_out_dat_imm(s, COND_AL, ARITH_ADD, reg, reg, val);
1550
        else
1551
            tcg_abort();
1552
    else if (val < 0) {
1553
        if (val > -0x100)
1554
            tcg_out_dat_imm(s, COND_AL, ARITH_SUB, reg, reg, -val);
1555
        else
1556
            tcg_abort();
1557
    }
1558
}
1559

    
1560
static inline void tcg_out_mov(TCGContext *s, int ret, int arg)
1561
{
1562
    tcg_out_dat_reg(s, COND_AL, ARITH_MOV, ret, 0, arg, SHIFT_IMM_LSL(0));
1563
}
1564

    
1565
static inline void tcg_out_movi(TCGContext *s, TCGType type,
1566
                int ret, tcg_target_long arg)
1567
{
1568
    tcg_out_movi32(s, COND_AL, ret, arg);
1569
}
1570

    
1571
void tcg_target_qemu_prologue(TCGContext *s)
1572
{
1573
    /* stmdb sp!, { r9 - r11, lr } */
1574
    tcg_out32(s, (COND_AL << 28) | 0x092d4e00);
1575

    
1576
    tcg_out_bx(s, COND_AL, TCG_REG_R0);
1577
    tb_ret_addr = s->code_ptr;
1578

    
1579
    /* ldmia sp!, { r9 - r11, pc } */
1580
    tcg_out32(s, (COND_AL << 28) | 0x08bd8e00);
1581
}