root / hw / mips_int.c @ 39d51eb8
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1 | 4de9b249 | ths | #include "vl.h" |
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2 | 4de9b249 | ths | #include "cpu.h" |
3 | 4de9b249 | ths | |
4 | 4de9b249 | ths | /* Raise IRQ to CPU if necessary. It must be called every time the active
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5 | 4de9b249 | ths | IRQ may change */
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6 | 4de9b249 | ths | void cpu_mips_update_irq(CPUState *env)
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7 | 4de9b249 | ths | { |
8 | 4de9b249 | ths | if ((env->CP0_Status & env->CP0_Cause & CP0Ca_IP_mask) &&
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9 | 4de9b249 | ths | (env->CP0_Status & (1 << CP0St_IE)) &&
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10 | 4de9b249 | ths | !(env->hflags & MIPS_HFLAG_EXL) && |
11 | 4de9b249 | ths | !(env->hflags & MIPS_HFLAG_ERL) && |
12 | 4de9b249 | ths | !(env->hflags & MIPS_HFLAG_DM)) { |
13 | 4de9b249 | ths | if (! (env->interrupt_request & CPU_INTERRUPT_HARD)) {
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14 | 4de9b249 | ths | cpu_interrupt(env, CPU_INTERRUPT_HARD); |
15 | 4de9b249 | ths | } |
16 | 4de9b249 | ths | } else {
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17 | 4de9b249 | ths | cpu_reset_interrupt(env, CPU_INTERRUPT_HARD); |
18 | 4de9b249 | ths | } |
19 | 4de9b249 | ths | } |
20 | 4de9b249 | ths | |
21 | 4de9b249 | ths | void cpu_mips_irq_request(void *opaque, int irq, int level) |
22 | 4de9b249 | ths | { |
23 | 39d51eb8 | ths | CPUState *env = (CPUState *)opaque; |
24 | 4de9b249 | ths | |
25 | 39d51eb8 | ths | if (irq < 0 || irq > 7) |
26 | 4de9b249 | ths | return;
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27 | 4de9b249 | ths | |
28 | 4de9b249 | ths | if (level) {
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29 | 39d51eb8 | ths | env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
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30 | 4de9b249 | ths | } else {
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31 | 39d51eb8 | ths | env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
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32 | 4de9b249 | ths | } |
33 | 4de9b249 | ths | cpu_mips_update_irq(env); |
34 | 4de9b249 | ths | } |