root / hw / mips_timer.c @ 39d51eb8
History | View | Annotate | Download (2.3 kB)
1 | e16fe40c | ths | #include "vl.h" |
---|---|---|---|
2 | e16fe40c | ths | |
3 | e16fe40c | ths | void cpu_mips_irqctrl_init (void) |
4 | e16fe40c | ths | { |
5 | e16fe40c | ths | } |
6 | e16fe40c | ths | |
7 | e16fe40c | ths | /* XXX: do not use a global */
|
8 | e16fe40c | ths | uint32_t cpu_mips_get_random (CPUState *env) |
9 | e16fe40c | ths | { |
10 | e16fe40c | ths | static uint32_t seed = 0; |
11 | e16fe40c | ths | uint32_t idx; |
12 | e16fe40c | ths | seed = seed * 314159 + 1; |
13 | e16fe40c | ths | idx = (seed >> 16) % (MIPS_TLB_NB - env->CP0_Wired) + env->CP0_Wired;
|
14 | e16fe40c | ths | return idx;
|
15 | e16fe40c | ths | } |
16 | e16fe40c | ths | |
17 | e16fe40c | ths | /* MIPS R4K timer */
|
18 | e16fe40c | ths | uint32_t cpu_mips_get_count (CPUState *env) |
19 | e16fe40c | ths | { |
20 | e16fe40c | ths | return env->CP0_Count +
|
21 | e16fe40c | ths | (uint32_t)muldiv64(qemu_get_clock(vm_clock), |
22 | e16fe40c | ths | 100 * 1000 * 1000, ticks_per_sec); |
23 | e16fe40c | ths | } |
24 | e16fe40c | ths | |
25 | e16fe40c | ths | static void cpu_mips_update_count (CPUState *env, uint32_t count, |
26 | e16fe40c | ths | uint32_t compare) |
27 | e16fe40c | ths | { |
28 | e16fe40c | ths | uint64_t now, next; |
29 | e16fe40c | ths | uint32_t tmp; |
30 | e16fe40c | ths | |
31 | 39d51eb8 | ths | if (env->CP0_Cause & (1 << CP0Ca_DC)) |
32 | 39d51eb8 | ths | return;
|
33 | 39d51eb8 | ths | |
34 | e16fe40c | ths | tmp = count; |
35 | e16fe40c | ths | if (count == compare)
|
36 | e16fe40c | ths | tmp++; |
37 | e16fe40c | ths | now = qemu_get_clock(vm_clock); |
38 | e16fe40c | ths | next = now + muldiv64(compare - tmp, ticks_per_sec, 100 * 1000 * 1000); |
39 | e16fe40c | ths | if (next == now)
|
40 | e16fe40c | ths | next++; |
41 | e16fe40c | ths | #if 0
|
42 | e16fe40c | ths | if (logfile) {
|
43 | e16fe40c | ths | fprintf(logfile, "%s: 0x%08" PRIx64 " %08x %08x => 0x%08" PRIx64 "\n",
|
44 | e16fe40c | ths | __func__, now, count, compare, next - now);
|
45 | e16fe40c | ths | }
|
46 | e16fe40c | ths | #endif
|
47 | e16fe40c | ths | /* Store new count and compare registers */
|
48 | e16fe40c | ths | env->CP0_Compare = compare; |
49 | e16fe40c | ths | env->CP0_Count = |
50 | e16fe40c | ths | count - (uint32_t)muldiv64(now, 100 * 1000 * 1000, ticks_per_sec); |
51 | e16fe40c | ths | /* Adjust timer */
|
52 | e16fe40c | ths | qemu_mod_timer(env->timer, next); |
53 | e16fe40c | ths | } |
54 | e16fe40c | ths | |
55 | e16fe40c | ths | void cpu_mips_store_count (CPUState *env, uint32_t value)
|
56 | e16fe40c | ths | { |
57 | e16fe40c | ths | cpu_mips_update_count(env, value, env->CP0_Compare); |
58 | e16fe40c | ths | } |
59 | e16fe40c | ths | |
60 | e16fe40c | ths | void cpu_mips_store_compare (CPUState *env, uint32_t value)
|
61 | e16fe40c | ths | { |
62 | e16fe40c | ths | cpu_mips_update_count(env, cpu_mips_get_count(env), value); |
63 | 39d51eb8 | ths | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
64 | 39d51eb8 | ths | env->CP0_Cause &= ~(1 << CP0Ca_TI);
|
65 | 4de9b249 | ths | cpu_mips_irq_request(env, 7, 0); |
66 | e16fe40c | ths | } |
67 | e16fe40c | ths | |
68 | e16fe40c | ths | static void mips_timer_cb (void *opaque) |
69 | e16fe40c | ths | { |
70 | e16fe40c | ths | CPUState *env; |
71 | e16fe40c | ths | |
72 | e16fe40c | ths | env = opaque; |
73 | e16fe40c | ths | #if 0
|
74 | e16fe40c | ths | if (logfile) {
|
75 | e16fe40c | ths | fprintf(logfile, "%s\n", __func__);
|
76 | e16fe40c | ths | }
|
77 | e16fe40c | ths | #endif
|
78 | e16fe40c | ths | cpu_mips_update_count(env, cpu_mips_get_count(env), env->CP0_Compare); |
79 | 39d51eb8 | ths | if ((env->CP0_Config0 & (0x7 << CP0C0_AR)) == (1 << CP0C0_AR)) |
80 | 39d51eb8 | ths | env->CP0_Cause |= 1 << CP0Ca_TI;
|
81 | 4de9b249 | ths | cpu_mips_irq_request(env, 7, 1); |
82 | e16fe40c | ths | } |
83 | e16fe40c | ths | |
84 | e16fe40c | ths | void cpu_mips_clock_init (CPUState *env)
|
85 | e16fe40c | ths | { |
86 | e16fe40c | ths | env->timer = qemu_new_timer(vm_clock, &mips_timer_cb, env); |
87 | e16fe40c | ths | env->CP0_Compare = 0;
|
88 | e16fe40c | ths | cpu_mips_update_count(env, 1, 0); |
89 | e16fe40c | ths | } |