Revision 39d51eb8 hw/mips_int.c
| b/hw/mips_int.c | ||
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void cpu_mips_irq_request(void *opaque, int irq, int level) |
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{
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CPUState *env = first_cpu; |
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uint32_t mask; |
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CPUState *env = (CPUState *)opaque; |
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if (irq >= 16)
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if (irq < 0 || irq > 7)
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return; |
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mask = 1 << (irq + CP0Ca_IP); |
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if (level) {
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env->CP0_Cause |= mask;
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env->CP0_Cause |= 1 << (irq + CP0Ca_IP);
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} else {
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env->CP0_Cause &= ~mask;
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env->CP0_Cause &= ~(1 << (irq +CP0Ca_IP));
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} |
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cpu_mips_update_irq(env); |
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} |
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